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JPH0239130B2 - - Google Patents
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JPH0239130B2 - - Google Patents

Info

Publication number
JPH0239130B2
JPH0239130B2 JP55162128A JP16212880A JPH0239130B2 JP H0239130 B2 JPH0239130 B2 JP H0239130B2 JP 55162128 A JP55162128 A JP 55162128A JP 16212880 A JP16212880 A JP 16212880A JP H0239130 B2 JPH0239130 B2 JP H0239130B2
Authority
JP
Japan
Prior art keywords
signal
terminal
field effect
effect transistor
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55162128A
Other languages
Japanese (ja)
Other versions
JPS5787224A (en
Inventor
Yasushi Fukuhara
Toshio Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyoda Koki KK
Original Assignee
Toyoda Koki KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Koki KK filed Critical Toyoda Koki KK
Priority to JP55162128A priority Critical patent/JPS5787224A/en
Publication of JPS5787224A publication Critical patent/JPS5787224A/en
Publication of JPH0239130B2 publication Critical patent/JPH0239130B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Description

【発明の詳細な説明】 本発明は、非直線的に変化する信号をほぼ直線
的に変化する信号に変換する所謂リニアライザに
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called linearizer that converts a non-linearly varying signal into a substantially linearly varying signal.

一般の半導体圧力変換器においては、加えられ
る圧力の変化に対する出力電圧の変化の割合は第
1図に示すように圧力の増大に伴つて次第に低下
して行き、加えられた圧力の大きさに対する出力
電圧の大きさは直線的に変化しない。
In general semiconductor pressure transducers, the ratio of change in output voltage to change in applied pressure gradually decreases as the pressure increases, as shown in Figure 1, and the output voltage to the magnitude of applied pressure gradually decreases as shown in Figure 1. The magnitude of the voltage does not change linearly.

この印加圧力に対する出力電圧の非直線性が測
定精度に与える影響はそれ程大きくないため、通
常の測定では問題とならないが、測定範囲を広く
取りたい場合もしくは、特に高い測定精度が要求
される場合には、圧力変換器からの出力を直線化
することが行われる。この直線化は、従来、折線
近似によつて信号を直線化するリニアライザを圧
力変換器の出力に接続することによつて行つてい
たが、このものにおいては、圧力変換器の飽和特
性的な出力電圧の変化を高精度に補正するために
は屈曲点を多数設けなければならず、このように
すると回路が著しく複雑になる欠点があつた。
This non-linearity of the output voltage with respect to the applied pressure does not have a large effect on measurement accuracy, so it is not a problem in normal measurements, but it may be useful when you want to widen the measurement range or when particularly high measurement accuracy is required. is done to linearize the output from the pressure transducer. Conventionally, this linearization has been performed by connecting a linearizer to the output of the pressure transducer that linearizes the signal using broken line approximation. In order to accurately correct changes in the output voltage, it is necessary to provide a large number of bending points, which has the disadvantage of significantly complicating the circuit.

本発明はこのような従来の問題点に鑑み、きわ
めて簡単な回路で高精度な直線化が行なえるよう
にしたもので、以下その実施例を図面に基づいて
説明する。
In view of these conventional problems, the present invention enables highly accurate linearization with an extremely simple circuit.Examples of the present invention will be described below with reference to the drawings.

第2図は本発明にかかるリニアライザの基本的
な回路を示すもので、非直線的に変化する入力信
号eiの与えられる入力端子10とアースとの間に
は抵抗R1と電界効果トランジスタFETが直列
に接続されており、抵抗R1と電界効果トランジ
スタFETとの接続点から出力信号eoが出力され
るようになつている。
Figure 2 shows the basic circuit of the linearizer according to the present invention, in which a resistor R1 and a field effect transistor FET are connected in series between the input terminal 10 to which the non-linearly varying input signal ei is applied and the ground. The output signal eo is output from the connection point between the resistor R1 and the field effect transistor FET.

本実施例では、入力端子10に与えられる信号
eiは負の信号であり、このような場合には電界効
果トランジスタFETとしてNチヤンネルのデプ
レツシヨン形のものが使用される。そして、電界
効果トランジスタFETのソース端子Sが抵抗R
1を介して入力端子10に接続されるとともにド
レイン端子Dが接地され、ゲート端子Gは入力端
子10に接続されている。
In this embodiment, the signal applied to the input terminal 10
ei is a negative signal, and in such a case, an N-channel depletion type field effect transistor FET is used. Then, the source terminal S of the field effect transistor FET is connected to the resistor R
1 to the input terminal 10, the drain terminal D is grounded, and the gate terminal G is connected to the input terminal 10.

上記の回路において、電界効果トランジスタ
FETのソース・ドレイン間の抵抗RSDとすると、
出力信号eoは(1)式で表わされるようになり、ま
た電界 eo=RSD/RSD+R1・ei1/1+R1/RSD・ei …(1) 効果トランジスタFETのソース・ドレイン間
の抵抗RSDは第3図に示すように、ゲート端子
Gとソース端子Sの間に印加される負電圧の大き
さに対して2次関数的に増大する。
In the above circuit, the field effect transistor
If the resistance between the source and drain of the FET is RSD, then
The output signal eo is now expressed by equation (1), and the electric field eo = RSD/RSD+R1・ei1/1+R1/RSD・ei...(1) The resistance RSD between the source and drain of the effect transistor FET is shown in Figure 3. As shown, it increases quadratically with respect to the magnitude of the negative voltage applied between the gate terminal G and the source terminal S.

したがつて、(1)式において1/(1+R1/
RSD)を分圧率Kとすれば、この分圧率Kは、
入力端子10に与えられる入力信号eiの絶対値が
小さい時には1に比べてかなり小さな値を取り、
入力信号eiの絶対値が大きくなるに従つて1に近
い値を取るようになり、かつ分圧率は飽和特性的
に変化する。このため、第2図に示すリニアライ
ザの入出力特性は第4図に示すように、入力信号
eiが小さい範囲では入力信号eiの変化に対する出
力信号eoの変化率が小さく、入力信号eiが大きく
なるに従つて変化率が増大する2次関数曲線もし
くは3次関数曲線に近い特性を取る。そして、こ
の特性は、抵抗R1の大きさの変更および電界効
果トランジスタFETの変更により変化でき、測
定圧力等に対する出力信号eoの変化曲線が最も
直線に近づくように抵抗R1および電界効果トラ
ンジスタFETの選択が行われる。
Therefore, in equation (1), 1/(1+R1/
RSD) is the partial pressure ratio K, then this partial pressure ratio K is
When the absolute value of the input signal ei applied to the input terminal 10 is small, it takes a value considerably smaller than 1,
As the absolute value of the input signal ei increases, it takes a value closer to 1, and the voltage division ratio changes in a saturation characteristic. Therefore, the input/output characteristics of the linearizer shown in Fig. 2 are as shown in Fig. 4.
In a range where ei is small, the rate of change of the output signal eo with respect to a change in the input signal ei is small, and as the input signal ei becomes larger, the rate of change increases, taking characteristics close to a quadratic or cubic function curve. This characteristic can be changed by changing the size of the resistor R1 and the field effect transistor FET, and the resistor R1 and the field effect transistor FET are selected so that the change curve of the output signal eo with respect to the measured pressure, etc. approaches the closest to a straight line. will be held.

これにより、出力端子11から出力される信号
eoは、入力信号eiに比べて直線性が改善され、測
定誤差が減少する。
As a result, the signal output from the output terminal 11
eo has improved linearity and reduced measurement errors compared to the input signal ei.

第5図は第2図に示す回路のより実際的な回路
を示すもので、信号入力端子10と電界効果トラ
ンジスタFETとの間が2本の抵抗R1,R2で
接続されているとともに、電界効果トランジスタ
FETと並列に抵抗R3が接続され、抵抗R1と
R2の接続点より出力信号eoを取出すようにな
つている。
FIG. 5 shows a more practical circuit of the circuit shown in FIG. 2, in which the signal input terminal 10 and the field effect transistor FET are connected through two resistors R1 and R2, and transistor
A resistor R3 is connected in parallel with the FET, and an output signal eo is taken out from the connection point between the resistors R1 and R2.

このものにおいては、抵抗R1,R2およびR
3の大きさと抵抗比を変更することにより入力電
圧eiの大きさの変化に対する分圧率Kの変化特性
を大幅に変更できるため、入力信号eiの飽和特性
に最も適した直線化を行うことができ、出力信号
eoの直線性をより向上できる。
In this one, resistors R1, R2 and R
By changing the magnitude of 3 and the resistance ratio, it is possible to significantly change the change characteristics of the voltage division ratio K with respect to changes in the magnitude of the input voltage ei, so it is possible to perform linearization that is most suitable for the saturation characteristics of the input signal ei. can output signal
The linearity of eo can be further improved.

また、第6図に示すように、入力信号eiを抵抗
R4,R5で分圧した電圧を電界効果トランジス
タFETのゲート端子に与えるようにしてもよく、
このようにすれば、抵抗R4とR5の比率を変更
することによつても直線化の特性を変更できる。
このものは、入力信号eiの大きさが大きい場合に
有用である。
Alternatively, as shown in FIG. 6, a voltage obtained by dividing the input signal ei by resistors R4 and R5 may be applied to the gate terminal of the field effect transistor FET.
In this way, the linearization characteristic can also be changed by changing the ratio of resistors R4 and R5.
This is useful when the magnitude of the input signal ei is large.

なお、入力信号が正である場合には電界効果ト
ランジスタFETをPチヤンネルでデブレツシヨ
ン形のものにすればよい。
Note that when the input signal is positive, the field effect transistor FET may be a P-channel depletion type transistor.

以上述べたように、本発明においては、圧力変
換器において、印加圧力が増加するに従つて検出
信号の増加率が次第に低下する非直線的な入力信
号が与えられる入力端子に、抵抗と電界効果トラ
ンジスタとから成る分圧回路を接続し、この分圧
回路によつて入力信号を分圧した電圧を出力信号
として出力するとともに、入力信号の大きさに応
じた電圧を電界効果トランジスタのゲート端子に
与えることによつて電界効果トランジスタの導通
抵抗を変化させ、これによつて分圧回路の分圧比
を入力信号の大きさに応じて変化させて直線化を
行うようにしたものであるから、極めて簡単な回
路で直線化が行なえる上、圧力変換器の検出器に
印加する電圧を変化させて直線化する方法のよう
に検出器に加わる電圧が変化することがないた
め、温度変化に対する感度の補正が行ないやすい
等の利点がある。
As described above, in the present invention, in a pressure transducer, a resistance and an electric field effect are applied to the input terminal to which a non-linear input signal in which the increase rate of the detection signal gradually decreases as the applied pressure increases. A voltage divider circuit consisting of a transistor is connected, and the voltage divided by the input signal is output as an output signal by this voltage divider circuit, and a voltage corresponding to the magnitude of the input signal is applied to the gate terminal of the field effect transistor. This is because the conduction resistance of the field effect transistor is changed by giving a signal, and the voltage dividing ratio of the voltage dividing circuit is thereby changed in accordance with the magnitude of the input signal to perform linearization. Linearization can be performed with a simple circuit, and the voltage applied to the detector does not change, unlike the method of linearization by changing the voltage applied to the detector of a pressure transducer, so the sensitivity to temperature changes is reduced. This has advantages such as ease of correction.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は一般の半導体圧力変換器における印加
圧力と出力電圧の関係を示す図、第2図から第6
図は本発明の実施例を示すもので、第2図は本発
明にかかるリニアライザの構成を示す回路図、第
3図は第2図における電界効果トランジスタの特
性を示す図、第4図は第2図に示す回路の入出力
特性を示す図、第5図および第6図は第2図に示
す回路の変形例を示す図である。 10…入力端子、11…出力端子、FET…電
界効果トランジスタ、R1〜R5…抵抗。
Figure 1 is a diagram showing the relationship between applied pressure and output voltage in a general semiconductor pressure transducer, and Figures 2 to 6
The figures show an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of a linearizer according to the invention, FIG. 3 is a diagram showing the characteristics of the field effect transistor in FIG. 2, and FIG. A diagram showing the input/output characteristics of the circuit shown in FIG. 2, and FIGS. 5 and 6 are diagrams showing modifications of the circuit shown in FIG. 2. 10...Input terminal, 11...Output terminal, FET...Field effect transistor, R1 to R5...Resistor.

Claims (1)

【特許請求の範囲】[Claims] 1 印加圧力が増加するに従つて検出信号の増加
率が次第に低下する非直線的な入力信号を分圧回
路により直線的に変化する出力信号に変換する圧
力変換器用リニアライザであつて、このリニアラ
イザを構成する分圧回路は少なくとも1以上の抵
抗とこの抵抗と直列をなしゲート端子の印加電圧
が増加するに従つて2次関数的にソース、ドレイ
ン間の抵抗が変化する電界効果トランジスタより
構成され、この電界効果トランジスタのソース端
子を前記抵抗を介して前記入力信号が入力される
信号入力端子に接続し、ドレイン端子を基準電位
側に接続し、ゲート端子を前記信号入力端子に接
続し、前記分圧回路の前記抵抗と前記電界効果ト
ランジスタのソース端子間に出力信号を取出す信
号出力端子を接続したことを特徴とする圧力変換
器用リニアライザ。
1 A linearizer for a pressure transducer that converts a nonlinear input signal in which the rate of increase of the detection signal gradually decreases as the applied pressure increases into an output signal that changes linearly using a voltage dividing circuit. The constituent voltage dividing circuit is composed of at least one resistor and a field effect transistor connected in series with the resistor and whose resistance between the source and the drain changes quadratically as the voltage applied to the gate terminal increases, The source terminal of this field effect transistor is connected via the resistor to the signal input terminal into which the input signal is input, the drain terminal is connected to the reference potential side, the gate terminal is connected to the signal input terminal, and the A linearizer for a pressure transducer, characterized in that a signal output terminal for taking out an output signal is connected between the resistor of the pressure circuit and the source terminal of the field effect transistor.
JP55162128A 1980-11-18 1980-11-18 Linearizer Granted JPS5787224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55162128A JPS5787224A (en) 1980-11-18 1980-11-18 Linearizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55162128A JPS5787224A (en) 1980-11-18 1980-11-18 Linearizer

Publications (2)

Publication Number Publication Date
JPS5787224A JPS5787224A (en) 1982-05-31
JPH0239130B2 true JPH0239130B2 (en) 1990-09-04

Family

ID=15748568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55162128A Granted JPS5787224A (en) 1980-11-18 1980-11-18 Linearizer

Country Status (1)

Country Link
JP (1) JPS5787224A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5890177A (en) * 1981-11-25 1983-05-28 Toshiba Corp Reference voltage circuit
US5191279A (en) * 1990-03-15 1993-03-02 Ixys Corporation Current limiting method and apparatus

Also Published As

Publication number Publication date
JPS5787224A (en) 1982-05-31

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