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JPH0239808B2 - - Google Patents
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JPH0239808B2 - - Google Patents

Info

Publication number
JPH0239808B2
JPH0239808B2 JP57222457A JP22245782A JPH0239808B2 JP H0239808 B2 JPH0239808 B2 JP H0239808B2 JP 57222457 A JP57222457 A JP 57222457A JP 22245782 A JP22245782 A JP 22245782A JP H0239808 B2 JPH0239808 B2 JP H0239808B2
Authority
JP
Japan
Prior art keywords
signal
luminance signal
clock
brightness
crt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57222457A
Other languages
Japanese (ja)
Other versions
JPS59112375A (en
Inventor
Sakuyuki Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57222457A priority Critical patent/JPS59112375A/en
Publication of JPS59112375A publication Critical patent/JPS59112375A/en
Publication of JPH0239808B2 publication Critical patent/JPH0239808B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

〔発明の技術分野〕 本発明は、デイスプレイ装置のCRT画面に表
示される像をハードコピーするハードコピー装置
の改良に関する。 〔発明の技術的背景とその問題点〕 従来のこの種の装置は、第1図に示すようにラ
スタスキヤン方式のCRTデイスプレイ装置1と、
この装置1を構成するCRT11の画面に表示さ
れる像をハードコピーするハードコピー装置2と
が設けられている。CRTデイスプレイ装置1は、
外部計算機から送られてくる情報を受信する受信
回路12、この受信情報を記憶するリフレツシユ
メモリ13、このリフレツシユメモリ13の内容
を読取つて輝度信号を発生するキヤラクタ・ジエ
ネレータ14、このジエネレータ14でデータセ
レクトされた輝度信号に基づいてCRT11をラ
スタスキヤンする駆動回路15およびリフレツシ
ユメモリ13に対してリフレツシユ用タイミング
信号として与え、キヤラクタ・ジエネレータ14
に対してデータセレクト用タイミング信号として
与え、また駆動回路15に対してCRT11をス
キヤンするための同期信号として与える信号発生
回路16等を備えている。一方、ハードコピー装
置2は、CRT11に与える輝度信号を記憶する
メモリ21、前記信号発生回路16から出力され
る同期信号と同じタイミングで信号を受けてメモ
リ21に書込みおよび読出指令を与える制御回路
22およびメモリ21より読出した内容をコピー
するコピー装置23等を備えている。 ところで、以上のような構成をとつた場合に
は、次のような欠点がある。即ちCRT11に与
えるべき輝度信号はメモリ21にも書込まれる
が、このメモリ21への書込み周期は通常60nsと
非常に高速であるため、例えばキヤラクタ・ジエ
ネレータ14からメモリ21までの信号線が長か
つたり、信号ノイズ、波形歪、反射波、クロスト
ーク等が存在したりすると、これらの影響を受け
て誤まつた輝度信号をメモリ21に書込んでしま
う。このため、コピー装置23にはCRT11の
像と異なつた像がコピーされてしまう欠点があ
る。 〔発明の目的〕 本発明は上記実情にかんがみてなされたもの
で、CRTに与えるべき輝度信号が多少歪んでい
ても正しい信号に変換してメモリに書込むことに
より、CRTに表示される像を正確にハードコピ
ーするハードコピー装置を提供することにある。 〔発明の概要〕 本発明は、デイスプレイ装置で使用されるタイ
ミング信号からそれぞれ異なる遅れ時間をもつた
複数の遅延クロツク信号を得るとともに、これら
の遅延クロツク信号を用いてCRTに与えるべき
輝度信号を個別にサンプリングした後、多数決論
理によつて論理判断して輝度補正信号を得るハー
ドコピー装置である。 〔発明の実施例〕 第2図は本発明の一実施例を示す図である。
CRTデイスプレイ装置1は第1図のものと同様
であるので、ここではその構成の説明を省略し、
以下、ハードコピー装置3について説明する。こ
のハードコピー装置3は、CRTデイスプレイ装
置1の信号発生回路16から出力される同期信号
と同じタイミングの信号を受けてクロツク信号を
作成して出力する制御回路31と、この制御回路
31から出力されるクロツク信号を受けてキヤラ
クタ・ジエネレータ14からの輝度信号を取込ん
で補正処理を行なうデータ補正回路32と、この
補正後の輝度信号を制御回路31からの指令信号
に基づいて取込んでコピー装置33に送出するメ
モリ34とを備えている。このコピー装置33か
ら制御回路31へはビジー信号が入力されてい
る。 前記データ補正回路32は、第3図に示すよう
にクロツク遅延回路321、複数のD形フリツ
プ・フロツプ322〜324および輝度補正信号
発生回路325を備えている。前記クロツク遅延
回路321は制御回路31からのクロツク信号を
受けてそれぞれ異なつた遅延時間をもつた3種類
の遅延クロツク信号CP1〜CP3を出力する。ま
た前記複数のD形フリツプ・フロツプ322〜3
24は輝度信号Lの入力されているときにクロツ
ク信号CP1〜CP3が入ると立上り、クロツク信
号CP1〜CP3がなくなると立下る機能をもつて
いる。 また、輝度補正信号発生回路325は複数のD
形フリツプ・フロツプ322〜324から出力さ
れる2値信号を論理的に判断して輝度補正信号を
出力するものである。 次に、以上のように構成された装置の作用を説
明する。今、キヤラクタ・ジエネレータ14から
データ補正回路32に入力される輝度信号Lは第
4図に図示点線で示すように例えばクロストーク
等によつて割れたり、歪んだりしているとする。
図中、イは割れた波形、ロは歪波形、ハは輝度信
号Lのセンターをそれぞれ示している。従つて、
輝度信号Lのセンターハでサンプリングしてもデ
ータ誤りとなる危険がある。そこで、信号発生回
路16から制御回路31を経て出力されるクロツ
ク信号CP0を受けてクロツク遅延回路321は、
輝度信号Lのセンターハで立上りエツジとなるよ
うな遅れをもつた遅延クロツク信号CP2を出力
する。さらに、クロツク遅延回路321は、クロ
ツク信号CP2よりも早い時点で立上る遅延クロ
ツク信号CP1およびクロツク信号CP2よりも遅
い時点で立上る遅延クロツク信号CP3をそれぞ
れ作成して出力する。これらの遅延クロツク信号
CP1〜CP3の発生タイミングは第4図に示す通
りである。そして、これらの遅延クロツク信号
CP1〜CP3は、輝度信号Lが入力されている各
フリツプ・フロツプ322〜324のクロツク端
子CPに供給する。従つて、これらのフリツプ・
フロツプ322〜324、つまりサンプリング用
ゲート回路はセンターハの部分の輝度信号とその
前後の輝度信号とそれぞれサンプリングし、第4
図のようなタイミングをもつて信号D1〜D3を
出力することになる。そして、これらの信号D1
〜D3は輝度補正信号発生回路325に入力され
るが、ここでは多数決論理に基づいて信号D1〜
D3を論理判断し、下表に示すような輝度補正信
号L0を得るものである。
[Technical Field of the Invention] The present invention relates to an improvement in a hard copy device for hard copying an image displayed on a CRT screen of a display device. [Technical background of the invention and its problems] As shown in FIG. 1, a conventional device of this type includes a raster scan type CRT display device 1;
A hard copy device 2 for making a hard copy of an image displayed on the screen of a CRT 11 constituting this device 1 is provided. The CRT display device 1 is
A receiving circuit 12 that receives information sent from an external computer, a refresh memory 13 that stores this received information, a character generator 14 that reads the contents of this refresh memory 13 and generates a luminance signal, and this generator 14. It is given as a refresh timing signal to the drive circuit 15 that raster scans the CRT 11 and the refresh memory 13 based on the data selected luminance signal, and is supplied to the character generator 14.
The CRT 11 is provided with a signal generating circuit 16, etc., which is supplied as a timing signal for data selection to the CRT 11, and to the drive circuit 15 as a synchronization signal for scanning the CRT 11. On the other hand, the hard copy device 2 includes a memory 21 that stores a luminance signal given to the CRT 11, and a control circuit 22 that receives a signal at the same timing as the synchronization signal output from the signal generation circuit 16 and gives write and read commands to the memory 21. A copying device 23 for copying the contents read from the memory 21 is also provided. However, the above configuration has the following drawbacks. That is, the luminance signal to be given to the CRT 11 is also written to the memory 21, but since the writing cycle to this memory 21 is usually very fast, 60 ns, for example, the signal line from the character generator 14 to the memory 21 is long and If there is signal noise, waveform distortion, reflected waves, crosstalk, etc., an erroneous luminance signal will be written to the memory 21 due to these influences. Therefore, the copying device 23 has the disadvantage that an image different from the image on the CRT 11 is copied. [Object of the Invention] The present invention has been made in view of the above-mentioned circumstances. Even if the luminance signal to be given to the CRT is slightly distorted, it can be converted into a correct signal and written into the memory, thereby changing the image displayed on the CRT. An object of the present invention is to provide a hard copy device that makes accurate hard copies. [Summary of the Invention] The present invention obtains a plurality of delayed clock signals each having a different delay time from a timing signal used in a display device, and uses these delayed clock signals to individually output a luminance signal to be applied to a CRT. This is a hard copy device that samples the brightness and then makes a logical decision using majority logic to obtain a brightness correction signal. [Embodiment of the Invention] FIG. 2 is a diagram showing an embodiment of the present invention.
Since the CRT display device 1 is the same as that shown in FIG. 1, the explanation of its configuration will be omitted here.
The hard copy device 3 will be explained below. The hard copy device 3 includes a control circuit 31 that receives a signal with the same timing as the synchronization signal output from the signal generation circuit 16 of the CRT display device 1, creates and outputs a clock signal, and a control circuit 31 that generates and outputs a clock signal. A data correction circuit 32 receives a clock signal from the character generator 14, receives a brightness signal from the character generator 14, and performs correction processing, and a data correction circuit 32 receives the brightness signal after correction based on a command signal from the control circuit 31, and processes the brightness signal from the character generator 14. 33 and a memory 34 for sending data to the memory 33. A busy signal is input from the copying device 33 to the control circuit 31 . The data correction circuit 32 includes a clock delay circuit 321, a plurality of D-type flip-flops 322-324, and a brightness correction signal generation circuit 325, as shown in FIG. The clock delay circuit 321 receives the clock signal from the control circuit 31 and outputs three types of delayed clock signals CP1 to CP3, each having a different delay time. Further, the plurality of D-type flip-flops 322 to 3
24 has a function of rising when the clock signals CP1 to CP3 are input while the luminance signal L is being input, and falling when the clock signals CP1 to CP3 disappear. Further, the luminance correction signal generation circuit 325 has a plurality of D
It logically judges the binary signals outputted from the flip-flops 322 to 324 and outputs a brightness correction signal. Next, the operation of the device configured as above will be explained. It is now assumed that the luminance signal L input from the character generator 14 to the data correction circuit 32 is broken or distorted due to, for example, crosstalk, as shown by the dotted line in FIG.
In the figure, A shows a broken waveform, B shows a distorted waveform, and C shows the center of the luminance signal L, respectively. Therefore,
Even if sampling is performed at the center of the luminance signal L, there is a risk of data errors. Therefore, upon receiving the clock signal CP0 outputted from the signal generation circuit 16 via the control circuit 31, the clock delay circuit 321 operates as follows.
A delayed clock signal CP2 having a delay such that a rising edge occurs at the center of the luminance signal L is output. Furthermore, the clock delay circuit 321 creates and outputs a delayed clock signal CP1 that rises earlier than the clock signal CP2, and a delayed clock signal CP3 that rises later than the clock signal CP2. These delayed clock signals
The timing of occurrence of CP1 to CP3 is as shown in FIG. And these delayed clock signals
CP1-CP3 are supplied to the clock terminal CP of each flip-flop 322-324 to which the luminance signal L is input. Therefore, these flip-flops
The flops 322 to 324, that is, the sampling gate circuits sample the luminance signal of the center part and the luminance signals before and after it, respectively, and
Signals D1 to D3 are outputted with the timing shown in the figure. And these signals D1
~D3 are input to the luminance correction signal generation circuit 325, but here, the signals D1~D3 are inputted to the luminance correction signal generation circuit 325, but here, based on majority logic
By logically determining D3, a brightness correction signal L0 as shown in the table below is obtained.

〔発明の効果〕〔Effect of the invention〕

以上詳記したように本発明によれば、CRTデ
イスプレイ装置に使用されているタイミング信号
からそれぞれ異なる遅れ時間をもつた複数のクロ
ツク信号を作成し、このクロツク信号によつて
CRTに供給すべき輝度信号を取込んで論理判断
し輝度補正信号を得るようにしたので、輝度信号
がクロストーク等によつて多少歪んでも歪のない
真の輝度信号を得ることができる。従つて、
CRTの画面に表示される画像を正確にハードコ
ピーできるハードコピー装置を提供できる。
As described in detail above, according to the present invention, a plurality of clock signals each having a different delay time are created from a timing signal used in a CRT display device, and
Since the brightness signal to be supplied to the CRT is taken in and logically judged to obtain a brightness correction signal, a true brightness signal without distortion can be obtained even if the brightness signal is somewhat distorted due to crosstalk or the like. Therefore,
It is possible to provide a hard copy device that can accurately hard copy images displayed on a CRT screen.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来装置の構成図、第2図ないし第4
図は本発明に係るハードコピー装置の一実施例を
示す図であつて、第2図は装置の全体構成図、第
3図は第2図のデータ補正回路の一具体例を示す
構成図、第4図は動作タイミングを示す図、第5
図は本発明の他の例を示す構成図、第6図は第5
図の動作を説明するタイミング図である。 1……CRTデイスプレイ装置、11……
CRT、16……信号発生回路、3……ハードコ
ピー装置、31……制御回路、32……データ補
正回路、33……コピー装置、34……メモリ、
321……クロツク遅延回路、322〜324…
…フリツプ・フロツプ、325……輝度補正信号
発生回路。
Figure 1 is a configuration diagram of the conventional device, Figures 2 to 4
The figures are diagrams showing one embodiment of a hard copy device according to the present invention, in which FIG. 2 is a general configuration diagram of the device, and FIG. 3 is a configuration diagram showing a specific example of the data correction circuit of FIG. 2. Figure 4 is a diagram showing the operation timing, Figure 5
The figure is a configuration diagram showing another example of the present invention, and FIG.
FIG. 3 is a timing diagram illustrating the operation shown in FIG. 1...CRT display device, 11...
CRT, 16...Signal generation circuit, 3...Hard copy device, 31...Control circuit, 32...Data correction circuit, 33...Copy device, 34...Memory,
321...Clock delay circuit, 322-324...
...Flip-flop, 325...Brightness correction signal generation circuit.

Claims (1)

【特許請求の範囲】 1 ラスタスキヤン方式デイスプレイ装置の
CRT画面に表示される表示データに相当する輝
度信号をハードコピーするハードコピー装置にお
いて、 前記デイスプレイ装置の輝度信号をセレクトす
る信号から作成されたクロツク信号を受け、前記
輝度信号のセンターおよびそのセンターの前後で
立ち上がるようなそれぞれ異なる時間遅れをもつ
た複数の遅延クロツク信号を発生するクロツク遅
延手段と、このクロツク遅延手段から発生するそ
れぞれの遅延クロツク信号を用いて前記輝度信号
をサンプリングする複数のサンプリング用ゲート
回路と、これらゲート回路から出力される信号を
多数決論理によつて論理判断して前記輝度信号に
生ずる不要信号を除去して真のレベルの輝度信号
を得る輝度補正手段とを備え、この真のレベルの
輝度信号をコピー装置にコピーすることを特徴と
するハードコピー装置。
[Claims] 1. Raster scan type display device
In a hard copy device that hard copies a luminance signal corresponding to display data displayed on a CRT screen, a clock signal generated from a signal for selecting the luminance signal of the display device is received, and the center of the luminance signal and the center of the luminance signal are selected. A clock delay means for generating a plurality of delayed clock signals having different time delays such that they rise before and after the clock, and a plurality of sampling devices for sampling the luminance signal using respective delayed clock signals generated from the clock delay means. The gate circuit includes a gate circuit, and a brightness correction means that logically judges the signals output from these gate circuits using majority logic to remove unnecessary signals occurring in the brightness signal to obtain a brightness signal at the true level. A hard copy device characterized by copying a luminance signal at a level of 1 to a copy device.
JP57222457A 1982-12-18 1982-12-18 Hard copy device Granted JPS59112375A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57222457A JPS59112375A (en) 1982-12-18 1982-12-18 Hard copy device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57222457A JPS59112375A (en) 1982-12-18 1982-12-18 Hard copy device

Publications (2)

Publication Number Publication Date
JPS59112375A JPS59112375A (en) 1984-06-28
JPH0239808B2 true JPH0239808B2 (en) 1990-09-07

Family

ID=16782709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57222457A Granted JPS59112375A (en) 1982-12-18 1982-12-18 Hard copy device

Country Status (1)

Country Link
JP (1) JPS59112375A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0551519U (en) * 1991-12-12 1993-07-09 富士元工業株式会社 Curved device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6225321A (en) * 1985-07-25 1987-02-03 Yokogawa Electric Corp Video interface device
JPS6257835U (en) * 1985-10-01 1987-04-10

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730475A (en) * 1980-07-31 1982-02-18 Canon Inc Video printer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0551519U (en) * 1991-12-12 1993-07-09 富士元工業株式会社 Curved device

Also Published As

Publication number Publication date
JPS59112375A (en) 1984-06-28

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