JPH0240217B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to structures for forming planarized interconnect leads on integrated circuit devices.

[Conventional technology]

As semiconductor integrated circuit structures become more complex and their functional density increases, there is a need to utilize multi-level interconnects to exploit the inherent operational potential of devices with tighter design rules. It is increasing at an accelerating pace. This multi-level interconnect consists of alternating layers of conductive leads and insulators, which can be patterned accordingly to select the individual electrically active and passive components of the integrated circuit. Individual electrical connections are made between each part.

Although such multi-level interconnect structures pose many challenges to the integrated circuit fabrication process, the cross-sectional area for the metal interconnect leads is generally kept constant and It is desirable that the resistivity of each lead be uniform. Furthermore, due to the step coverage limitations of conventional metal impurity-introduced deposition methods, it is inevitable that the individual lead layers tend to become thinner over the step portions. The extent of this thinning can be alleviated by forming the step sidewall into an inclined surface. The transverse stepped portion of the adherend layer with the sloped surface has conventionally been formed by various methods.
These include, for example, angled lead etching, quartz interlayer insulation using RF bias sputtering, or sputter etching of the insulator to form sidewall facets.

[Problem that the invention seeks to solve]

However, as described above, the method of forming the sidewall into a sloped surface for step coverage requires process control required to form a step-shaped slope, and features of adjacent planar shapes that are close to each other. Because of this, there are restrictions on making the step part an inclined surface.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a structure in which the interconnect lead layer is substantially completely planar in the fabrication of such an interconnect structure, and a method of forming the structure. .

[Means for trying to solve problems]

To achieve these objectives, the present invention provides an interconnect structure that includes layers of conductive plugs alternating with interconnect leads. Among these plugs, a first level plug is brought into contact with a desired portion of the integrated circuit through a contact opening, and an insulating layer is formed around these plugs to planarize the surface of the plug layer. The top surface is substantially flush with the top surface of the insulating layer.
A conductive layer is then deposited on the substantially planar top surface and patterned to form interconnect leads. A layer of insulator is then formed in the areas between these interconnect leads to fill this space and to be flush with the top surface of the conductive interconnect leads. Thus, plugs and interconnect leads can be stacked in alternating layers as required.
The plug electrically interconnects between adjacent interconnect lead layers or between a bottom interconnect lead layer and an integrated circuit. The layers of interdigitated leads formed in this manner are all substantially planar. Further, it may be necessary to form the bottom plugs so that their heights are different from each other so that their upper surfaces are planar. Thus, by using the process of the present invention, the only vias etched through the insulator are those used to facilitate contact between the bottom layer plug and the contact areas of the integrated circuit below. Become.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. First, as shown in FIG.
0 has a contact area 12 on its top surface. This semiconductor circuit board 10 further includes various active and passive elements, and these elements are manufactured using appropriately known methods. However, the illustrated substrate and these elements on this substrate themselves are not constituent elements of the present invention.

An insulating layer 14, preferably made of silicon dioxide, is formed on the substrate 10, and this insulating layer 1
4 can be a substantially thinner layer than oxide layers used in conventional interconnect configurations, such as 500-800 Å or less. The insulating layer 14 is thin enough to provide good step coverage of the overlying conductor at its contact openings and to induce charge carriers on the surface of the semiconductor substrate 10 when the overlying conductor is applied with a predetermined potential. It is thinned as much as possible. Therefore, as described below, additional insulating layers of various thicknesses are formed on the top surface of this insulating layer 14 to provide sufficient insulation between the interconnect leads and the substrate 10 for device operation. Do it like this. The oxide insulating layer 14
A contact opening 16 is etched to make electrical contact with the contact area 12. As mentioned above, this oxide insulating layer 14 is relatively thin, so that the contact opening 16 can be formed with minimal dimensions. For example, the contact opening 16 may have a width of 0.5 microns so that the thin oxide insulating layer substantially or completely eliminates step coverage problems.

Thus, the first plug layer 18 is formed, and there are various methods for forming this. Among these, the preferred method is to
There are methods for forming an adhesion diffusion barrier layer 20 of 500-3000 Å. The adhesion diffusion barrier layer 20 is preferably TiW, but may be formed from other metallic materials as is well known. Then, on this first TiW layer, that is, the adhesion diffusion barrier layer 20,
A conductive layer 22 preferably made of Al and 2% Cu is formed. This conductive layer 22 preferably has a thickness of about 2500-12500 Å, but in any case, the thickness of this conductive layer 22 determines the spacing between the semiconductor circuit board 1 and a first interconnect layer to be described below. becomes. An etch end point detection layer 24 is further formed on the conductive layer 22. The etch end point detection layer 24, which optionally uses TiW, can be formed by plasma etching or reactive ion etching (RIE), selectively etching silicon oxide, and It is necessary that the conductive layer 22 emits optically detectable fluorescence in a mixed gas such as CF ₄ plus O ₂ that has no effect on the conductive layer 22 . In this example, the metal material that meets these standards is
In addition to TiW, for example, Ti, Mo, W, Ta,
There are Nb, V, Hf, etc. The function of this etching end point detection layer 24 will be described later.

The three metal layers 20, 22, and 24 are formed over the entire top surface of the substrate 10, and then patterned and etched in a known manner to form a pattern as shown in FIG. A conductive plug 18 is constructed. In this embodiment, the conductive plug 18 includes a sandwich structure consisting of the three metal layers 20, 22, 24 as described above, but the illustrated plug 18 may be made of, for example, TiW or the metal layers described above, if desired. A metal material suitable for the detection layer at the end of etching may be selected as appropriate, and a single thick layer thereof may be used.

Next, as shown in FIG. 2, an insulating layer 26 is formed on the surface of the structure of the substrate 10 and oxide layer 12. The insulator layer 26 is preferably a silicon dioxide layer and is formed in a manner that provides the same topography as the underlying layer. Such a method is
Chemical vapor deposition from plasma reaction of silane with an oxygen-containing gas such as carbon dioxide or nitrogen oxides, or reaction of silane or tetraethylorthosilicate or other suitable silicon-containing gas with oxygen, or containing both oxygen and silicon. Thermal decomposition of gas is suitable. Note that this insulator layer 26
It is necessary to form this so that its thickness is at least equal to the height of the conductive plug 18.

Next, a planarization layer 28 made of an organic resist is formed on the substrate 10 so as to cover all the undulations of the lower layer and provide a flat upper surface. This can be accomplished using various known techniques for spin coating with photoresist. It is important to select an organic material used for the planarization layer 28 that has substantially the same etch rate as the oxide insulating layer 26.

One method for forming the flattening layer 28 of the organic resist is to apply a positive resist having the same viscosity as OFPR-800-50 (product name), and then hold the semiconductor wafer for 15 to 30 seconds at a temperature of 5,000 to 5000.
Spin at 6000 RPM and then bake the resist at 110-150° C. in air or under vacuum to ensure surface flatness and a consistent etch rate.

Next, as shown in FIG. 3, the laminated structure thus formed is plasma etched to form the conductive plug 1.
Expose 8. The mixed gas used for this plasma etch is adjusted so that the etch rate is equal for both the organic resist planarizing layer 28 and the insulating layer 26. Further, the point at which etching of the etching end point detection layer 24 starts is determined using a plasma emission spectrometer. FIG. 8 shows the change in plasma emission intensity, that is, the fluorescence intensity, with respect to time at a predetermined wavelength. The etching state of the detection layer 24 at the end of etching is as follows:
Any wavelength at which the end-of-etch detection layer 24 emits fluorescence can be used to detect this, in which case a laser tuned to operate at a predetermined fluorescence wavelength can be used to detect signal-to-noise. (S/N) ratio is improved. Thus, when the curve in FIG. 8 reaches its apex, the etching end point detection layer 24 is etched over the entire surface of the chip. This etch process may be stopped at or after the peak of plasma emission from the etch end detection layer 24, but it is preferable to stop it at the drop point indicated by 32 on the curve in FIG. It is preferable to This ensures that all of the plugs 18 are exposed and that etch effects on the conductive layer 22 of the plugs are minimized.

Thus, as shown in FIG. 3, the upper surface 33 of the chip becomes a substantially planar surface. In this case, if the depth of the contact opening 16 is greater than the thickness of the end-etch detection layer 24, a small oxide island 34 will remain at the center of the top surface of the plug 18. In any case, a portion of the end-of-etch detection layer 24 remains on the upper surface of the plug 18 above the contact opening 16. However, plug 1
Since the area of the contact area surrounding the area above the contact opening 16 is sufficient, the island portion 34 and the remaining portion of the etching completion point detection layer 24 have no effect on the operation of the plug 18 itself. Never. It should be noted that since the plug 18 is generally substantially larger than the area of the contact opening 16, the minimum dimensions of the features are not an issue after the contact opening 16 is formed. In addition, in order to prevent the island portion 34 from appearing, the thickness of the etching end point detection layer 24 should be made larger, or the thickness of the insulator layer 14 should be made smaller so that the upper surface of the plug 18 could be prevented from appearing. It is sufficient that only the remaining portion of the etch end detection layer 24 as described above remains in the recessed portion.

Next, as shown in FIG. 4, a third layer preferably includes an adhesive layer 36 of TiW, a conductive layer 38 of Al with 2% Cu added, and an etch completion detection layer 40 of TiW or other metal material. A sandwich-like stacked structure of 2 is formed on the currently planar surface 33 of the chip. in this case,
As previously described for plug 18, if desired, instead of this three-layer laminate structure, one
A layer or two layer structure may also be used. In the case of this embodiment, the above three layers 36, 38, 4
0 is formed and then patterned to form electrokinetic leads 42 as shown. Thereafter, an insulating layer 44, preferably made of an oxide, is formed by the same method as described above so as to match the undulations of the underlying layer (to form a conformal surface), and a flattening layer 46 of an organic resist is further coated on the upper surface thereof. .

Then, as shown in FIG. 5, the chip is etched. This etch process is allowed to proceed until the fluorescence intensity curve of FIG. 8 at a predetermined wavelength indicates the etched state of the detection layer 40 at the end of the etch process. FIG. 5 shows the resulting structure. At this point, the first level conductive interconnect stack is complete, with the oxide of the insulating layer 44 filling between the conductive leads 42. Also, at present, the top surface of the chip is substantially planar over its entire surface.

If a second level conductive interconnect stack is desired to be formed, it is formed on top of the first level conductive interconnect stack in substantially the same manner as described above. For this purpose, the adhesive layer 50, the conductive layer 52, and the etching completion point detection layer 5 are formed in the same manner as described above.
4 is formed on the surface of the chip and then patterned to form a plug. Adhesive layer 50 is preferably also used as an etch stop layer to prevent further etching of the top surface of conductive lead 42. In addition, when the adhesive layer 50 and the etching end point detection layer 54 are each made of TiW, and the conductive layer 52 is made of Al with added Cu, three different types of etching processes are performed using the same mask. Define the plug. Selective etching of TiW over aluminum and oxides is easy to perform, allowing the adhesion layer 50 to be completely etched without further etching the second insulating layer 44 or conductive leads 42. It is possible to do so.

Then, as in the previous case, the third insulating layer 56
After forming it on the chip so as to match the undulations of the underlying layer, a flattening layer 58 made of an organic resist is coated on the top surface. Next, the insulating layer 56 and the planarization layer 58 are subjected to an etchback process. This etch-back process is continued until the plasma emission spectrometer indicates the etch state of the upper plug end-of-etch detection layer 54. FIG. 7 shows the resulting structure. This second plug can be used for interconnection with a second layer of conductive leads (not shown) or can be used as a bond pad. When used as a bond pad in this manner, bonding can be performed above the element forming area of the chip, resulting in a significant reduction in the size of the chip. Additionally, because the top surface of the chip is planar and well supported by the underlying interconnect and insulating layers, bonding above the device formation areas of the chip can be carried out without jeopardizing the integrated circuit. It becomes possible to do so.

It will be apparent to those skilled in the art that the interconnect structure and method of making it as described above has many advantages, but in addition to these advantages, the use of other materials in various locations be able to. For example, instead of constructing all of the plugs and interconnections in a three-layer laminate structure as described above, it is possible to form them from a single-layer or two-layer laminate. Furthermore, polycrystalline silicon can be used instead of aluminum plus copper for the plug and interconnect leads. Further, it is clear that the substrate 10 is suitable for use in laminating a desired number of layers thereon, as long as each layer has a planar surface. Forming such a planar surface also allows for tighter mask alignment when masking interconnect layers.

FIGS. 9-15 now illustrate another embodiment of an interconnect structure according to the present invention, which facilitates connecting first level interconnect leads and second level plugs at approximately the same time. It is designed so that it can be formed. This example further illustrates one method for planarizing the first level interconnect leads when the top surface of the chip used to perform the method according to the invention is not initially planarized. It is something.

Referring first to FIG. 9, an integrated circuit device 60 is similar to device 10 in the previous embodiment, but in this example, the contact area 62 of the integrated circuit device 60 and the contact area 62 above the surface of the integrated circuit device 60 are Electrical coupling is to be made to a polysilicon lead 64 which is provided and separated from the surface by an oxide insulator layer 66. Note that this lead 64 is surrounded by the oxide insulating layer 68.

As shown in FIG. 10, contact openings 70 and 72 are formed in the insulator layer 66, and contact is made with the polysilicon lead 64 and the contact area 62 through these openings. To do this, first, a thin adhesive diffusion barrier layer 74 of TiW or other suitable material is formed over the entire surface of the chip in the same manner as described above, and then a conductive layer 76 of Al with 2% Cu added is placed on the layer. be coated with. This conductive layer 76 must be formed so that it is thicker than the highest part of the undulations of the chip. Next, a planarization layer 78 made of an organic material is formed by spin coating to perform planarization. Next, this chip is subjected to etching treatment in substantially the same manner as described above, thereby forming the planarization layer 78 of the organic resist and the aluminum conductive layer 7.
6 are etched at substantially the same etch rate. This etching process shows that the plasma emission spectral curve shown in FIG. Stop when this is indicated. As previously mentioned, such a point is between the apex of the curve shown in FIG. 8 and point 32. Then the first
As shown in FIG. 1, a second TiW layer is formed as an end-of-etch detection layer 80 on the planar surface of the chip. Note that this may result in a small aluminum plug portion 82 remaining in the illustrated contact opening as part of the conductive layer 76, but this is, of course, completely harmless to the operation.

The chip is then patterned to define plugs 83 for contact openings in each layer, as shown in FIG. As with the previous embodiment, these plugs 84 are typically larger in size than the contact openings 70,72. In this example, a conductive plug extending upward from the polysilicon lead 64 is not provided. An oxide insulator layer 84 having a surface matching the undulations of the underlying layer is then deposited on the chip, followed by a planarization layer 86 of organic resist in the same manner as described above. For the resulting chip, the plasma emission spectrometer shows the etch state of the detection layer 80 at the end of the etch of the plug 84 and directly through the contact opening 72 until it reaches the polysilicon lead 64. Perform etching treatment. At this point, the top surface of the chip is planar.

Then, as shown in FIG. 13, several layers are added on the chip at once. This technique is particularly useful when a plasma deposition reactor can be used that has several different targets and does not require removal of the chips from the reactor vacuum. In the illustrated example, the above several layers include a thin layer of TiW and 2 layers of Al.
It is made by laminating alternately thick layers containing 5% Cu.
Layers 88, 90, 92, 94, and 96 are provided. These layers constitute the first level interconnect leads and the two level plugs.

A suitable resist pattern is then used to define and etch second level plugs 98, as shown in FIG.
Define. After etching these first level interconnect leads 100, a layer of oxide 102 having a surface that matches the topography of the underlying layer is then deposited over the chip, followed by an organic planarization layer 104. be coated with. In this case, as shown in FIG. 14, the mask alignment tolerances for the interconnect level and the upper plug level do not need to be very strict. Furthermore, since there is no step at the bottom of the lead, it is acceptable even if there is an error in mask alignment as long as electrical contact can be made between the plug and the lead.

Next, the organic planarizing layer 104 and the oxide insulating layer 102 are etched until a plasma spectrometer shows the etch state of the upper plug etch completion detection layer 98, as shown in FIG. Get structure. These top plug end-etch detection layers 98 can be used for bonding or to form and connect additional interconnect leads as described above.

Instead of the process of FIGS. 13-15 as described above, another layer of leads may be added immediately after the first planar level is obtained. This allows the interconnect leads above the ridges of the chip, such as polysilicon leads 64 in the illustrated configuration, to be further separated from integrated circuit 10 by an additional oxide layer. .

A problem with creating structures such as those described above is that the planar surface of the metal may act as a mirror surface during the process. This mirror surface makes optically fine mask alignment of photomasks used to define resist layers when forming plugs and interconnect leads extremely difficult. For this reason, it is generally necessary to define some preselected portions of the integrated circuit board 60 with undulations that cannot be flattened by the methods described above. Examples of such undulations include the formation of very deep trenches that cannot be completely filled even if a layer of metal or oxide that matches the underlying undulations is deposited, or the formation of high pillars. is possible. However, it is necessary to use as few of these undulations as possible for each integrated circuit chip so that the sacrifice in surface area utilization is negligible, so as to take advantage of the advantages obtained by the method described above. .

Although various embodiments of the present invention have been described above, it goes without saying that the structure and method according to the present invention may be implemented by adding or modifying these embodiments as appropriate.

[Effect of the invention] As described above, in the present invention, the insulating layer 14,
66 is sufficiently thin so that its contact opening can provide good step coverage to the overlying conductor.
Furthermore, the contact area between the overlying conductor and the substrate can be substantially widened, and the contact resistance can be made sufficiently low.

[Main aspects of the invention]

As described above, the present invention provides planar lead layers in an interconnect structure, with conductive plugs connecting the leads of each layer to each other and connecting the lower lead layer to the integrated circuit. These plugs are formed in desired locations and then an insulating layer is filled between the individual leads, thereby allowing interconnections to be made on the planar surface. Thus, by employing the method according to the invention, the only vias that need to be formed through the oxide layer are those required for the first level plug to contact the integrated circuit device.

In connection with the above description, the following sections are further disclosed.

(1) A structure for interconnecting desired portions of an integrated circuit device, including a plurality of first conductive leads, each of which shares substantially the same plane, and the first conductive leads and the integrated circuit device. An interconnect structure comprising a plurality of first conductive plugs coupled to.

(2) a plurality of second conductive leads, each of which shares substantially the same plane, and a plurality of second conductive plugs coupled to the second conductive leads and the first conductive lead; 2. The interconnect structure according to claim 1, further comprising:

(3) disposed between the second conductive plug and the first and second conductive leads, and further between the first conductive plug and the first conductive lead and the integrated circuit device; 3. The interconnect structure of claim 2 further comprising a plurality of barrier layers disposed therebetween.

4. The interconnect structure of claim 1, wherein the desired portions of the integrated circuit device do not share the same plane, so that the first conductive plugs have different heights.

(5) In fabricating a structure that electrically interconnects desired portions on the surface of an integrated circuit device with each other: a. forming a plurality of conductive plugs extending and each sharing substantially the same plane at a top end spaced from a surface of the integrated circuit device; b. a top surface spaced from a surface of the integrated circuit device; forming a first insulating layer on a surface of the integrated circuit device, the top surface of which is substantially coplanar with the top surface of the plug; c. forming a plurality of leads disposed on the top surface of the first insulating layer.

(6) d A second insulating layer having an upper surface separated from the upper surface of the first insulating layer and having this upper surface formed on substantially the same plane as the upper surface defined by the lead. 6. The method of claim 5, further comprising the step of forming the interconnect structure on the insulating layer.

(7) e: forming a plurality of second plugs, each having an upper end that shares substantially the same plane, and whose lower end is coupled to the plurality of leads; f: an upper end of the second plug; forming a third insulating layer on the second insulating layer and the plurality of leads, the third insulating layer having an upper surface substantially coplanar with the second insulating layer; g. forming a second lead on the third insulating layer; h forming a fourth insulating layer on the third insulating layer having an upper surface substantially coplanar with an upper surface defined by the second lead; 7. The method of claim 6, further comprising forming the interconnect structure on the insulating layer.

8. The method of claim 7, wherein the plug has a barrier layer in contact with a surface of the integrated circuit device and a conductive layer extending from the surface of the integrated circuit device.

(9) In fabricating an integrated circuit device interconnect structure, the steps include: a. forming a plurality of contact openings in desired areas of the integrated circuit device; and b. forming a first contact opening on the surface of the integrated circuit device. c forming a first electrically conductive layer on the first barrier layer; and d forming a first end-of-etch detection layer on the first electrically conductive layer. e. patterning the first end-etch detection layer, the first conductive layer, and the first barrier layer to form a plurality of plugs located over the plurality of contact openings; f forming a first insulating layer on the integrated circuit device and the plug having a thickness at least equal to the height of the plug; and g forming a planarization layer on the first insulating layer. and h the planarization layer and the first insulating layer,
Each surface of the plug is etched until the first etch end point detection layer is exposed, in which case the first planarization layer and the first insulating layer are etched at the same etch rate. forming on the same plane and completely removing the planarization layer; i forming a patterned conductive lead in contact with the plug in the first insulating layer; forming an insulating layer and a second insulating layer over the patterned lead.

10. The interconnect of claim 4, wherein said barrier layer serves as an etch stop, and said first barrier layer and said first conductive layer are patterned by different etching processes. How to make the structure.

(11) k forming a second barrier layer on the first insulating layer and the plug; l forming a second conductive layer on the second barrier layer; m forming the second conductive layer on the second barrier layer; 10. The method of claim 9, further comprising patterning the second barrier layer and the second conductive layer to define patterned conductive leads.

(12) The second barrier layer acts as an etch stop, and the first and second conductive layers are patterned by selective etching on the second barrier layer. 12. The interconnect of claim 11, wherein the second pariah layer is patterned on the first and second conductive layers by selective etching. How to make the structure.

13. The method of manufacturing an interconnect structure according to claim 9, further comprising the step of forming at least one undulation on the integrated circuit device that is not planarized by the planarization layer.

(14) The method for manufacturing an interconnection structure according to item 5, further comprising the step of forming at least one undulating portion that does not share the same plane as the lead.

(15) The method for manufacturing an interconnection structure according to item 7, further comprising the step of forming at least one undulating portion that does not share the same plane as the second lead.

[Brief explanation of drawings]

1 to 7 are cross-sectional views illustrating a stacked structure for fabricating an interconnect structure with substantially planar leads using the method of the present invention, and FIG. 8 shows the fluorescence intensity of an indicator material. FIGS. 9 to 15 are cross-sectional views illustrating a layered structure in which an interconnection structure is fabricated using another embodiment of the method according to the invention. 10,60...Substrate (integrated circuit), 12,62...
Contact area, 14, 66... Insulating film, 16, 70, 7
2... Contact opening, 18, 83, 98... Plug, 2
0, 36, 50, 74...adhesive layer, 22, 38, 5
2, 76... Conductive layer, 24, 40, 54, 80...
End of sex detection layer, 26, 44, 56, 68
...Insulating layer, 42,64,100...Lead.

Claims (1)

Claims: 1. A method of forming interconnects for an integrated circuit device comprising the steps of: a. forming a plurality of contact openings in selected areas of the integrated circuit; b. forming a plurality of contact openings in a surface of the integrated circuit. c forming a first conductive layer on the first barrier layer; d forming a first end point detection layer on the first conductive layer; e patterning the first termination point detection layer, the first conductive layer and the first barrier layer to form a plurality of plugs overlying the plurality of contact openings; f at least over the integrated circuit and the plugs; Step of forming a first insulating layer having the same thickness as the height of the plug; g Forming a planarizing layer on the first insulating layer; h Etching the planarizing layer and the first insulating layer. During the step of exposing the first endpoint detection layer, the etching rate of the planarization layer and the first insulating layer were the same, so that the top surfaces of the plug were coplanar, but i forming patterned conductive leads on the first insulating layer in contact with the plug; j forming the second insulating layer on the first insulating layer; and the process of forming it on the patterned lead. 2. The end point detection layer is a material that emits fluorescence under plasma emission spectroscopy;
2. The method of claim 1, wherein the step of exposing the end point detection layer is performed while monitoring the fluorescence level and is stopped when the fluorescence level reaches a certain level.