JPH0241051B2 - SAIKINCHIHANTEIKAIRO - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a circuit that determines, from among several signal values, a signal value that is closest to a given signal value. There are three digital signals X, A and B,
When determining whether A or B is closer to X, the absolute value of (X-A) |
This can be determined by comparing the magnitude of the absolute value |X-B| of X-A| and (X-B). Conventionally, a circuit that determines which of A and B is closer to X with respect to signal X (hereinafter, a circuit that determines the latest value is referred to as the latest value determination circuit) is |X-A
Comparing the magnitudes of | and |X-B| was achieved by constructing digital circuit elements.
In this case, to calculate |X-A|, a subtraction circuit and an absolute value circuit (for example, if the signal is expressed in two's complement, it can be configured with an exclusive OR circuit and an addition circuit) are required. . Therefore, the nearest value determination circuit configured by comparing the magnitudes of |X-A| and |X-B| requires two subtraction circuits, two absolute value circuits, and one magnitude comparison circuit. This has the disadvantage of increasing the circuit scale. An object of the present invention is to provide a nearest value determination circuit that can easily configure a determination as to which of the two signals A and B has a value closer to the signal X with respect to a given signal X. The present invention uses (2X
-A-B) and a first code signal indicating the positive/negative of (A-B);
The second code signal indicating the positive/negative of B) is obtained, and the circuit includes a means for determining the nearest value from the obtained first and second code signals. According to the present invention, the latest value determination circuit, for example,
The latest value determination circuit can be configured with one addition circuit for determining the sign of (2X-(A+B)) and (A-B), two magnitude comparison circuits, and a gate circuit for determining the latest value from the determined sign. Therefore, the circuit becomes simpler than the conventional circuit configuration in which the determination is made by comparing the magnitudes of |X-A| and |X-B|. Another advantage is that in the method of comparing the magnitudes of |X-A| and |X-B|, the signals of It takes three stages of processing. On the other hand, according to the present invention
For A and B, only the magnitude comparison and gate processing are required, and for A and B, addition, magnitude comparison, and gate processing are required, thereby shortening the processing time and realizing faster calculations. The present invention will be explained in detail below. The magnitude relationship between |X-A| and |X-B| is (X-
A) It matches the magnitude relationship between ² and (X-B) ² . Therefore, if the magnitude relationship between (X-A) ² and (X-B) ² is known, the latest value can be determined. Now function F
Letting F = (X-A) ² - (X-B) ₂ (1) and find the positive, negative, or 0 sign of F, we get |X
It is possible to determine the magnitude of -A| and |X-B|, and therefore it is possible to determine the closest value to X from A and B. If we transform equation (1), we get equation (2). F=(X-A) ² -(X-B) ² =-2(X-A-B)(A-B) =-2(X-A+B/2)(A-B) (2) (2 ) If the sign of (X-A+B/2), that is, (2X-A-B), and the sign of (A-B) are known, the sign of the function F can be determined. For example (X-
If A+B/2)>0 and (A-B)<0, then F=-2(X-A+B/2)(A-B)>0. That is, since |X −A|−|X−B|>0, the nearest value for X is determined to be B. Table 1 shows the sign relationship of the function F of (X-A+B/2) and (A-B), that is, |X-A|-|X-B|, in cases 1 to 9.

[Table] When X-A+B/2 or A-B is 0 (in the case of 2, 4, 5, 6, and 8), the function F=0 and A and B are at the same distance with respect to X. . FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. In this embodiment, signals A and B
The case is shown in which a determination is made on the nearest value of the signal X, and a determination output signal consisting of an S signal indicating magnitude and a Z signal indicating equidistance is output as the determination result. When A is the latest value, S = 0, Z = 0, and when B is the latest value, S = 1, Z = 0,
When A and B are equidistant from X, Z=1 and S is 0
Or it takes a value of 1 and becomes undefined. The digital signal X (for example, a 3-bit signal with a positive value) input to the input terminal 1 of the latest value determination circuit 12 is supplied to the multiplication circuit 4 with a coefficient of 2, and its output is a signal ( 2X). The multiplication circuit 4 having a coefficient of 2 can be constructed by shifting each bit of the input signal upward by one bit. The 4-bit signal (2X) doubled by the multiplier circuit 4 is supplied to the input a terminal 61 of the magnitude comparison circuit 6. The 3-bit signal A having a positive value supplied to the input terminal 2 is supplied to the adder circuit 5 and the input terminal 71 of the magnitude comparison circuit 7. Input terminal 3
The 3-bit signal B having a positive value is supplied to the input terminal 72 of the adder circuit 5 and the magnitude comparison circuit 7.
supplied to Signal A and signal B supplied to the adder circuit 5 are added and the output of the adder circuit 5 is (A+
The 4-bit addition result of B) is output and supplied to the input b terminal 62 of the magnitude comparison circuit 6. The magnitude comparison circuit 6 compares the magnitudes of the natural binary signals of the respective bits inputted to the inputs a and b, and outputs the comparison results to output terminals 63 to 65 according to the magnitude relationship between a and b. When a>b, output terminal 63
Only the output terminals 64 and 65 become high level indicating positive logic 1, and the output terminals 64 and 65 become 0. i.e. 2X−
When (A+B)>0, in other words, X-A+B/2>0, only the output terminal 63 becomes 1. Similarly a=b
That is, when 2X-(A+B)=0, only the output terminal 64 becomes 1, and a<b, that is, 2X-(A+B)<
When the signal is 0, only the output terminal 65 becomes 1. In other words, the output of the magnitude comparison circuit 6 has a positive value of (2X-A-B),
A code signal indicating a negative value or 0 is output. The magnitude comparison circuit 7 performs the same operation as the magnitude comparison circuit 6. In other words, when A-B>0, only the output terminal 73 becomes 1, and when A-B=0, only the output terminal 74 becomes 1. Therefore, when A-B>0, only the output terminal 75 becomes 1. In other words, the magnitude comparison circuit 7 outputs a sign signal indicating whether (A-B) is positive, negative, or 0. The code signal output from the output terminal 63 of the magnitude comparison circuit 6 is supplied to the exclusive OR circuit 8, and the code signal output from the output terminal 64 is supplied to the OR circuit 9. The code signal output from the magnitude comparison circuit 73 is supplied to the exclusive OR circuit 8, and the code signal output from the output terminal 74 is supplied to the OR circuit 9. The exclusive OR circuit 8 outputs a signal S obtained by exclusive ORing the two input signals and supplies it to the output terminal 10. The OR circuit 9 outputs a signal Z obtained by ORing the two input signals and supplies it to the output terminal 11. Signal Z becomes Z=1 when (2X-A-B)(A-B)=0, and (2X-A-B)・(A-B)≠0
When , Z=0. The signal S is (2X-A-B)(A
-B) becomes 1 when <0 (2X-A-B) (A-B)
When >0, it becomes 0. That is, |X−A|<|X−
When A is the most recent value in B|, S=0, Z=0, and |
When X-A|>|X-B| and B is the latest value, S=1,
When Z=0 and |X-A|=|X-B|, when A and B are equidistant from X, Z=1 and S becomes indefinite. Therefore, the determination of the latest value for the signal X can be determined from the signals S and Z output from the output terminals 10 and 11. FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention. In this example, |X−A|=|X−
When B|, it is a case where only the signal S is output, since it does not matter which of the signals A or B is selected as the latest value. The MSB (Most Significant Bit) of the number expressed in two's complement is the Sign
Indicate the positive or negative sign. If the MSB is 0, it indicates a positive number, and if the MSB is 1, it indicates a negative number.
The number 0 has the MSB as 0 and is treated as a positive number. Reference numerals 1, 2, 3, 4, 5, 8 and 10 have the same function as each reference numeral in FIG. Input terminals 1 and 2 of the latest value determination circuit 12 in FIG.
Signals X, A, and B expressed in two's complement numbers are input to 3 and 3, respectively. Signal X is supplied to multiplier circuit 4, and signals A and B are supplied to both adder circuit 5 and subtracter circuit 14, respectively. The signal (2X) output by doubling the input in the multiplication circuit 4 is sent to the subtraction circuit 13
The adder 5 adds the two input signals and outputs the signal (A+B), which is also supplied to the subtraction circuit 13 . The subtraction circuit 13 subtracts the signal (2X) supplied from the multiplication circuit 4 and the signal (A+B) supplied from the addition circuit 5, and outputs the processed signal (2X-A-B). Signal (2X−
The MSB of A-B) indicates the Sign code and the signal (2X-A
-B) is positive, it becomes 0, and when it is negative, it becomes 1.
Signal output from subtraction circuit 13 (2X-A-B)
The MSB of
supplied to In the subtraction circuit 14, the signal A and the signal B
The processing result signal (A-
B) is output. The MSB indicating the sign code of the signal (A-B), that is, the sign signal, is supplied to the exclusive OR circuit 8. The exclusive OR circuit 8 outputs a signal S obtained by exclusive ORing the two input signals and supplies it to the output terminal 10. When the signal S is 0, it indicates that the latest value is A, and when the signal S is 1, it indicates that the latest value is B. Note that in this embodiment, since the determination is made using each MSB (Sign bit) of the signals (2X-A-B) and (A-B), the signal (2X-A-B) and (A-B) are used for determination.
When both A-B) and (A-B) are greater than or equal to 0 or less than 0, the signal S=0, and the signal (2X
-A-B) and (A-B) is 0 or more and the other is less than 0, the signal S=1. In this embodiment, in the first embodiment, a code signal indicating the state a<b outputted from the output 65 of the magnitude comparison circuit 6 and a code signal indicating the state a<b outputted from the output 75 of the magnitude comparison circuit 7 are used. It can also be constructed by taking the exclusive OR of FIG. 3 is a block diagram showing the configuration of a third embodiment of the present invention. In this embodiment, among the signals X, A, and B, the signal A is input with a time delay compared to the signals X and B, and the latest value determination result is output after the signal A is input. It is designed to shorten the time it takes to complete the process. That is, signal A
From input to output, only a magnitude comparison path and gate circuit processing are added. The signal X input to the input terminal 1 is multiplied by 2 in a multiplication circuit 4 having a coefficient of 2, and then supplied to a subtraction circuit 15. The signal A input to the input terminal 2 is supplied to the b input terminal 62 of the magnitude comparison circuit 6 and the input terminal 71 of the magnitude comparison circuit a. The signal B input to the input terminal 3 is sent to the subtraction circuit 15 and the magnitude comparison circuit 7.
is supplied to the input terminal 72 of b. Subtraction circuit 15
Then, subtraction is performed, and the result of the calculation (2X-B) is outputted and supplied to the input terminal a of the magnitude comparison circuit 6. The magnitude comparison circuit 6 compares the magnitudes of the two's complement signals input to a and b, and outputs the result as a code signal. When a>b, that is, (2X-B)-A>0, the output terminal 63 becomes 1 and the other output terminals 64 and 65 become 0. Similarly, when a=b, that is, 2X-B-A=0, output terminal 6
Only 4 becomes 1, and a<b, that is, 2X-B-A
When <0, only the output terminal 65 becomes 1. In other words, the magnitude comparison circuit 6 performs a sign determination of (2X-A-B). The magnitude comparison circuit 7 also determines the magnitude of the signal A and the signal B, that is, the sign of (A-B). When A-B>0, only the output terminal 73 becomes 1, and when A-B, the output terminal 74 only becomes 1. The code signals output from the magnitude comparison circuits 6 and 7 are supplied to an exclusive OR circuit 8 and an OR circuit. The exclusive OR circuit 8 outputs a signal S obtained by exclusive ORing the two input signals and supplies it to the output terminal 10. The OR circuit 9 outputs a signal Z obtained by ORing the two input signals and supplies it to the output terminal 11. Signal Z becomes Z=1 when (2X-A-B)(AB)=0, and becomes Z=0 when (2X-A-B)(AB)≠0. On the other hand, the signal S is (2X-(A-B))
When (A-B) < 0, it becomes 1 (2X-(A+B)) (A
-B) becomes 0 when > 0. That is, when A is the latest value, S = 0, Z = 0, and when B is the latest value, S =
1, Z=0, and when A and B are equidistant from X, Z=1 and S is insufficient. As explained above, according to the present invention, in the nearest value determination circuit that determines which of the two signals A and B has a value closer to the signal X, (2X
- By configuring the nearest value judgment circuit to find the sign of A-B) and the sign of (A-B) and make the nearest value judgment from the obtained sign, the circuit is simpler than the conventional circuit configuration. It is easy to perform, and since the processing time from inputting a signal to outputting a determination result can be shortened, high-speed calculation can be realized. Also, for signal X, N signals greater than 2
The determination of which one of A ₁ , A ₂ ...A _N has the closest value to the signal It is sufficient to determine the magnitude relationship between all the combinations (two combinations of N) using the method of the present invention, and determine the nearest value from the determined magnitude relationship of NC ₂ (the number of two combinations out of N). . With this configuration, each |X−Ai
|However, i is a number from 1 to N)) Compared to the conventional method of calculating the value and then comparing the magnitude, the processing time from inputting a signal to outputting a determination result can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention. FIG. 1, 2, 3, 61, 62, 71 and 72 are input terminals, 10, 11, 63, 64, 65, 73,
74 and 75 are output terminals, 4 is a multiplication circuit, 5 is an addition circuit, 13, 14 and 15 are subtraction circuits, 6
and 7 is a magnitude comparison circuit, 8 is an exclusive OR circuit,
9 is an OR circuit, and 12 is a nearest value determination circuit.

Claims (1)

[Claims] 1. In a circuit that determines which of two signals A and B has a value closer to signal X with respect to signal X, the first sign indicating the positive or negative of (2X-A-B) from signals 1. A latest value determination circuit comprising means for determining a second code signal indicating whether a signal and (A-B) are positive or negative, and determining the latest value from the determined first and second code signals.