JPH0241112B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory device.
In particular, it relates to a sense amplifier for bit line potential in a CMOS random access memory (RAM).

[Technical background of the invention and its problems]

Conventionally, as a sense amplifier for the viratline potential in a CMOS RAM, one using a bipolar transistor as shown in FIG. 1 has been proposed. This circuit applies the high-speed operation characteristics and high sensitivity characteristics of bipolar transistors to CMOS RAM. Darlington-connected NPN type bipolar transistors Q ₁ , Q ₂ and Q ₃ ,
Q ₄ , load resistors R ₁ , R ₂ , resistors R ₃ , R ₄ , a series circuit of NPN type transistor Q ₅ serving as a current source and load resistor R ₆ , and an input terminal connected to the transistor
It consists of a differential amplifier 11 configured as a MOS transistor connected to the collectors of Q ₂ and Q ₄ . The bases of the transistors Q ₁ and Q ₃ have bit lines BL ₁ and
BL ₂ is connected. The differential amplifier 11 is used to match the output signal level to the level of the MOS circuit. For example, if the signal amplitude level of the bit lines BL ₁ and BL ₂ is about 500 mV, this level is the level of the bipolar transistors Q ₁ to _{Q 4} . The output voltage is amplified to about 1.6V by a differential amplifier consisting of a differential amplifier 11, and the output thereof is amplified to about the power supply voltage by a differential amplifier ₁₁ to obtain a differential output OUT1.

In the circuit shown in FIG. 1 above, the Darlington connection is used because the amplitude of the bit lines BL ₁ and BL ₂ is the output of the MOS, and it is not possible to supply a sufficient base current. This is because it is necessary to lower the base currents of the transistors Q ₂ and Q ₄ in order to make them large and to prevent the transistors Q ₂ and Q ₄ from being saturated. In addition, during standby, the current source transistor
By setting the base of _Q5 to a low level and turning off transistor _Q5 , the power consumption of this sense amplifier can be reduced to zero.

FIGS. 2a and 2b show a Darlington-connected differential amplifier and a single-stage differential amplifier. The maximum amplitude of a single stage differential amplifier is Rcie, and the sensitivity i ₁ /i ₂
is expq/k _T (V ₁ − V ₂ )=expqΔV/k _T. Now, for example, if the difference ΔV between the base applied voltages V ₁ and V ₂ of transistors Q ₆ and Q ₇ is 100 mV, then i ₁ /i ₂ = 54, which is equal to the maximum amplitude Rcie with an error of about 2%. . On the other hand, the maximum amplitude in the Darlington-connected differential amplifier shown in Figure a is Rc(ie-
Only Vf/Re) can be taken. Here, Vf is the forward voltage of the PN junction. When analyzing the sensitivity of this circuit, assuming that Re=∞ and the current amplification factor β of each transistor is equal, it is calculated that i ₁ /i ₂ =expq/2kTΔV. Now, as before, ΔV=100mV
Then, i ₁ /i ₂ = 7.1, and in the region where ΔV is large, the output amplitude difference ΔVout is ΔVout = Rcie
(α-1/α+1), so there is hardly any problem, but the sensitivity decreases at low input amplitudes.

If Re is a finite value, for example, Rc=Re=10K
Figure 3 shows the relationship between input voltage and output voltage at Ω, ie = 240 μA. The solid line is the characteristic of the circuit shown in FIG. 2a, and the broken line is the characteristic of the circuit shown in FIG. 2b.
As shown, the circuit of FIG. 2a is inferior to the circuit of FIG. 2b in both sensitivity and amplification factor. However, the second
The circuit shown in Figure b is not suitable as a sense amplifier for CMOS RAM. As mentioned above, for example, when ie=240μA and current amplification factor β=50,
This is because it requires a current of 5 μA and causes a high-level voltage drop on the bit line, causing a lack of power supply voltage margin for the memory itself. Also, if the high level of the bit line potential is BLH, then
This is because there are drawbacks such as the output amplitude being only about Vcc-BLH.

One way to improve these shortcomings is to
As shown in FIG. 4, there are emitter follower currents that flow ie and ie'. In this method, as the input of a differential amplifier consisting of transistors Q ₂ and Q ₄ ,
Since a voltage lowered by Vf determined by ie and ie′ of the bit line potentials V ₁ and V ₂ is applied, the second
Sensitivity and amplification factors comparable to those in Figure b can be obtained. Furthermore, during standby, transistors Q ₈ and Q ₅
By setting the base potential of _Q9 to low level, power consumption can be reduced to zero.

However, in the above configuration, when writing information to the memory cell, the potential V 1 of the bit line BL ₁ connected to the base of the transistor Q 1 is set to the GND level, and the potential V ₁ of the bit line BL ₁ connected to the base of the transistor Q ₃ is set to the GND level. It is necessary to set the potential V ₂ of the line BL ₂ to the V _DD level, and in the process, the transistor Q ₈ becomes saturated. This is not a particularly big problem in a memory composed only of bipolar transistors, but it becomes a cause of latch-up in a CMOS memory. In order to avoid this phenomenon (latch-up), transistor _Q8 can be turned off at the time of writing, but this results in a decrease in the speed of the write-read-write cycle. Furthermore, it is difficult to set the timing of the signal that turns off transistor _Q8 .

[Purpose of the invention]

This invention was made in view of the above-mentioned circumstances, and its purpose is to provide an excellent device with high sensitivity and high performance, which can reduce power consumption to zero during standby mode, and which does not cause any problems during write operations. An object of the present invention is to provide a semiconductor memory device.

[Summary of the invention]

The input terminal of an emitter follower amplifier whose load is a constant current source that acts as a constant current source during operation and is cut off during standby is connected to the bit line of a memory cell that is composed of MOS transistors and stores information. Connect the input end of the emitter-coupled differential amplifier. Furthermore, an amplifier having a MOS transistor configuration is provided at the output end of the differential amplifier to amplify the output level to a MOS signal level.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 5, the same components as those in FIG. 1 are given the same reference numerals, and their explanations will be omitted. In the figure, 12 ₁ , 12 ₂ , ... are static memory cells of CMOS configuration, and these memory cells 1
2 ₁ , 12 ₂ ,... are bit lines BL ₁ , BL ₂ ,...
and the word lines WL ₁ , WL ₂ , . . . 13 is a column transfer gate for transferring signals on bit lines BL ₁ and BL ₂ ;
4 and 15 are MOS transistors; 16 and 17 are MOS transistors that act as constant current sources during operation and as a means to be cut off during standby;
The MOS transistors 16 and 17 are controlled on and off in response to a chip enable signal.

FIG. 6 shows the base drive circuit for transistor _Q5 . The MOS transistor 16,1
7 has a select level of, for example, 5V and a day select level of 0V, so the chip enable signal can be applied to its gate via a two-stage inverter circuit, but transistor _Q5 has a select level of, for example, 1, 2V, Day select level is 0V
Therefore, it is necessary to drive with a level conversion circuit as shown in the figure. Chip enable signal
CE is connected to a P channel type MOS transistor 19 and an N channel type MOS transistor via an inverter circuit 18.
It is supplied to the gate of the MOS transistor 20.
One end of these MOS transistors 19 and 20 is commonly connected, and the other end of the MOS transistor 19 is connected to the MOS transistor ₂₀ through a resistor R9, between the collector and emitter of an NPN transistor _Q10 , and through resistors _R10 and _R11 . connected to the other end.
Between the source and drain of this transistor 20 is
The collector and emitter of the NPN transistor _Q11 are connected in parallel, the base of the transistor _Q11 is connected to the connection point between the resistors _R10 and _R11 , and the base of the transistor _Q10 is connected to the collector of the transistor _Q11 . Ru. Then, a drive signal for transistor _Q5 is output from the emitter of transistor _Q10 .

The operation in the above configuration will be explained. In the case of a read operation, the signals on the bit lines BL ₁ and BL ₂ are transmitted to the sense lines BL _1a and BL _2a via the column transfer gate 13, level shifted and amplified via the emitter follower circuit, and the output is a differential signal. Input to amplifier. The output signal is made to swing fully to the power supply potential using an amplifier to obtain the output signal OUT ₂ .

On the other hand, in the case of a write operation, one of the MOS transistors 14 and 15 is turned on, raising the potential of the bit line to the GND level and the other to the vicinity of V _DD . At this time, for example, the sense line
Although the level of BL _2a may vary from the GND level to the V _DD level, a large amount of reference current flows through the MOS transistor 17 for any of the levels, and no latch-up occurs.

FIG. 7 shows a simulation waveform of the relationship between time and output voltage in the circuit shown in FIG. 5, and is indicated by a broken line. The solid line is a simulation waveform of the circuit shown in FIG. When the address signal AD is input at a predetermined time, the bit line
BL ₁ and BL ₂ (sense lines BL _1a and BL _2a are also almost the same) are shown as BL in the figure. The gradual slope with respect to time is due to the large parasitic capacitance associated with the bit line and sense line.
The waveform at the sense amplifier output is SA ₁ (circuit shown in Figure 5)
and SA ₂ (circuit in Figure 1). The region _t1 is a delay, which is caused by the fact that in the circuit shown in FIG. 1, the sensing sensitivity is particularly poor in the region of low potential difference.

OUT ₁ and OUT ₂ are the respective output waveforms.
The reason why the delay t ₂ is slightly larger than t ₁ is that the output amplitude of the first stage sense amplifier is large and the rise is steep.

FIG. 8 shows another embodiment of this invention,
Only the main parts are shown. That is, in addition to the MOS transistors 16 and 17 in the circuit of FIG. 5, resistors R ₁₂ and R ₁₃ are further provided in series with the transistors 16 and 17. Here, MOS transistors 16 and 17 function as switches that cut off current during standby. And resistance
R ₁₂ and R ₁₃ act as constant current sources. Of course, even in such a configuration, the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain an excellent semiconductor memory device that has high sensitivity and high performance, can consume zero power during standby, and has no problems during write operation.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams for explaining a sense amplifier in a conventional semiconductor memory device, Figure 3 is a diagram showing the input/output characteristics of the circuit in Figure 2, and Figure 4 is a diagram for explaining a conventional bipolar ECL. A diagram showing a circuit, FIG. 5 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention, and FIG.
FIG. 7 is a diagram showing simulation waveforms of the conventional and the present invention, and FIG. 8 is a diagram for explaining another embodiment of the present invention. 11...Amplifier, ₁₂₁ , ₁₂₂ ...Memory cell, 16,17...MOS transistor, _BL1 ,
BL ₂ ... Bit line, Q ₁ to _{Q 5} ... NPN type bipolar transistor.

Claims (1)

[Claims] 1. A memory cell configured with a MOS transistor and storing information, and a bit line of this memory cell connected to an input terminal, which acts as a constant current source during operation and is cut off during standby, as a load. It consists of an emitter follower amplifier, an emitter-coupled differential amplifier whose input terminal is connected to the output terminal of the emitter follower amplifier, and a MOS transistor.
A semiconductor memory device characterized by comprising an amplifier for amplifying to a MOS signal level. 2. The semiconductor memory device according to claim 1, wherein the means that acts as a constant current source during operation and is cut off during standby is comprised of a MOS transistor whose conduction is controlled by a chip enable signal. 3 The means that functions as a constant current source during the above operation and is cut off during standby is a MOS transistor whose conduction is controlled by a chip enable signal, and a MOS transistor whose conduction is controlled by a chip enable signal.
2. The semiconductor memory device according to claim 1, comprising a MOS transistor and a resistor connected in series.