JPH0241230B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides image processing for removing moiré that occurs when scanning halftone photographs for image input devices and facsimile devices that handle binary black and white image data. This invention relates to an image signal processing device for improving the quality of characters and line drawings that have been degraded by image processing.

Conventional technology Conventionally, when obtaining binary image data by scanning a black and white binary image such as a halftone photograph or text/line drawings found on a newspaper, the analog image signal level of the scanned image is set at a certain level. A method was used to compare it with a threshold value and binarize it into a single sheet of paper.

In this single-paper binarization method, interference occurs between the halftone dot period of the halftone photograph and the scanning period of the image scan, resulting in interference fringes called moiré, which impairs image quality.

Recently, a patent application filed in 1983 was published as an effective image signal processing method for removing moiré.
There is a configuration described in the specification of Publication No. 97938.
However, although image signal processing using this configuration has a great effect on removing moiré from halftone photographs, it tends to generate alternating black and white high frequency components in the black and white boundary areas of straight line parts such as characters and line drawings that are parallel to the image scan. The components visually deteriorate the character quality. Figure 7 is an explanatory diagram of a conventional binarized image.
To explain using the example in Figure 7a, the image signal obtained by scanning a binary image in which the inside of thick frame 1 is black with the period of grid 2 is binarized using a threshold of a certain level, and the image is shown in Figure 7b. It will look like frame 3 (black inside).

The moire removal involves image processing so that the black area of the original image and the black area of the binary image signal are locally the same, and this image processing works effectively to remove moire. For an image like thick frame 1, the image after moiré removal processing looks like frame 4 (inner black) shown in Figure 7c, and the alternating black and white pattern in the same figure improves the visual beauty of characters and line drawings. This will impair the quality (smoothness). Therefore, it is necessary to smooth this alternating black and white high frequency component.

Problems to be Solved by the Invention The problem here is that the smoothing process generates new textures such as shading patterns that are not present in the original image in the halftone photographic area, and the corner parts of characters and line drawings. It has the negative effect of curling up.

The present invention is intended to solve the above-mentioned problem, and aims to detect areas that are black and white boundaries of straight line portions of characters and line drawings parallel to image scanning, and to perform partial smoothing processing.

Means for Solving the Problems The present invention performs rescanning on a binary image signal using a scanning window of m×n pixels, removes isolated pixels from the pixels in front of the scanning window, and then A boundary sequence of orthogonal binary image signals is detected and smoothing processing is performed on the boundary sequence. Boundary column detection is performed by detecting the center pixel if one of the plurality of columns sandwiching the pixel at the center of the scanning window is all 1 (or θ) and one of the other plurality of columns is all θ (or 1). The included columns are determined to be boundary columns. This smoothing process is performed on the boundary row, and the central pixel is converted to 1 or θ by majority voting process after weighting. Thereafter, the above object is achieved by removing isolated pixels from pixels behind the scanning window.

Effects According to the above configuration, the present invention detects a boundary row of a binary image signal that is parallel or perpendicular to scanning, and performs smoothing processing only on the boundary row, thereby converting halftone photographs and characters. It is possible to eliminate high-frequency components of alternating black and white in straight line parts, which cause visual deterioration of character quality in binary images containing line drawings.
Moreover, it is designed to prevent image quality deterioration from adversely affecting image parts such as other halftone photographs. In addition, 2
The reason why multiple columns sandwiching the central pixel are used to detect boundary columns of a value image signal is to improve the accuracy of boundary column detection for binary images containing noise. This is so that priority is given to information in the vicinity of the pixel of interest (center pixel).

Embodiment FIG. 1 is a block diagram of an image signal processing apparatus according to an embodiment of the present invention. In FIG. 1, 5 is a binary image data input signal terminal, 6 is a data storage circuit, 7 is a signal line for 5×5 scanning window data, 8 is a binary image data output signal terminal, and 9 is a boundary row in the main scanning direction. In the detection circuit, 10 is its output signal line, 11 is a sub-scanning direction boundary row detection circuit, 12 is its output signal line, 13 is a weighting addition circuit for main-scanning direction boundary row data, 14 is its output signal line, and 15 is its output signal line. In the binarization circuit, 16 is its output signal line, 17 is a sub-scanning direction boundary column data weighting addition circuit, 18 is its output signal line, 19 is the binarization circuit, 20 is its output signal line, and 21 is data selection. circuit, 22 is a signal line for set/reset signals, 23 is an isolated pixel removal circuit, 2
4 and 25 are its output signal lines.

The operation of the above configuration will be explained below.

A signal obtained by scanning the original image and converting it into a binary signal enters a data storage circuit 6 from a binary image data input signal terminal 5.
A 5×5 scanning window is set in the data storage circuit 6,
The stored binary data is rescanned, and the data within the scanning window is output to the signal line 7. Further, the central pixel within the scanning window can be rewritten by a set/reset signal 22, which will be described later. Furthermore, isolated pixels in the scanning window are also rewritten with an isolated pixel removal signal, which will be described later. Final data within the scanning window, which will be described later, is output to a binary image data output signal terminal 8 and becomes an image signal for the image display/recording device.

The boundary row detection circuit 9 in the main scanning direction
From the data in the ×5 scanning window, among the main scanning line data that sandwich the center pixel of the scanning window, one of the two columns on one side is all θ (or 1), and one of the two columns on the opposite side is all 1 ( or θ), the main scanning line data including the center pixel is determined to be a boundary column, and 1 is output to the signal line 10. The boundary row detection circuit 11 in the sub-scanning direction detects data in the 5×5 scanning window of the signal line 7 by detecting all θ (or 1 ), and any one of the two columns on the opposite side is all 1
(or θ), the sub-scanning line data including the center pixel is determined to be a boundary column, and 1 is output to the signal line 12. The main scanning direction boundary row data weighting addition circuit 13 calculates the weighted sum S of the following equation for the main scanning line data including the center pixel P _i,j among the data within the 5×5 scanning window of the signal line 7, and calculates the weighted sum S of the signal line 7. Output to 14.

S=P _i,j-2 +2P _i,j-1 +P _i,j +2P _i,j+1 +P _i,j+2 ...(1) Since the data is θ or 1, the range of S is θ≦S ≦
It becomes 7. This value of S is checked in the binarization circuit 15, and when S is θ~3, the signal line 16 is
When S is 4 to 7, 1 is output to the signal line 16. The sub-scanning direction boundary column data weighting addition circuit 17 selects among the data within the 5×5 scanning window of the signal line 7,
A weighted sum S of the following equation is determined for the sub-scanning line data including the center pixel P _i,j and output to the signal line 18.

S=P _i-2,j +2P _i-1,j +P _i,j +2P _i+1,j +P _i+2,j ...(2) This value of S is checked in the binarization circuit 19, and S When S is θ to 3, θ is output to the signal line 20, and when S is 4 to 7, 1 is output to the signal line 20. The data selection circuit 21 uses the signal on the signal line 16 as the set/reset signal on the signal line 22 when the signal line 10 is 1, and uses the signal on the signal line 20 as the set/reset signal on the signal line 22 when the signal line 12 is 1. do. The signal line 10 and signal line 12 becoming 1 at the same time does not theoretically occur due to the boundary column detection. When signal line 10 and signal line 12 are both θ, signal line 2
2 is an open state. The set/reset signal on the signal line 22 is connected to a 5×5 signal in the data storage circuit 6.
The center pixel data P _i,j of the scanning window is rewritten to 1/θ.

The isolated pixel removal circuit 23 removes pixels located in the front of the scan among the data within the 5×5 scan window of the signal line 7.
If P _i+1,j+1 is an isolated pixel of θ, an isolated pixel removal signal of 1 is output to the signal line 24, and if it is an isolated pixel of 1, an isolated pixel removal signal of θ is output to the signal line 24. . Further, similar processing is performed on the pixels P _i-1,j-1 located at the rear of the scan, and 1/θ of the isolated pixel removal signal is outputted to the signal line 25. The signals on the signal lines 24 and 25 drive the data within the scanning window of the data storage circuit 6, so that the signal on the former signal line 24 removes isolated noise from the input image data, and the signal on the latter signal line 2
The signal No. 5 removes newly generated isolated pixels by rewriting the central pixel data P _i,j . Moreover, the former noise removal makes the boundary sequence detection more reliable.

Hereinafter, more detailed configuration of the main parts of the above configuration will be explained.

FIG. 2 is a detailed circuit diagram of the data storage circuit 6. In FIG. 2, numerals 26 to 29 are shift registers each storing pixel data for one scanning line. Therefore, the pixel data of P _i+2,j+2 to _{P i-2,j-2} shown in the figure becomes 5×5 scanning window data and is output to the signal line 7. Of these, P _i-2,j-2 is 2 as the final data
The value image data is also output to the output signal terminal 8. The set/reset signal on the signal line 22 has three states (1,
θ, open) signal sets/resets the central pixel P _i,j to 1/θ. When open, P _i,j does not change.

The isolated pixel removal signal on the signal line 24 sets its signal level θ or 1 to the pixel P _i+1,j+1 . Also,
Similarly, the isolated pixel removal signal on the signal line 25
Set to P _i-1,j-1 .

Next, the boundary column detection circuit 9 will be explained.

FIG. 3 is a detailed block diagram of the boundary row detection circuit 9 in the main scanning direction. In Figure 3, 30~
33 is a gate circuit network, the specific circuit of which is shown in FIG. 3b.

35-42 are output signal lines of each gate circuit network 30-33, 43-46 are OR circuits, 47-48 are AND circuits, and 49 is an OR circuit. Gate circuit networks 30 to 33 each contain 5×5 scanning window data,
The main scanning line data that does not include the center pixel P _i,j is input, and the inputs of the gate circuit networks 30 to 33 are all θ.
Signal lines 35, 37, 39, 4 that output 1 when
1 and signal line 3 that outputs 1 when all inputs are 1
It has 6, 38, 40, 42. Gate circuit network 30
and 31 perform data determination on two columns on one side of the main scanning line data sandwiching the central pixel P _i,j, and gate circuit networks 32 and 33 perform data determination on two columns on the opposite side. The OR circuits 43 to 46 each have a signal line 35
and 37, 36 and 38, 39 and 41, and 40 and 42 are output. AND circuits 47 to 48 output AND signals of the outputs of OR circuits 43 and 46, and 44 and 45, respectively. The OR circuit 49 sends the OR signal of the outputs of the AND circuits 47 and 48 to the signal line 10.
Output to. When the signal on this signal line 10 is 1,
This means that the main scanning line data including the center pixel P _i,j is determined to be a boundary row.

Note that the detailed configuration (not shown) of the boundary row detection circuit 11 in the sub-scanning direction is also the same as that in FIG.
The input data to each gate network is as follows.

(P _i-2,j-2 Pi-1,j-2P _i,j-2 P _i+1,j-2
P _i+2 , _j-2 ), (P _i-2,j-1 P _i-1,j-1 P _i,j-1 P _i+1,j-1 P _i+2,j-1 ) , (P _i-2,j+1 P _i-1,j+1 P _i,j+1 P _i+1,j+1 P _i+2,j+1 ), (P _{i-2,j+ 2} P _i-1,j+2 P _i,j+2 P _i+1,j+2 P _i+2,j+2 ).

Next, the weighted addition circuit 13 and the binarization circuit 15
I will explain about it.

Weighting addition circuit 1 for main scanning direction boundary row data
3 and the binarization circuit 15 perform simple weighted addition and binarization of the first equation (when S=θ~3, θ, S=4
7), the two circuits can be easily configured together. FIG. 4 shows the detailed configuration of the weighted addition and binarization circuit for boundary row data in the main scanning direction. In the figure, 50 is a 2-bit adder circuit, 51 is an AND gate, and 52 is an OR gate. The adder circuit 50 selects P _i,j-1 as the upper bit,
Data with P _i,j-2 as the lower bit and data with P _i,j+1 as the upper bit and P _i,j+2 as the lower bit are added. The AND gate 51 performs the logical product of the lower two bits of the addition value of the adder circuit 50 and P _i,j, and outputs the OR gate 5.
2 takes the logical sum of the upper 1 bit of the adder circuit 50 and the output of the AND gate 51 and outputs the result to the signal line 16.

Note that the weighting addition circuit 17 and the binarization circuit 19 for the sub-scanning direction boundary row data also have the same configuration as in _FIG .
Data with P _i-2,j as the lower bit and data with P _i+1,j as the upper bit and P _i+2 , _j as the lower bit are added.

Next, the data selection circuit 21 will be explained.

FIG. 5 shows the detailed configuration of the data selection circuit 21. In the figure, reference numerals 53 and 54 are bus buffer gates with three-state outputs, and when the signal lines 10 and 12 are 1, the gate outputs are turned on. As mentioned above, the signal lines 10 and 12 are simultaneously
Such a state cannot logically occur.

Next, the isolated pixel removal circuit 23 will be explained.

FIG. 6 is a detailed circuit diagram of the isolated pixel removal circuit 23. An isolated pixel can be determined based on 8 pixels around the pixel of interest, or determined using 4 pixels on the top, bottom, left, and right around the pixel of interest, and this embodiment shows the latter. In the figure, 55-57 and 60-62 are exclusive OR gates, 58 and 63 are AND gates,
59 and 64 are bus buffer gates with three-state output. Exclusive OR gates 55 to 57 and AND gate 58 are pixel data on the top, bottom, left and right of the pixel of interest P _i+1,j+1
When P _i+1,j P _i+1,j+2 P _i,j+1 P _i+2,j+1 are all the same, the bus buffer gate 59 is turned on. The bus buffer gate 59 outputs the signal of the pixel P _i+2,j+1 to the signal line 24 when it is on. Similarly, exclusive OR gates 60 to 62 and AND gate 63 are pixels of interest.
Pixel data on the top _{, bottom, left and right of P i-1 ,j-1 P i-1,j-2} P _i-1 , _j
P _i-2,j-1 When P _i,j-1 are all the same, the bus buffer gate 64 is turned on, and the bus buffer gate 64
outputs the signal of pixel P _i,j-1 to the signal line 25.

As described above, according to this embodiment, after removing isolated pixels located in front of the scanning window, it is determined that the line containing the central pixel is a boundary using multiple line data on each side of the central pixel of the scanning window. Therefore, the rate of correctly determining boundaries is increased even for image data whose boundaries are disturbed due to noise or the like. In addition, the method of binarizing the weighted addition value of the line including the center pixel in the direction of the boundary line of main scanning or sub-scanning and resetting the center pixel is a smoothing process only in the direction of the line segment of the image. It has been experimentally confirmed that visually good results can be obtained. Furthermore, by resetting the central pixel, newly generated isolated pixels are removed at the rear of the scanning window, so a reproduced image with less noise can be obtained.

Effects of the Invention As described above, the present invention detects the black and white boundary area of the straight line part of the character/image parallel to the image scanning and performs partial smoothing on a binary image containing halftone photographs and character/line drawings. Since the process can be applied, it is possible to create a visually good image without deteriorating the halftone photograph or rounding the corners of the text and line drawings, which is highly effective.

[Brief explanation of drawings]

FIG. 1 is a block wiring diagram of an image signal processing device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a data storage circuit, FIG. 3a is a block wiring diagram of a boundary row detection circuit in the main scanning direction, and FIG. Figure 3b is the circuit diagram of the same main part, Figure 4 is the circuit diagram of the weighted addition and binarization circuit for border column data in the main scanning direction, Figure 5 is the circuit diagram of the data selection circuit, and Figure 6 is the isolated pixel removal circuit. The circuit diagram of FIG. 7 is a conceptual diagram of conventional binarized image processing. 5... Binary image data input signal terminal, 6... Data storage circuit, 7... Signal line, 8... Binary image data output signal terminal, 9... Boundary row detection circuit, 13
... Weighted addition circuit, 11 ... Boundary column detection circuit, 17 ... Weighted addition circuit, 21 ... Data selection circuit, 23 ... Isolated pixel removal circuit.

Claims (1)

[Claims] 1. For image signal processing to scan an original image and obtain a binary image signal, means for rescanning the binary image signal with a scanning window of m×n pixels, and a means for rescanning the binary image signal with a scanning window of m×n pixels; a first isolated pixel removing means for removing an isolated pixel from a pixel located ahead of the pixel in both the main scanning and sub scanning directions; and a pixel column in the main scanning or sub scanning direction including the central pixel of the scanning window. Boundary row detection means for detecting a boundary row of a binary image signal parallel to main scanning or parallel to sub-scanning, and when a pixel row in the main scanning direction including the center pixel is a boundary row in the main scanning direction; A first weighted addition means calculates and binarizes the weighted sum of each pixel in the main scanning direction including the center pixel, and sets it as the center pixel; When it is a boundary row, a second weighted addition means calculates and binarizes the weighted sum of each pixel in the sub-scanning direction including the center pixel and uses it as the center pixel; The second method removes isolated pixels for pixels located at the rear of the scan.
An image signal processing device having isolated pixel removal means. 2. The boundary row detection means is configured such that one of the two pixel rows adjacent to one of the pixel rows in the main scanning or sub-scanning direction including the center pixel is all 1 (or θ), and one of the two rows adjacent to the other one is 1 (or θ). When all the columns are θ (or 1), the pixel column in the main scanning direction or the sub-scanning direction including the central pixel is defined as the pixel column in the main scanning direction or the pixel column in the sub-scanning direction. The image signal processing device according to scope 1.