JPH0241258B2 - - Google Patents
Info
- Publication number
- JPH0241258B2 JPH0241258B2 JP26646685A JP26646685A JPH0241258B2 JP H0241258 B2 JPH0241258 B2 JP H0241258B2 JP 26646685 A JP26646685 A JP 26646685A JP 26646685 A JP26646685 A JP 26646685A JP H0241258 B2 JPH0241258 B2 JP H0241258B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- mos
- fet
- resistor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Emergency Protection Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔概要〕
過渡電流抑制回路であつて、電源接続端子と負
端子との間にMOS−FETのソース−ドレインを
直列に操入し、そのゲート−ソース間の電圧を制
御して、電源投入時に負荷回路に突入する一時的
に過大な過渡電流を制御する。[Detailed Description of the Invention] [Summary] This is a transient current suppression circuit in which the source-drain of a MOS-FET is connected in series between the power supply connection terminal and the negative terminal, and the voltage between the gate and source is controlled. control to control temporarily excessive transient currents that rush into the load circuit at power-up.
本発明は電源投入時の過大電流を抑制する過渡
電流抑制回路に関するものである。
The present invention relates to a transient current suppression circuit that suppresses excessive current when power is turned on.
一般に電子回路には、ノイズ防止、電圧の安定
のためのコンデンサが多数使用され、個々のコン
デンサの容量は小さいが電子回路の電源接続端子
側からみると、等価的にはかなりの容量のコンデ
ンサが接続されていることになる。 Generally, many capacitors are used in electronic circuits to prevent noise and stabilize voltage.Although the capacitance of each individual capacitor is small, when viewed from the power supply connection terminal side of the electronic circuit, it is equivalent to a capacitor with a considerable capacitance. It will be connected.
従つて、電源を投入した瞬間にはこのコンデン
サを充電するために、電子回路動作時の定常電流
の数倍の電流が流入する。 Therefore, at the moment the power is turned on, a current several times the steady current when the electronic circuit is operating flows in order to charge the capacitor.
その結果、電源電圧低下、あるいはノイズ発生
等によつて、その電源を共有する電子回路が誤動
作する原因になる。 As a result, electronic circuits sharing the power supply may malfunction due to a drop in power supply voltage or noise generation.
第５図は過渡電流説明図で、従来の電子回路の
等価回路と電源の接続を示し、第６図はその時間
−負荷電流特性図である。
FIG. 5 is a transient current explanatory diagram showing the equivalent circuit of a conventional electronic circuit and the connection of a power supply, and FIG. 6 is a time-load current characteristic diagram thereof.
電子回路は等価的にみて、通常等価コンデンサ
１と等価抵抗２で構成される。 When viewed equivalently, an electronic circuit usually consists of an equivalent capacitor 1 and an equivalent resistor 2.
電源３の電圧をＥ、接続線等の等価回路抵抗４
の抵抗値をｒとすると、スイツチ５をオンにした
瞬間には過渡電流I0は、
I0＝Ｅ／ｒ
となり、等価回路抵抗ｒが通常は非常に小さいの
で、過渡電流I0は大電流になる。 The voltage of power supply 3 is E, and the equivalent circuit resistance of connection wires, etc. is 4.
Assuming that the resistance value of is r, the transient current I 0 at the moment switch 5 is turned on is I 0 =E/r, and since the equivalent circuit resistance r is usually very small, the transient current I 0 is a large current. become.
上記した過渡電流I0は瞬間に立ち上がるパルス
電流となるために、その高周波成分によるノイズ
によつて、微弱信号によつて動作する電子回路の
論理回路に影響を及ぼし、あるいは電源の内部抵
抗によつて生ずる一時的な電圧低下によつて、回
路部品の誤動作の原因となる。
The above-mentioned transient current I0 is a pulse current that rises instantaneously, so it may affect the logic circuit of electronic circuits that operate with weak signals due to noise due to its high frequency component, or may be caused by the internal resistance of the power supply. The resulting temporary voltage drop may cause circuit components to malfunction.
しかし、電源投入時の突入電流を抑制するため
に、コンデンサの等価的容量を減らすとノイズ防
止に支障をきたし、等価回路抵抗ｒを増やすと電
力損失が増加することになる。 However, if the equivalent capacitance of the capacitor is reduced in order to suppress the rush current when the power is turned on, noise prevention will be hindered, and if the equivalent circuit resistance r is increased, power loss will increase.
本発明はこのような点に鑑みて創作されたもの
であつて、MOS−FETによつて電源投入時の過
大電流を防止する過渡電流抑制回路を提供するこ
とを目的としている。 The present invention was created in view of these points, and an object of the present invention is to provide a transient current suppression circuit that prevents excessive current when power is turned on using a MOS-FET.
第１図の本発明の過渡電流抑制回路の実施例の
回路図に示すように、電源接続端子の正端子１
１、負端子１２、負荷接続端子の正端子１３、負
端子１４をもち、MOS−FET９のドレイン−ソ
ースが負荷接続端子の負端子１４と電源接続端子
の負端子１２と間に挿入され、そのMOS−FET
９のゲート端子１１，１２間に接続された抵抗
６、コンデンサ７、抵抗８の直列回路の抵抗６と
コンデンサ７の接続点に接続された回路で構成さ
れている。
As shown in the circuit diagram of the embodiment of the transient current suppression circuit of the present invention in FIG.
1. It has a negative terminal 12, a positive terminal 13 as a load connection terminal, and a negative terminal 14, and the drain-source of the MOS-FET 9 is inserted between the negative terminal 14 as a load connection terminal and the negative terminal 12 as a power supply connection terminal. MOS-FET
The circuit is connected to a connection point between the resistor 6 and the capacitor 7 in a series circuit of a resistor 6, a capacitor 7, and a resistor 8 connected between the gate terminals 11 and 12 of the resistor 9.
スイツチ５が投入された瞬間では、MOS−
FET９のゲート−ソース電圧（以下、ゲート電
圧と称する）VGSは低く、ドレイン−ソース間は
遮断状態である。
At the moment switch 5 is turned on, MOS-
The gate-source voltage (hereinafter referred to as gate voltage) V GS of FET 9 is low, and the drain-source is in a cutoff state.
コンデンサ７が充電されるにつれて、ゲート電
圧VGSは次第に上昇し、それにつれてドレインソ
ース間の電流（以下、ドレイン電流と称する）ID
が次第に大きくなる。 As the capacitor 7 is charged, the gate voltage V GS gradually increases, and the drain-source current (hereinafter referred to as drain current) I D
gradually becomes larger.
一方、MOS−FETのドレイン電流はゲート電
圧に支配されるので、負荷の電子回路を充電する
過渡電流は、ドレイン電流に制限されて急激に増
加しない。 On the other hand, since the drain current of a MOS-FET is controlled by the gate voltage, the transient current that charges the electronic circuit of the load is limited by the drain current and does not increase rapidly.
そして、コンデンサ７が充電された後、ゲート
電圧VGSはMOS−FET９のドレイン電流ID、即
ち、負荷電流Ｉを流すに十分の電圧になるよう設
定される。 After the capacitor 7 is charged, the gate voltage V GS is set to a voltage sufficient to cause the drain current ID of the MOS-FET 9, that is, the load current I to flow.
以下、図面を参照して更に詳細に説明する。 A more detailed explanation will be given below with reference to the drawings.
第１図は本発明の過渡電流抑制回路の実施例の
回路図を示す。 FIG. 1 shows a circuit diagram of an embodiment of the transient current suppression circuit of the present invention.
第３図は、MOS−FET９のゲート電圧VGSと
ドレイン電流IDの特性曲線で、不感帯の電圧VOFF
を経てドレイン電流IDが流れ始める。 Figure 3 shows the characteristic curve of gate voltage V GS and drain current ID of MOS-FET 9, where the dead band voltage V OFF
Drain current I D begins to flow through .
スイツチ５がオンした時のゲート電圧VGOは
VGO＝Ｅ・R2／（R1＋R2）
（R1、R2は抵抗６，８の抵抗値）VGO＝VOFFとな
るように部品定数を設定すると、ドレイン電流
ID、即ち負荷電流Ｉが遅延することなく流れ始
め、ゲート電圧VGSは第４図の時間−VGS特性曲
線に従つて、VOFFから時定数C1（R1＋R2）で上昇
する（C1はコンデンサ７の容量）。 The gate voltage V GO when switch 5 is turned on is V GO = E・R 2 / (R 1 + R 2 ) (R 1 and R 2 are the resistance values of resistors 6 and 8) so that V GO = V OFF . By setting the component constants, the drain current
I D , that is, the load current I starts flowing without delay, and the gate voltage V GS rises from V OFF with a time constant C 1 (R 1 + R 2 ) according to the time-V GS characteristic curve in Figure 4. ( C1 is the capacitance of capacitor 7).
従つて、第２図に示すように、負荷電流Ｉ、即
ちMOS−FET９のドレイン電流IDは、電子回路
の等価コンデンサを充電する電流をパルス状にす
ることはなく、過渡電流が抑制される。 Therefore, as shown in Figure 2, the load current I, that is, the drain current I D of the MOS-FET 9, does not pulse the current that charges the equivalent capacitor of the electronic circuit, and transient current is suppressed. .
なお、第１図のダイオード６１，８１はコンデ
ンサ７の放電回路を形成するものである。 Note that the diodes 61 and 81 in FIG. 1 form a discharge circuit for the capacitor 7.
因に負荷供給電力12V1Aの過渡電流抑制回路
の１例は、R1＝1MΩ、R2＝240KΩ、C1＝1μF、
MOS−FET＝2FS428で構成する。 Incidentally, an example of a transient current suppression circuit with a load supply power of 12V1A is R 1 = 1MΩ, R 2 = 240KΩ, C 1 = 1μF,
Consists of MOS-FET=2FS428.
また、本発明の制御用トランジスタはMOS−
FETのみならず、コレクタ電流がゲート電圧で
制御できるトランジスタに置換することが可能で
ある。 Furthermore, the control transistor of the present invention is a MOS-
It is possible to replace not only FETs but also transistors whose collector current can be controlled by gate voltage.
以上述べてきたように、本発明によれば、簡単
な回路で効果的に過渡電流を抑制でき、電力損失
が殆どなく、実用的には極めて有用である。
As described above, according to the present invention, transient current can be effectively suppressed with a simple circuit, there is almost no power loss, and the present invention is extremely useful in practice.
第１図は本発明の過渡電流抑制回路の一実施例
の回路図、第２図は実施例の時間−負荷電流特性
図、第３図はMOS−FETのVGS−ID特性図、第４
図は実施例の時間−VGS特性図、第５図は過渡電
流発生説明図、第６図は第５図の時間−負荷電流
特性図である。
図において、６は抵抗（R1）、７はコンデンサ
（C1）、８は抵抗（R2）、９はMOS−FET、１１，
１２は電源接続端子、１３，１４は負荷接続端子
である。
Fig. 1 is a circuit diagram of an embodiment of the transient current suppression circuit of the present invention, Fig. 2 is a time-load current characteristic diagram of the embodiment, and Fig. 3 is a V GS -I D characteristic diagram of the MOS-FET. 4
The figure is a time-V GS characteristic diagram of the embodiment, FIG. 5 is an explanatory diagram of transient current generation, and FIG. 6 is a time-load current characteristic diagram of FIG. 5. In the figure, 6 is a resistor (R 1 ), 7 is a capacitor (C 1 ), 8 is a resistor (R 2 ), 9 is a MOS-FET, 11,
12 is a power supply connection terminal, and 13 and 14 are load connection terminals.
Claims (1)
コンデンサ７と第２の抵抗８とからなる直列回路
を、該第１の抵抗６の一端が該電源入力端子の正
端子１１につながるよう接続し、 該第１の抵抗６と該コンデンサ７の接続点に
MOS−FET９のゲートを接続し、 該MOS−FET９のソースに前記電源接続端子
の負端子１２を接続し、 該MOS−FET９のドレインに負荷接続端子の
負端子１４を接続し、 前記電源接続端子と前記負荷接続端子のそれぞ
れの正端子１１，１３を接続してなる過渡電流抑
制回路。[Claims] 1. A series circuit consisting of a first resistor 6, a capacitor 7, and a second resistor 8 is connected between the power supply connection terminals 11 and 12, with one end of the first resistor 6 connected to the power supply input terminal. Connect it to the positive terminal 11, and connect it to the connection point between the first resistor 6 and the capacitor 7.
Connect the gate of the MOS-FET 9, connect the negative terminal 12 of the power connection terminal to the source of the MOS-FET 9, connect the negative terminal 14 of the load connection terminal to the drain of the MOS-FET 9, and connect the negative terminal 12 of the power connection terminal to the source of the MOS-FET 9. and a transient current suppression circuit formed by connecting the respective positive terminals 11 and 13 of the load connection terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26646685A JPS62126508A (en) | 1985-11-26 | 1985-11-26 | Transient current suppression circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26646685A JPS62126508A (en) | 1985-11-26 | 1985-11-26 | Transient current suppression circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62126508A JPS62126508A (en) | 1987-06-08 |
| JPH0241258B2 true JPH0241258B2 (en) | 1990-09-17 |
Family
ID=17431317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26646685A Granted JPS62126508A (en) | 1985-11-26 | 1985-11-26 | Transient current suppression circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62126508A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0625633B1 (en) * | 1992-12-03 | 2000-03-15 | Toyota Jidosha Kabushiki Kaisha | Exhaust gas cleaning apparatus for internal combustion engines |
| JP2013116001A (en) * | 2011-11-30 | 2013-06-10 | Mitsubishi Electric Corp | Power-supply circuit |
-
1985
- 1985-11-26 JP JP26646685A patent/JPS62126508A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62126508A (en) | 1987-06-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |