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JPH0241276B2 - - Google Patents
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JPH0241276B2 - - Google Patents

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Publication number
JPH0241276B2
JPH0241276B2 JP56107514A JP10751481A JPH0241276B2 JP H0241276 B2 JPH0241276 B2 JP H0241276B2 JP 56107514 A JP56107514 A JP 56107514A JP 10751481 A JP10751481 A JP 10751481A JP H0241276 B2 JPH0241276 B2 JP H0241276B2
Authority
JP
Japan
Prior art keywords
transistor
collector
transistors
motor
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56107514A
Other languages
Japanese (ja)
Other versions
JPS589589A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP56107514A priority Critical patent/JPS589589A/en
Publication of JPS589589A publication Critical patent/JPS589589A/en
Publication of JPH0241276B2 publication Critical patent/JPH0241276B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02PCONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P7/00Arrangements for regulating or controlling the speed or torque of electric DC motors
    • H02P7/06Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current
    • H02P7/18Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current by master control with auxiliary power
    • H02P7/24Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices
    • H02P7/28Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices
    • H02P7/285Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices controlling armature supply only
    • H02P7/288Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices controlling armature supply only using variable impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Direct Current Motors (AREA)

Description

【発明の詳細な説明】 本発明はカレントミラー方式により、直流モー
タを駆動する小型直流モータの速度制御回路に係
り、第1のカレントミラー回路と第2のカレント
ミラー回路との間に抵抗を接続する事により、第
1のカレントミラー回路の夫々のトランジスタの
コレクタ、エミツタ電圧が飽和領域付近に達した
時に、夫々のトランジスタ間のエミツタ面積の大
小に起因する特性のバラツキによる電流比の変動
を小さく抑えて直流モータのハンチングを防止す
る事を目的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed control circuit for a small DC motor that uses a current mirror method to drive a DC motor, in which a resistor is connected between a first current mirror circuit and a second current mirror circuit. By doing so, when the collector and emitter voltages of each transistor in the first current mirror circuit reach near the saturation region, the fluctuation in the current ratio due to the variation in characteristics caused by the size of the emitter area between each transistor is reduced. The purpose is to suppress hunting of the DC motor.

従来のモータの速度制御回路の1例を第1図に
示す。同図中破線で囲んだ部分はモノリシツク
IC化された部分であり、1〜5はその外部導出
端子である。端子1,2間、2,3間及び3,4
間には夫々抵抗R1,R2及びボリユームVRが接続
されている。このボリユームVRは速度調整用で
ある。又、端子5はアース端子であり、電源Vcc
は端子1,5間に接続されている。モータMは端
子1,4間に接続されている。
An example of a conventional motor speed control circuit is shown in FIG. The part surrounded by the broken line in the figure is monolithic.
It is an IC part, and 1 to 5 are its external lead terminals. Between terminals 1 and 2, between terminals 2 and 3, and between terminals 3 and 4
Resistors R 1 and R 2 and a volume VR are connected between them. This volume VR is for speed adjustment. In addition, terminal 5 is a ground terminal and is connected to the power supply Vcc.
is connected between terminals 1 and 5. Motor M is connected between terminals 1 and 4.

一方モノリシツクIC内には、第1のカレント
ミラーを構成するベースを共通接続されたトラン
ジスタQ1,Q2のエミツタが抵抗R3,R4を介して
夫々アースされている。これらのトランジスタ
Q1,Q2のコレクタは、第2のカレントミラーを
構成するトランジスタQ3,Q4の夫々のエミツタ
と接続されて、これらのカレントミラー回路は縦
続接続されている。トランジスタQ3及びQ4のコ
レクタは端子2及び定電流源6を介して端子1と
夫々接続されている。トランジスタQ3,Q4のベ
ースは互いに接続され、トランジスタQ4のベー
スとコレクタは接続されている。トランジスタ
Q2のコレクタは端子4へ接続されている。
On the other hand, in the monolithic IC, the emitters of transistors Q 1 and Q 2 that constitute a first current mirror and whose bases are connected in common are grounded via resistors R 3 and R 4 , respectively. these transistors
The collectors of Q 1 and Q 2 are connected to the respective emitters of transistors Q 3 and Q 4 constituting the second current mirror, and these current mirror circuits are connected in cascade. The collectors of transistors Q 3 and Q 4 are connected to terminal 1 via terminal 2 and constant current source 6, respectively. The bases of transistors Q 3 and Q 4 are connected to each other, and the base and collector of transistor Q 4 are connected. transistor
The collector of Q 2 is connected to terminal 4.

端子7a及び7bが端子1及び端子5へ接続さ
れた比較器(演算増巾器)7が設けられ、この非
反転入力端子は端子3と接続され、反転入力端子
は、端子2,5間に直列に接続された、ツエナー
ダイオード8と定電流源9との接続点に接結され
る。
A comparator (operational amplifier) 7 is provided with terminals 7a and 7b connected to terminals 1 and 5, the non-inverting input terminal is connected to terminal 3, and the inverting input terminal is connected between terminals 2 and 5. It is connected to a connection point between a Zener diode 8 and a constant current source 9, which are connected in series.

トランジスタQ3,Q4の夫々のベース、エミツ
タ間電圧VBE3及びVBE4はほぼ等しく、従つてトラ
ンジスタQ1,Q2のコレクタ電圧はほぼ等しい電
圧に保持されている。
The base-to-emitter voltages V BE3 and V BE4 of transistors Q 3 and Q 4 are approximately equal, and therefore the collector voltages of transistors Q 1 and Q 2 are maintained at approximately equal voltages.

上記の回路構成において、トランジスタQ1
Q2のエミツタ面積の比は1:K(Kは正の整数)
とされている。ここでモータMの逆起電圧Eg、
内部抵抗をRg、モータを流れる電流をIM、トラ
ンジスタQ3及びQ4のコレクタ電流は共にほぼ等
しく、トランジスタQ1のコレクタに流れる電流
をIKとし、抵抗R2に流れる電流をIS、その両端に
発生する電圧をVS、ツエナーダイオードに流れ
る電流をIZ、ボリユームVRの抵抗値をR〓とする。
又、比較回路7の夫々の入力インピーダンスは非
常に高くそれらに流入する電流は無視すると、次
式の関係が成立する。
In the above circuit configuration, transistors Q 1 ,
The emitter area ratio of Q 2 is 1:K (K is a positive integer)
It is said that Here, the back electromotive force Eg of the motor M,
The internal resistance is Rg, the current flowing through the motor is I M , the collector currents of transistors Q 3 and Q 4 are almost equal, the current flowing through the collector of transistor Q 1 is I K , the current flowing through resistor R 2 is I S , Let the voltage generated across both ends be V S , the current flowing through the Zener diode be I Z , and the resistance value of the volume VR be R〓.
Further, the input impedance of each of the comparator circuits 7 is very high, and if the current flowing into them is ignored, the following relationship holds true.

Eg+IMRg=IS(R1+R2+R〓)+(IK+IZ)R1 ……(1) ここで IS=VS/R2 ……(2) IK=1/K・IMつまりK=IM/IK ……(3) この(2)、(3)式を(1)式に代入して次式を得る。Eg + I M Rg = I S (R 1 + R 2 + R〓) + (I K + I Z ) R 1 ... (1) where I S = V S /R 2 ... (2) I K = 1 / K・I M, that is, K=I M /I K (3) Substituting equations (2) and (3) into equation (1), the following equation is obtained.

Eg+IMRg=VS/R2(R1+R2+R〓)+IZR1+IM/KR1
…(4) ブリツジのバランス条件より、4式の左辺第1
項と右辺の第1項、第2項、又左辺第2項と右辺
第2項より次式が成立する。
Eg+I M Rg=V S /R 2 (R 1 +R 2 +R〓)+I Z R 1 +I M /KR 1 ...
…(4) From the bridge balance condition, the first left side of equation 4
The following equation holds true from the first and second terms on the right side, the second term on the left side, and the second term on the right side.

Eg=VS/R2(R1+R2+R〓)+IZR1 ……(5) IMRg=IM/KR1 ……(6) 6式より、 R1=KRg ……(7) が導びかれる。 Eg=V S /R 2 (R 1 +R 2 +R〓)+I Z R 1 ...(5) I M Rg=I M /KR 1 ...(6) From equation 6, R 1 =KRg ...(7 ) is derived.

通常(7)式における抵抗R1の値は、Kを少し大
き目に選定して右辺のKRgの値よりも少し小さ
目に設定されて過制御とならない様に(ハンチン
グ防止の為)されている。
Usually, the value of the resistor R 1 in equation (7) is set slightly larger than the value of KRg on the right side by selecting K a little larger to prevent overcontrol (to prevent hunting).

この回路において比較器7は基準電圧となるツ
エナーダイオード8の電圧VZと直流モータMの
逆起電圧及びモータの内部抵抗Rgによる電圧降
下とを差動増巾し、この出力となる差電圧によつ
てトランジスタQ1を含む直流モータを駆動する
為のトランジスタQ2を駆動し、モータMに流れ
る電流を制御する事により、直流モータMの回転
が一定となる様に制御される。
In this circuit, the comparator 7 differentially amplifies the voltage VZ of the Zener diode 8, which serves as the reference voltage, the back electromotive force of the DC motor M, and the voltage drop due to the internal resistance Rg of the motor, and converts it into the differential voltage that becomes the output. Therefore, by driving the transistor Q 2 for driving the DC motor including the transistor Q 1 and controlling the current flowing to the motor M, the rotation of the DC motor M is controlled to be constant.

この様な従来の回路では、電源電圧が低下した
場合、過負荷時及び起動時等の際に、第1のカレ
ントミラー回路を構成するトランジスタQ1,Q2
のコレクタ、エミツタ間電圧(以下単にVCEとい
う)が飽和付近又は飽和領域に達すると、第2図
のVCE−IC(ICはコレクタ電流)特性図で示す様
に、トランジスタQ2のコレクタ電流IC2(このIC2
IMとほぼ等しいものとする)はトランジスタQ1
のコレクタ電流IKよりも減少率が大きく、その結
果、(3)式で示したKが小さくなり、そして(6)式の
右辺が左辺に対して大きくなる為、補正が過大と
なつてモータMがハンテイングを起す事になる。
In such a conventional circuit, when the power supply voltage decreases, when there is an overload, when starting up, etc., the transistors Q 1 and Q 2 forming the first current mirror circuit are
When the collector-to-emitter voltage (hereinafter simply referred to as V CE ) of Q2 reaches near saturation or reaches the saturation region, as shown in the V CE −I C (I C is collector current) characteristic diagram in Figure 2, the voltage of transistor Q 2 Collector current I C2 (This I C2 is
I M ) is the transistor Q 1
As a result, K shown in equation (3) becomes smaller, and the right side of equation (6) becomes larger than the left side, so the correction becomes excessive and the motor M will start hunting.

本発明は係る従来の問題点を一掃したもので以
下図面と共にその実施例について説明する。第3
図は本発明の一実施例になる速度制御回路を示
す。第1図と同一構成部分には同一符号を付し、
その説明は省略する。
The present invention eliminates the problems of the conventional art, and embodiments thereof will be described below with reference to the drawings. Third
The figure shows a speed control circuit according to an embodiment of the present invention. The same components as in Fig. 1 are given the same reference numerals.
The explanation will be omitted.

トランジスタQ1のコレクタとトランジスタQ3
のエミツタとの間に抵抗Rが接続されている。こ
の実施例におけるトランジスタQ1,Q2のコレク
タ電流のIK,IC2は1:50の比即ちKは50に選定さ
れている。尚、このKの値は次の二つの条件を満
足する様に選定される。その第1はKを例えば1
にすると、Q1のコレクタへQ2と同じコレクタ電
流(例えば200mA)が流れ、電流ロスが大とな
る為、Kは1より充分大きくする必要がある。
又、第2は抵抗R1を流れるツエナーダイオード
8の電流IZ(例えば0.1mA)の温度ドリフトによ
る影響を避ける為に、IK(例えば4mA)はIZ
り充分大きな値に選定する必要がある。従つてIK
はこれらの条件を満足させる為に50に選定されて
いる。ここで何らかの原因でトランジスタQ1
Q2の各々のVCEが飽和領域付近に達すると、前記
従来例の如く夫々のコレクタ電流IK,IC2は減少し
始めてIC2の減少率が大きい為、Kが小さくなる
方向に変化するが、然しこの場合コレクタ電流の
小さいトランジスタQ1のコレクタとトランジス
タQ3のエミツタとの間に抵抗Rが接続されてい
る為、飽和領域付近では、この抵抗による電流ド
ロツプが発生し、そのIKの電流の勾配は第4図に
示すVCE−IC特性で示すIK曲線の様になる。即ち
飽和領域付近では抵抗RによりトランジスタQ1
のコレクタ電流IKも減少する為、IKとIC2(IC2≒IM
の比は殆んど変らず、従つて過大制御とならずハ
ンチング現象は発生せず安定なモータの速度制御
が可能となるものである。
Collector of transistor Q 1 and transistor Q 3
A resistor R is connected between the emitter and the emitter. In this embodiment, the collector currents I K and I C2 of transistors Q 1 and Q 2 are selected to have a ratio of 1:50, that is, K is 50. Note that the value of K is selected so as to satisfy the following two conditions. The first is to set K to 1, for example.
In this case, the same collector current (for example, 200 mA) as that of Q 2 flows to the collector of Q 1 , resulting in a large current loss, so K needs to be sufficiently larger than 1.
Second, in order to avoid the influence of temperature drift of the current I Z (e.g. 0.1 mA) of the Zener diode 8 flowing through the resistor R 1 , I K (e.g. 4 mA) must be selected to a value sufficiently larger than I Z. be. Therefore I K
is selected as 50 to satisfy these conditions. Here, for some reason, the transistor Q 1 ,
When each V CE of Q 2 reaches near the saturation region, the respective collector currents I K and I C2 start to decrease as in the conventional example, and since the decreasing rate of I C2 is large, K changes in the direction of decreasing. However, in this case, since a resistor R is connected between the collector of transistor Q1 , which has a small collector current, and the emitter of transistor Q3 , a current drop due to this resistor occurs near the saturation region, and the I K The slope of the current becomes like the IK curve shown in the V CE -I C characteristic shown in Figure 4. In other words, near the saturation region, the resistance R causes the transistor Q 1
Since the collector current I K also decreases, I K and I C2 (I C2 ≒ I M )
The ratio hardly changes, and therefore, no excessive control occurs, no hunting phenomenon occurs, and stable motor speed control is possible.

第5図はトランジスタQ1,Q2のVCEの変化に対
するKの変化を示す図で、点線K′は従来の速度
制御回路によるものであり、実線Kは本発明の実
施例おけるKの変化示すもので、点線K′の方が
VCEの比較的大きい所から小さくなり始めている
事を示すものである。
FIG. 5 is a diagram showing the change in K with respect to the change in V CE of transistors Q 1 and Q 2 , where the dotted line K' is due to the conventional speed control circuit, and the solid line K is the change in K in the embodiment of the present invention. The dotted line K′ is
This shows that V CE starts to decrease from a relatively large point.

尚、抵抗Rの値は回路の定数、Kの大きさ或い
はトランジスタの電流容量等で決定されるが、本
実施例では30Ωに選定されている。
The value of the resistor R is determined by the circuit constant, the magnitude of K, the current capacity of the transistor, etc., and is selected to be 30Ω in this embodiment.

次に第6図に第3図の変形例になる速度制御回
路を示す。第1図及び第3図と同一部分には同一
符号を付し、その説明は省略する。
Next, FIG. 6 shows a speed control circuit that is a modification of FIG. 3. Components that are the same as those in FIGS. 1 and 3 are designated by the same reference numerals, and their explanations will be omitted.

第2のカレントミラー回路は、トランジスタ
Q3 Q5で構成され、Q3のベースへPNPトランジ
スタQ5のエミツタが接続され、その接続点は定
電流源6を介して端子1へ接続される。Q5のベ
ースはQ2のコレクタと端子4へ接続され、コレ
クタは端子5へ接続される。この回路ではトラン
ジスタQ5のコレクタは端子5へ接続されており、
トランジスタQ2のコレクタへ流れ込む電流はそ
のベース電流のみであり、このベース電流は非常
に小さく、従つて第1図、第2図に示す様にその
コレクタ電流(このコレクタ電流は負荷変動に比
例して変化する)が流れない為、K(IC2/IK)が
他の変動要因を受けず一定とする事ができ、安定
なモータの回転速度の制御を行う事ができる。
The second current mirror circuit is a transistor
The emitter of a PNP transistor Q5 is connected to the base of Q3 , and the connection point thereof is connected to terminal 1 via a constant current source 6. The base of Q 5 is connected to the collector of Q 2 and terminal 4, and the collector is connected to terminal 5. In this circuit, the collector of transistor Q 5 is connected to terminal 5,
The current flowing into the collector of transistor Q2 is only its base current, and this base current is very small. Therefore, as shown in Figures 1 and 2, its collector current (this collector current is proportional to load fluctuation Since K (I C2 /I K ) does not flow, K (I C2 /I K ) can be kept constant without being affected by other fluctuation factors, and the rotational speed of the motor can be controlled stably.

上述した様に本考案では、エミツタ面積の異な
る複数のトランジスタで構成した第1のカレント
ミラー回路と、第2のカレントミラー回路を縦続
接続した直流モータMの駆動回路において、第1
のカレントミラー回路のエミツタが小面積のトラ
ンジスタのコレクタに抵抗を接続する構成とした
為、トランジスタの特性の相違に基ずくVCEの飽
和又はその付近でのK(IC2/IK)の値をほぼ一定
とするか又は大き目とする事ができ、例えば低電
源電圧での速度制御(運転)、過負荷時及び起動
時等におけるハンチングの発生を防止する事がで
き、安定に直流モータの回転速度を制御できるも
のである。
As described above, in the present invention, in a drive circuit for a DC motor M in which a first current mirror circuit constituted by a plurality of transistors having different emitter areas and a second current mirror circuit are connected in cascade, the first
Since the emitter of the current mirror circuit is configured to connect a resistor to the collector of a transistor with a small area, the value of K (I C2 /I K ) at or near the saturation of V CE based on the difference in the characteristics of the transistor can be made almost constant or large, for example, it is possible to prevent hunting from occurring during speed control (operation) at low power supply voltage, overload, startup, etc., and to ensure stable DC motor rotation. The speed can be controlled.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例のモータ速度制御回路図、第2
図は従来回路における第1のカレントミラー回路
のトランジスタのVCE−IC特性図、第3図は本発
明の一実施例になるモータ速度制御回路図、第4
図は本発明実施例の回路における第1のカレント
ミラー回路のトランジスタのVCE−IC特性図、第
5図はVCE−Kの特性図、第6図は本発明の実施
例の他の変形例を示すモータの速度制御回路図を
夫々示す。 1〜5……端子、7……比較回路、8……ツエ
ナーダイオード、M……直流モータ、Q1〜Q5
…トランジスタ、R1〜R4,R……抵抗、VR……
ボリユーム。
Figure 1 is a conventional motor speed control circuit diagram, Figure 2
The figure is a V CE -I C characteristic diagram of the transistor of the first current mirror circuit in a conventional circuit, Figure 3 is a motor speed control circuit diagram according to an embodiment of the present invention, and Figure 4 is a diagram of a motor speed control circuit according to an embodiment of the present invention.
The figure shows the V CE -I C characteristic diagram of the transistor of the first current mirror circuit in the circuit of the embodiment of the present invention, Fig. 5 shows the V CE -K characteristic diagram, and Fig. 6 shows the characteristic diagram of the transistor of the first current mirror circuit in the circuit of the embodiment of the present invention. 3A and 3B show speed control circuit diagrams of motors showing modified examples, respectively. 1 to 5... terminal, 7... comparison circuit, 8... Zener diode, M... DC motor, Q 1 to Q 5 ...
...transistor, R1 to R4 , R...resistance, VR...
Volume.

Claims (1)

【特許請求の範囲】 1 直流電源の一端及び他端に直列接続されたモ
ータ及び第1のトランジスタと、 該モータと並列関係に直列接続され、第1、第
2及び第3の抵抗と、 該第1のトランジスタのエミツタの面積に対し
て1/K(Kは正数)のエミツタ面積を有し、且
つ、ベースが該第1のトランジスタのベースと共
通接続された第2のトランジスタと、 互いにベースが接続された第3及び第4のトラ
ンジスタからなるカレントミラー回路と、 該第3のトランジスタのコレクタが該第1及び
第2の抵抗の接続点に、又エミツタが該第2のト
ランジスタのコレクタ・エミツタ間電圧が飽和付
近又は飽和領域に達したときそのコレクタ電流を
減少させる為の抵抗を介して該第2のトランジス
タのコレクタに夫々接続され、 該第4のトランジスタのコレクタは該電源の一
端に、又エミツタは該第1のトランジスタのコレ
クタに夫々接続され、 一入力端が基準電圧源を介して該第1及び第2
の抵抗の接続点に、又他入力端が該第2及び第3
の抵抗の接続点に夫々接続され出力端が該第1及
び第2のトランジスタのベースに接続された比較
器とを具備してなる小型直流モータの速度制御回
路。
[Claims] 1. A motor and a first transistor connected in series to one end and the other end of a DC power supply; first, second, and third resistors connected in series in parallel with the motor; a second transistor having an emitter area that is 1/K (K is a positive number) of the emitter area of the first transistor, and whose base is commonly connected to the base of the first transistor; a current mirror circuit consisting of third and fourth transistors whose bases are connected; the collector of the third transistor is connected to the connection point of the first and second resistors; and the emitter is connected to the collector of the second transistor. - Connected to the collectors of the second transistors through resistors to reduce the collector current when the emitter voltage approaches saturation or reaches the saturation region, and the collector of the fourth transistor is connected to one end of the power supply. Also, the emitters are respectively connected to the collectors of the first transistor, and one input terminal is connected to the first and second transistors through a reference voltage source.
The other input terminal is connected to the connection point of the second and third resistors.
A speed control circuit for a small direct current motor, comprising: a comparator connected to a connection point of each of the resistors, and having an output terminal connected to the bases of the first and second transistors.
JP56107514A 1981-07-09 1981-07-09 Speed control circuit for compact dc motor Granted JPS589589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56107514A JPS589589A (en) 1981-07-09 1981-07-09 Speed control circuit for compact dc motor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56107514A JPS589589A (en) 1981-07-09 1981-07-09 Speed control circuit for compact dc motor

Publications (2)

Publication Number Publication Date
JPS589589A JPS589589A (en) 1983-01-19
JPH0241276B2 true JPH0241276B2 (en) 1990-09-17

Family

ID=14461127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56107514A Granted JPS589589A (en) 1981-07-09 1981-07-09 Speed control circuit for compact dc motor

Country Status (1)

Country Link
JP (1) JPS589589A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018692U (en) * 1983-07-14 1985-02-08 三洋電機株式会社 motor circuit
JPS61231886A (en) * 1985-04-05 1986-10-16 Rohm Co Ltd Electronic governor
JP2663415B2 (en) * 1985-05-07 1997-10-15 松下電器産業株式会社 DC motor speed controller
JPS6440296U (en) * 1987-09-02 1989-03-10

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5681089A (en) * 1979-11-30 1981-07-02 Hitachi Ltd Speed controlling circuit for dc motor

Also Published As

Publication number Publication date
JPS589589A (en) 1983-01-19

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