JPH0241765B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a random number generation circuit, and particularly to an improved random number generation circuit that can obtain a random number signal with a simple configuration. [Background Art] In order to obtain the sounds of percussion instruments, sound effects of games, etc. using electronic circuits, a noise sound source that outputs random numbers is required, and for this reason various random number generation circuits have been developed and put into practical use. . FIG. 2 shows such a conventional random number generation circuit, and as shown in FIG. 2A, this random number generation circuit includes a serial input parallel output type shift register 10 and a memory of this shift register 10 It includes a feedback circuit 12 that calculates the contents and inputs a predetermined serial signal to the shift register. Then, each time the shift pulse SP is input from the shift pulse output circuit 14, the feedback circuit 12 sends the shift register 1 to the shift register 1.
By inputting a new serial signal to 0 and shifting the memory contents rightward in the figure, pseudorandom numbers with a predetermined period are generated in the shift register. FIG. 2B shows a specific circuit configuration of such a conventional random number generation circuit, and the random number generation circuit of the embodiment includes an n-stage shift register 10 and a desired parallel and a feedback circuit 12 to which the output is input, and generates pseudo-random numbers in the shift register 10 with a clock cycle of 2 ⁿ -1. Therefore, when the contents of any stage of the shift register 10 are output and extracted, an irregular random number sequence of 0's and 1's is obtained. As mentioned above, the random number sequence has a period of 2 ⁿ -1, so it is called a pseudorandom number, but if the value of n is large enough, this period also becomes large, so it is not true in actual use. It is safe to regard it as the same as a random number. Therefore, by using the random number obtained in this way as a sampling address, it is possible to output a desired noise signal. [Problems to be Solved by the Invention] However, in the conventional random number generation circuit, it is necessary to independently provide the shift register 10 and the shift pulse output circuit 14 that supplies shift pulses to the shift register 10. However, the disadvantage is that the number of circuit parts increases, making the entire device complex and expensive. In particular, in sound generation circuits that generate desired sounds using electronic circuits, a periodic waveform generation circuit for generating desired onomatopoeic sounds is provided in addition to such a random number generation circuit for generating noise waveforms. Therefore, if such a conventional random number generation circuit is provided separately from a periodic waveform generation circuit, the entire circuit becomes extremely complicated and expensive, and the entire circuit becomes large. [Object of the Invention] The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a small-sized and low-cost random number generation circuit that increases the degree of integration of the entire circuit. [Means and effects for solving the problem] In order to achieve the above object, the circuit of the present invention includes an accumulation memory that stores an accumulated value, and a circuit that adds the accumulated value and externally input frequency data. a first adder for writing and storing the added value in the accumulation memory as a new accumulated value, and based on a carry signal generated when the accumulated value of the first adder overflows. It consists of a shift pulse output section that outputs a shift pulse, a random value memory, and a second adder, and each time the shift pulse is input, the second adder is used to add a multiple of the random value memory contents and update the shift register. and a feedback circuit that feeds back a feedback signal to the carry input terminal of the second adder based on the output of the random value memory, and generates a predetermined random number in the random value memory. A random number generating section, and the first adder and the second adder are characterized in that the same adder is shared in a time-sharing manner. With the above configuration, the random number generation circuit of the present invention can reduce the number of parts used and increase the degree of integration of the entire circuit. As a result, a small and low cost random number generation circuit can be provided. can do. Here, the random number generation circuit of the present invention can be widely used for various purposes, and is particularly suitable as a random number generation source used when generating noise in a sound generation circuit. [Example] Next, a preferred example of the present invention will be described based on the drawings. (A) Principle of random number generation circuit FIG. 1 shows a preferred embodiment of the random number generation circuit according to the present invention. and a random number generator 2 that generates a predetermined random number every time the shift pulse SP is input.
2. The shift pulse output section 20 adds the frequency data F stored in the frequency data memory 24 and the cumulative value B stored in the cumulative memory 26 using an adder 28, and uses the added value as a new cumulative value. The memory contents of the accumulation memory 26 are updated as the calculated value B. Such updating of the accumulation memory 26 is performed every time a write pulse a is input from the timing generation circuit 30 at a constant cycle. Therefore, the shift pulse output section 20 of the embodiment
is the cumulative value stored in the cumulative memory 26 and the frequency data memory 24 by the operation of the adder 28.
If a write pulse a is output from the timing generation circuit 30, the added value is written and stored in the accumulation memory 26 as a new accumulated value. . Then, the adder 28 adds such an accumulated value B
When this added value overflows as a result of addition of and frequency data F, a carry signal c is output from the output terminal CO, and the carry signal c thus output is a write signal output from the timing generation circuit 30. It is supplied to the AND gate 31 together with the timing signal b having the same period as the pulse a, and the shift pulse SP is supplied from the AND gate 31.
is output as In this way, the shift pulse output section 2 of the embodiment
0 outputs a shift pulse SP to the random number generator 22 every time the adder 28 overflows and outputs a carry signal c. The time interval at which this shift pulse SP is output is the time interval at which the adder 28 overflows. Therefore, if the value of the frequency data F input to the adder 28 is large, the time interval can be shortened. By decreasing the value of F, the time interval can be lengthened. Therefore, by setting a large value of the frequency data F to be written and stored in the frequency data memory 24, the shift pulse output section 2 of the embodiment
Shift pulses SP are output at short time intervals from 0, and by setting small frequency data F in the frequency data memory 24, it is possible to lengthen the time interval of output shift pulses SP. Further, the random number generation unit 22 of the embodiment includes a shift circuit 32 functioning as a shift register, a feedback circuit 12 that supplies a serial signal to the shift circuit 32 based on the parallel output of the shift circuit 32,
including. The shift circuit 32 includes a random value memory 34 and a second adder 36, and uses the second adder 36 to update the memory contents of the random value memory 34 every time a shift pulse SP is input from the shift pulse output section 20. Add multiples and update to new memory contents. In the embodiment, the second adder 36 functions as a doubler that doubles the memory contents of the random value memory 34. By doing this, the random value memory 3
The memory contents stored in 4 are the shift pulse
Each time SP is input, it shifts to the higher digits,
It will function as a shift register. That is, when the memory content of the random value memory 34 is, for example, "0011" and the feedback value of the feedback circuit 12 is "0", when the memory content is multiplied by the second adder 36, the content becomes "0110". ”. Furthermore, when this new memory content "0110" is further multiplied by the adder 36, the memory content becomes "1100". It is thus understood that shift circuit 32 functions similarly to a shift register. The feedback circuit 12 then operates the random value memory 34.
A predetermined serial signal is output as a feedback signal based on the parallel outputs of , and the serial signal is input to the carry input terminal CI of the second adder 36 . Here, the carry input terminal CI is equivalent to a serial input in a shift register. By doing so, the random number generator 22 of the embodiment functions in exactly the same way as the circuit shown in FIG. 2, and can generate random numbers inside the random value memory 34 every time the shift pulse SP is input. can. At this time, the random number generation cycle is determined by the output cycle of the shift pulse SP supplied from the shift pulse output section 20, and therefore, random numbers can be generated by increasing the value of the frequency data F written and stored in the frequency data memory 24. The cycle can be set short, and the random number generation cycle can be set long by reducing the set frequency data. As explained above, the random number generation circuit according to the present invention has a circuit configuration that approximates the shift pulse output section 20 and the random number generation section 22, and its characteristic feature is that by using a time division method, The advantage is that the same adder can be used as the first adder 28 and the second adder 36 used in the shift pulse generating section 20 and the random number generating section 22. That is, by performing the operation of the shift pulse output section 20 and the operation of the random number generation section 22 at different timings using a time-sharing method, the first adder 28 and the second adder 36
cannot operate at the same time. Therefore, one adder is replaced by the first adder 2 when the shift pulse output section 20 is operating.
8, and when the random number generator 22 is operating, it can be used as the second adder 36. In this way, the same adder can be used as the first and second adder 36.
By using it as adders 28 and 36,
The configuration of the random number generation circuit can be simplified and its degree of integration can be increased, and as a result, the cost of the entire circuit can be reduced. Further, in the random number generation circuit of the present invention, ordinary memories can be used as the memories 24, 26, and 34 used in the shift pulse output section 20 and the random number generation section 22. Same memory, e.g.
It becomes possible to form them at different addresses within the RAM, and by doing so, it becomes possible to further increase the degree of integration of the entire circuit. (B) Principle of sound generation circuit Next, a case where the random number generation circuit of the present invention is applied to a sound generation circuit will be explained as an example. In the embodiment, this sound generation circuit includes a periodic waveform generation circuit that outputs a waveform of an arbitrary frequency and shape to generate a desired onomatopoeia, and a periodic waveform generation circuit that outputs a noise waveform of a desired period and generates, for example, the sound of a percussion instrument or the sound effect of a game. a noise waveform generation circuit that generates
including. Here, the random number generation circuit of the present invention is used as a part of the noise waveform generation circuit. The sound generation circuit of the embodiment will be explained below by dividing it into a periodic waveform generation circuit and a noise waveform generation circuit. (B-1) Periodic waveform generation circuit FIG. 3A shows a preferred embodiment of the periodic waveform generation circuit. By reading an arbitrary waveform from the waveforms at a desired period, a waveform with an arbitrary frequency and shape is generated. As is well known, general waveforms are waveform (shape),
It has three elements: repetition frequency (period) and amplitude, and if any one of these is different, the waveform will be different. For example, in the case of onomatopoeia, the timbre, pitch, and sound pressure will be different. Note that the frequency also includes the initial phase. Corresponding to the above three elements, each element is also arbitrarily designated in the waveform generating circuit of the embodiment, and the waveform is determined by the selection of the waveform stored in the waveform memory 40, and the selected waveform The frequency (period and initial phase) is determined by setting the readout frequency division ratio. After these waveforms and frequencies are digitally specified, their amplitudes are set. The characteristic feature of the periodic waveform generation circuit of the embodiment is that the waveform selection and the readout frequency division ratio are processed separately, and in particular, the readout frequency division ratio is determined by inputting the readout frequency (period) from the outside. It has the advantage that any frequency can be set using only the waveform memory 40, and a large number of waveforms can be generated even though the amount of data stored in the waveform memory 40 is limited. The details of the periodic waveform generation circuit of this embodiment will be explained below. In the embodiment, the waveform memory 40 is a ROM.
Alternatively, it is formed using a RAM or the like, and a plurality of waveforms are stored therein. Table 1
An example of a waveform stored in the waveform memory 40 is shown in FIG. The waveforms stored in the waveform memory 40 in this manner are selected by the waveform number S supplied from the waveform selection memory 42 and configured with 4-bit numerical data, and the selected waveform consists of one wavelength. is output as data. Such reading of data for one wavelength is performed by sequentially reading and outputting waveform data at a predetermined sampling period based on a sampling address signal supplied from the periodic address output circuit 43. In the embodiment, this periodic address output circuit 43 includes a frequency memory 44 and an accumulation memory 4.
6 and an adder 48, and the reading cycle of the waveform selectively outputted from the waveform memory 40 described above is determined by the frequency data F supplied from the frequency memory 44. Note that the initial phase of this readout frequency is
It is written and stored in the accumulation memory 46 by an initial phase setting circuit (not shown). That is, the circuit of the embodiment has an accumulation memory 4
6 and an adder 48 constitute an accumulator, and the adder 48 adds the frequency data F supplied from the frequency memory 44 and the accumulated value B accumulated and stored in the accumulation memory 46, If a write pulse WP is input, an update operation is performed to update the memory contents of the accumulation memory 46 as a new accumulated value. Therefore, the accumulated data B in the accumulated memory 46 is sequentially increased by the frequency data F supplied from the frequency memory 44 every time the write pulse WP is supplied. The periodic waveform generation circuit supplies the new accumulated data B written in the accumulated memory 46 to the waveform memory 40 as a sampling address signal every time the update operation is performed. Then, a sampling operation is performed to read out the waveform data specified by the accumulated data B from the waveform selected by the waveform number S. In addition, to give an example of the number of bits of each circuit part in the periodic waveform generation circuit of the embodiment, the frequency data F is set to 20 to ensure frequency accuracy.
The bit and cumulative value B are set to 21 bits. However, the waveform data selected by the accumulated value B does not require as much as ²²¹ words of bits, so only the upper 5 bits of B (B
2 ^21-5 = 65536 and rounded down to the decimal point) is used as sampling address information, that is, phase angle information. Therefore, the waveform data read from the waveform memory 40 is 2 ⁵ =
It will be 32 words. Each word thus read indicates the amplitude of the waveform. Since one word of waveform data is 4 bits, one waveform data is 32×4=128 bits. Furthermore, since the waveform number S is 4 bits and 16 types of waveforms can be registered, the total waveform memory is 128 bits x 16 = 2048 bits. Table 2 shows only the accumulated data B for each sampling for one type of waveform and an example of the waveform data output from the waveform memory 40. Nn (n=0, 1, 2, 3,
4,...) is a symbol representing the "n" sampling, SD-0 in the waveform data column is the output waveform data based on Table 1 when the waveform number S = 0, and SD-7 is the waveform number. S=
7 represents output waveform data based on Table 1. Here, it is assumed that the frequency data F in the initial state is F=010000H, and the accumulated data B is B=00H. Here, the H at the end indicates that the number represented is a hexadecimal number. First, it is assumed that the waveform number S=0H is selected by the waveform number S. In the case of sampling N0, the waveform number is S=0H, so the upper 4 bits of the address of the waveform memory 40 are
0000, and the cumulative data B is B=00H, so the lower 5 bits of the address of the waveform memory 40 are 00000, and the data from the waveform memory 40 is
Waveform data "7" designated by the address 000000000, ie, 000H, is sampled and read out. Similarly, for sampling N1, S
=0H, and the accumulated data B5 bit is 01H, so the waveform data "9" at 001H, where the upper 4 bits and lower 5 bits of the address of the waveform memory 40 are 0000 and 00001, respectively, is sampled and read out. In this way, the accumulated data B is sequentially filled with F
As a result, the top five bits of the accumulated data B change sequentially as shown in Table 2 each time each sampling operation is performed.
The waveform data S=01H selected in Table 1 is sequentially sampled and read out at predetermined intervals. FIG. 13 shows an output waveform diagram of the waveform selected by the waveform number S=0H, and as is clear from the figure, it can be seen that when the waveform is selected by S=0H, a sin waveform is obtained. In the figure, the horizontal axis represents the number of samplings, and the vertical axis represents the analog amount of sampled waveform data. Note that the above explanation is based on the waveform number S=0H
Although the explanation has been given by taking as an example the case where the sine waveform is selected by As shown in the SD-7 column of
The waveform data of the waveform selected by 7H is sequentially sampled and read out. FIG. 14 shows the waveforms sampled and read out in this way, and as is clear from the figure, it can be seen that when the waveform is selected with S=7H, a sawtooth wave is output. As described above, according to the periodic waveform generation circuit of the embodiment, it is possible to arbitrarily select and output the waveform selected by the waveform number S from a plurality of waveforms preset in the waveform memory 40, and therefore the waveform By simply presetting an appropriate waveform in the memory 40, a desired waveform can be output. Next, the readout frequency f of the waveform sampled and read out in this manner will be considered. Focusing on the value of cumulative data B in Table 2,
The value of B at the initial state N0 is equal to the value at N20. This means that after 20H cycles from N=0, the adder 48 overflows and the value of sampling address B becomes the same value as the initial state, and the sampling address of the waveform memory 40 returns to its initial state. During this period, a periodic waveform of one wavelength is output. The period corresponding to this one wavelength is defined as "one period". In this example, the entire cumulative data B (21
1 while the value of bit) increases by 200000H
It becomes a cycle. However, the number of cycles required to obtain one cycle of the waveform changes depending on the value of the frequency data F. That is, if the interval between increases in the cumulative data B is short, a large number of sampling cycles are required to obtain one cycle of the waveform, and if it is long, one cycle of the waveform can be obtained with a small number of sampling cycles. Here, if the number of sampling cycles occurring during one period is Ns, and the number of bits of accumulated data B is M, then Ns=2 ^M /F (1). Further, if the time required for one sampling, that is, the time required for one sampling cycle is ts, and the time related to one cycle is Ts, then Ts=Ns·ts. Therefore, the frequency f of the output waveform is f=1/Ts=1/Ns・ts=F/ts・2 ^M ...(2) where ts is a constant, so the frequency f of the output periodic waveform is The frequency f is determined by the value F of frequency data. This means that the frequency f of the output periodic waveform can be set arbitrarily, regardless of the value of the frequency data F. In this way, the reading period of the periodic waveform from the waveform memory 40 can be shortened when the value of the frequency data F set in the frequency memory 44 is large, and can be made long when the frequency data F is small. When considering the case of reading out the waveforms shown in Table 2 above, in Table 2,
Waveform data is sequentially read out every sampling cycle. If the value 010000H of the frequency data F is smaller and there is no change in the contents of the upper 5 bits of the accumulated data B at the end of one cycle of sampling operation, the value of the waveform data sampled and output from the waveform memory 40 will also change. do not. In such a case, the sampling operation is repeated for several cycles (multiple readings are performed) until the contents of the upper five bits of the accumulated data B change, and the output frequency of the periodic waveform becomes lower accordingly. Conversely, if the value of the frequency data F is greater than 010000H and the value of the upper five bits of the accumulated data B is accumulated over 02H during one sampling cycle, the waveform data is read out in an interlaced manner. In this case, the output frequency will be higher, but the harmonic components of the waveform will be impaired. As explained above, in the periodic waveform generation circuit of the embodiment, it is possible to set the desired waveform number S and frequency data F in the waveform selection memory 32 and frequency memory 44, and therefore, the desired waveform number S and frequency data F can be set in the waveform selection memory 32 and the frequency memory 44. By setting , it is possible to generate an arbitrary waveform from the waveform memory 40 at an arbitrary frequency. Although the case where one periodic waveform is outputted by the periodic waveform generation circuit has been described above, it is also possible to obtain a periodic waveform by combining a plurality of waveforms by using a time division multiplexing technique. In this case, as the number of channels increases due to multiplexing, the sampling frequency for each channel becomes lower, but this sampling frequency should theoretically be at least twice the upper limit of the frequency band required for the output waveform. frequency. The time-division sampling is performed cyclically for each channel, and by performing predetermined filtering on the waveform output via the DA converter and removing frequencies outside the necessary frequency band, This makes it possible to obtain a complete composite waveform from periodic waveforms of multiple channels. Note that in the periodic waveform generation circuit of the embodiment, each memory has a predetermined storage element, e.g.
They are formed at different addresses in RAM. (B-2) Noise waveform generation circuit The noise waveform generation circuit of the embodiment replaces the periodic address output circuit 43 of the periodic waveform generation circuit shown in FIG. When used as a circuit, a random-shaped noise waveform is generated at an arbitrary cycle by randomly reading out an arbitrary waveform at a predetermined cycle from a plurality of waveforms stored in advance in the waveform memory 40. FIG. 3B shows such a noise waveform generation circuit according to the present embodiment, and the circuit according to the embodiment generates an arbitrary waveform stored in the waveform memory 40 according to the waveform number S supplied from the waveform selection memory 42. is selected, and the selected waveform is generated by the sampling address (random number) address output circuit 45 configured with the random number generation circuit of the present invention.
It is read out and output at random using random numbers supplied from . That is, the random number generation circuit of the present invention forming the random number address output circuit 43 supplies random numbers at predetermined time intervals, and by supplying the thus supplied random numbers to the waveform memory 40 as a sampling address signal. , from the waveform memory 40, the waveform number S
The waveform data specified by the random number is sampled and read out from the waveform selected by the random number. Therefore, the waveform data sampled and read out in this manner is different from the periodic waveform sampled readout, and because the sampling address changes randomly, the waveform data as a whole is output as a noise waveform whose waveform changes randomly. . In this embodiment, the random number output from the random number address output circuit 45 is set to 16 bits, and a predetermined 5 of this 16 bit random number is set to 16 bits.
Only the bits are supplied to the waveform memory 40 as sampling addresses. In the above explanation, the noise waveform generation circuit of the embodiment outputs one noise waveform as an example. However, the noise waveform generation circuit of the embodiment can perform time division multiplexing like the periodic waveform generation circuit described above. By using this method, it is also possible to obtain a noise waveform that is a composite of multiple waveforms. (B-3) Characteristics of this embodiment A characteristic feature of this embodiment is that the operation of the periodic waveform generation circuit and the operation of the noise waveform generation circuit can be performed at different timings to achieve the same operation. adders 28, 36,
48, and the same waveform memory 40 can be used for the periodic waveform generation circuit and the noise generation circuit to perform the periodic waveform generation operation and the noise waveform generation operation. By sharing the adder and waveform memory used in the periodic waveform generation circuit and the noise waveform generation circuit in this way, it is possible to simplify the overall circuit configuration and increase its degree of integration, thereby reducing the cost of the entire device. Can be done. Next, a circuit formed by combining the periodic waveform generation circuit shown in FIG. 3A and the noise waveform generation circuit shown in FIG. A specific example will be explained. (C) Specific Example Figure 4 shows a circuit that can arbitrarily switch between the functions of generating periodic waveforms and generating noise waveforms, and the circuit of the example has 16 channels. However, both functions can be freely switched and used for each channel. The circuit of the embodiment is formed by combining the periodic waveform generation circuit shown in FIG. 3A and the random number generation circuit shown in FIG. 3B in principle.
The circuits shown in FIG. 1 and FIGS. 3A and 3B only show their principle diagrams, and therefore have somewhat different circuit configurations from the circuit of this embodiment. The circuit of the embodiment has RAM50 and
Each memory 24, 26, 34, 4 shown in FIG. 3A and FIG. 3B is stored in different addresses of the RAM 50.
2, 44, and 46 are formed. The memory area formed in this way is called a sound port, and in this embodiment, it has a fixed 8-byte area for each channel as a sound port when periodic waveforms are generated and a sound port when noise waveforms are generated. are doing. Figure 5 shows the memory contents of such a sound port. Figure 5A shows the memory contents of the sound port used when generating periodic waveforms, and Figure 5B shows the memory contents of the sound port used when generating noise waveforms. It shows. The data symbols in each of these sound ports are as shown in Fig. 1, Fig. 3A, and Fig. 3B.
The same data symbols used in the above are used. In FIG. 5A, frequency data F and cumulative data B are F0, F1,
The sound ports are stored in three parts, F2, B0, B1, and B2. This is Figure 3A
As explained in , the data F and B stored in the frequency memory 44 and the accumulation memory 46 of the embodiment are of 20 bits and 21 bits, respectively, whereas the circuit of the embodiment shown in FIG. Since the adder 52 used in is of 8 bits, each data F and B is
This is because the addition cannot be performed unless it is divided into bits. Note that the addition of the frequency data F and the accumulated data B explained in FIG. 3 is performed sequentially from the lower order side of each data shown in FIG. 5A, taking into account a carry signal. Further, in the sound port for noise waveform generation shown in FIG. 5B, the SR stored in the random value memory 34 is divided into SR0 and SR1 and stored in order from the lower order. This is because the memory capacity of the random value memory 34 is 16 bits.
This is because the adder 36 has only an 8-bit addition capacity. Furthermore, data G0 and G1 common to both sound ports shown in FIGS. 5A and 5B are waveform gains. This gain is outputted from the sound port of the RAM 50 at the same time as the output of the waveform data from the waveform memory 40 shown in FIG. The signal is multiplied by the waveform data and output as an analog signal. Therefore, the amplitude of the waveform data read from the waveform memory 40 is controlled by this gain. In the example, this gain is typically
Although G0 is used, for example, when outputting a stereo waveform, the amplitude of the waveform can also be adjusted using gain G1 independently of this gain G0. Furthermore, in both sound ports shown in FIGS. 5A and 5B, N is a data bit that switches between the periodic waveform generation operation and the noise waveform generation operation of the circuit, and the channel whose function can be switched by this N is , is not the channel corresponding to the sound port where the N exists, but is the channel on which sampling will be performed next. This is because data N is read out at the end of one sampling process. In the embodiment, the sound ports shown in FIGS. 5A and 5B as described above are formed in the RAM 50, respectively. The CPU accesses data from each of these sound ports on a time-sharing basis in synchronization with the CPU bus cycle according to a predetermined program. That is, one sampling process of one channel in the embodiment is divided into four processes in order to perform time-division access to the RAM 50. Therefore, in the circuit of the embodiment, sampling of 16 channels is performed. In order to complete the process, it is necessary to execute time-division access of 4×16=64, that is, 64 cycles. Next, the operation of the circuit shown in FIG. 4 will be divided into periodic waveform generation operation and noise waveform generation operation, and the sampling process will be explained. Note that when performing such an operation, there are actually intermittent periods in which the CPU occupies the RAM 50, but in this embodiment, the multiplexer 58, which controls time division of RAM addresses, is set on the channel and port selection signal side. CPU as
The explanation of the RAM occupation period will be omitted. (C-1) Periodic waveform generation operation First, the operation for generating a periodic waveform using the circuit shown in FIG. 4 will be explained. As shown in the principle of the periodic waveform generation circuit shown in FIG. 3A, the operation is such that the sound port frequency data F and cumulative value data B shown in FIG. An arbitrary waveform is read out from the waveform memory 40 based on the accumulation result, and then the waveform amplitude is determined by the gain G0 of the sound port shown in FIG. 5A, and the waveform is outputted from the DA converter 56 as an analog signal waveform. Hereinafter, this waveform generation operation will be explained separately into an operation of accumulating frequency data F and accumulated data B, and an operation of reading a periodic waveform from the waveform memory 40 based on the accumulation result. First, this waveform data F and cumulative value data B
For the accumulation, the adder 52 is used as the adder 48 shown in FIG.
It is divided into three steps: F2 + B2. That is, in the circuit of the embodiment, when the random number mode flip-flop 60 is cleared, the timing and control circuit 62 causes the entire circuit to operate as a periodic waveform generating circuit. (First step) As a result, as shown in FIG. 6, the circuit clears the carry flip-flop 64 as indicated by the arrow, and its stored contents are set to 0. Subsequently, from the sound port of the RAM 50 shown in FIG. . Here, the multiplexer 70 selects the waveform number mask circuit 72 side. At this point, the waveform number mask circuit 72 is in a data transparent state. Therefore, the data F0 and B0 stored in the latch circuits 66 and 68 are supplied to the adder 52, and the accumulated value Y=F0+B0+CY is calculated. In addition,
In this calculation of the lowest data, since CY=0, the output of the adder 52 becomes Y=F0+B0. Simultaneously with the completion of this operation, a write pulse is supplied from the timing and control circuit 62 to the RAM 50, and at the same time, the 3-state buffer 74 opens and the adder 50
The calculation data Y=F0+B0 of 2 is stored in the B0 write area of the sound port shown in FIG. 5A in the RAM, that is, in the accumulation memory 46. In this way, first, the accumulated value of the lowest side
B0 is updated to the new cumulative value and stored. At this time, if a carry occurs due to the operation of F0 + B0, "1" is sent, and if no carry occurs, "0" is sent from the Co terminal of the adder 52 as a carry signal CY, as shown by the arrow. It is held in a leaf flip-flop 64. (Second step) After completing this series of operations, the next step is
The computation of F1 and B1, that is, the computation of the second step is started. This operation, similar to the operation in the first step, reads F1 and B1 from the sound port shown in FIG. Because the carry flip-flop is connected to the CI input terminal of adder 52 through multiplexer 76, the carry signal held in the carry flip-flop in the first step
Perform calculations that take CY into account, and calculate calculation data Y=
F1+B1+CY as sound port data B1
In the storage area, i.e. the cumulative memory 46,
Write and store as new data. Also,
At the same time, the contents of the carry flip-flop 64 are also updated. (Third Step) When the second step is completed, the calculation of the third step is started as shown in FIG. This calculation is as shown by the arrows and
The process begins by reading and latching data F2 and S into latch circuit 66 from the sound port shown in FIG. At this time, the waveform number mask circuit 72 adds "0" as bit 5 to the lower 4 bits corresponding to F2 stored in the latch circuit 66, expands the data F2 to 5 bits, and sends the data to the adder 5.
Supply to 2. In this way, the adder 52 receives the data supplied from the latch circuits 66 and 68.
Accumulate F2 and B2, and as shown by the arrow,
The cumulative value Y = F2 + B2 + CY is calculated in the same way as above.
B2 storage area of the sound port shown in FIG. 5A in the RAM 50, that is, the cumulative memory 46
It is written and stored as new data in the memory. At this time, the carry flip-flop 64 is not updated in the calculation of the third step, but since the carry flip-flop 64 still holds CY in the second step, it is used as an arbitrary value for the next sampling operation. Cleared first. (Fourth Step) When the accumulation operation consisting of the first to third steps is completed, the waveform data stored in the waveform memory 40 is next read out as shown in FIG. That is, at the end of the third step, the adder 52 outputs the output value data (Y=F2+B2+CY), and at the same time, the waveform number S is output from the latch circuit 66 as shown by the arrow. The signal is output and supplied to the waveform memory 40 as a sampling address. When the output data Y and the waveform number S are supplied to the waveform memory in this manner, the waveform data stored in the waveform memory 40 is outputted to the waveform latch 54 as shown by the arrow. In addition, in conjunction with the sampling read operation of a series of waveform data, RAM5
From the sound port shown in Figure 5A of 0,
Gain G0 is read out and the read data is supplied to waveform latch 54 as indicated by the arrow. In this way, the waveform latch 54
The latched waveform data and the gain G0 are multiplied in the DA converter 56 having a multiplication function, and are simultaneously converted into analog signals and output until the waveform reading of the next sampling operation is started. Then, by repeating the sampling operation consisting of the first to fourth steps a number of times given by the above equation (1), one cycle of the arbitrary periodic waveform selected by the waveform number S is read out and output. Ru. As described above, in the circuit of the embodiment, by repeating the series of operations of the first to fourth steps described above for each channel, the periodic waveform stored in the waveform memory 50 can be read out at a desired readout period and gain. It can be read and output using G0. In addition, when obtaining a stereo effect, the waveform latch 54 and the DA converter 56 are connected to one another.
Prepare the 5th set in RAM50 in the same way as above.
By reading out the gain G1 from the sound port shown in FIG. A, it is also possible to read out a predetermined periodic waveform whose amplitude is determined by this gain G1. Further, in the circuit of the embodiment, each time the series of sampling operations of the first to fourth steps described above are completed, the data N read out from the sound port shown in FIG. The data N thus read into the flip-flop 60 determines whether the operation of the next channel is a periodic waveform generation operation or a noise waveform generation operation as described below. In this way, the circuit of the embodiment can output any periodic waveform shown in FIGS. 13 and 14, for example, at a desired period. The above is the periodic waveform generation operation in the circuit of this embodiment.Next, the noise waveform generation operation performed using the circuit of this embodiment will be explained. (C-2) Noise waveform generation operation In the circuit of the embodiment, the noise waveform generation operation is started by setting the output of the random number mode detection flip-flop 60 to 1,
In this way, the output of flip-flop 60 is
1, the timing and control circuit 62 controls the entire circuit to operate for noise waveform generation. When the noise waveform generation operation is started in this way, the circuit of the embodiment first operates as a shift pulse generation section for outputting the shift permission signal P as a first step, and then as a second step.
In the third step, it operates as a random number generator that generates random numbers based on the output shift permission signal P, and in the fourth step, it operates to generate a noise signal based on the generated random numbers. Each of these operations will be explained in step order below. (First step) At the same time as the noise waveform generation operation starts, the circuit of the embodiment, as shown in FIG.
It operates as a shift pulse generator 20. That is, the circuit of the embodiment clears the carry flip-flop 64 as shown by the arrow at the same time as the start of operation, and clears the carry flip-flop 64 as shown in FIG. 5B of the RAM 50.
Start reading the data from the random number generation sound port shown in . To read this data, as shown by the arrows and, the frequency data F and accumulated data B are read out from the memories 24 and 26 of the sound port shown in FIG. 68
Latch inside. The data F and B thus latched in the latch circuits 66 and 68 are accumulated in the adder 52 and output as the value Y=F+B. The value Y=F+B obtained in this way is stored as new accumulated value data B in the storage area of accumulated value data B shown in Sound Port FIG. 5B, as shown by the arrow.
That is, it is written and stored in the accumulation memory 26. This write operation is performed as follows. First, if the added value of the adder 52 overflows as a result of performing the arithmetic operation on data F and B, the value added by the adder 52 overflows as shown by the arrow.
A carry signal is supplied from the terminal of CO to the random number carry flip-flop 76, and as a result, the random number carry flip-flop 76 sends a shift permission signal P (third In figure B, adder 2
8) is output. Next, the timing and control circuit 62
A write pulse WP is output to the RAM 50, and the cumulative value data is updated. Hereinafter, the second and subsequent steps will be explained assuming that the shift permission signal P has been output. (Second Step) When the shift permission signal P is output from the random number carry flip-flop 76 in this way, the timing and control circuit 62
As shown in Figure 0, the entire circuit is controlled as a random number generator. In this way, when the circuit of the embodiment is controlled as a random number generator, the random number memory 3 is used in the random number generation sound port shown in FIG.
The lower random number SR0 is read out from the memory area functioning as 4 and latched into the latch circuit 68. At this time, the multiplexer 70 selects the latch circuit 68 side, and therefore, the data B0 latched in the latch circuit 68 is supplied to both input terminals of the adder 52, as shown by the arrow. . At the same time as this operation, the multiplexer 71 switches to the feedback value memory 78 side, and the feedback value read from the feedback value memory 78 is input to the carry input terminal CI of the adder 52, as shown by the arrow. The feedback value memory 78 is an addressable memory with a capacity equal to the number of channels, and in this embodiment (1 bit).
It is configured with ×16 RAM. The feedback value written and stored in the feedback value memory 78 is serial data input via the feedback circuit 12 during the previous random number generation operation. As a result, from the adder 52, Y=2×
The value of SR0+ (feedback value) is output, and this value
The data is written and stored as new data in the SR0 data area (random value memory 34) shown in FIG. 5B of the RAM 50. Simultaneously with writing such data, the 8-bit adder 52 supplies a carry signal CY=1 from the CO terminal to the carry flip-flop 64 as indicated by the arrow. In this way, when the update of the lower data SR0 is completed, the update of the upper data SR1 is started next. This operation is performed as shown in FIG. (Third Step) First, from the random number generation sound port shown in FIG. Data S representing the waveform number is read out from the sound port and latched into the latch circuit 66. When this latch operation is completed, since the multiplexer 70 has selected the latch circuit 68 side, the data SR1 latched in the latch circuit 68 is transferred to the adder 5 as shown by the arrow.
At the same time, the carry signal CY, which was supplied to both input terminals of 2 and held in the carry flip-flop 64 via the multiplexer 71 as shown by the arrow, is applied to the carry input terminal CI.
is supplied to As a result, the adder 52 outputs the value Y=2×SR1+CY including this carry signal CY, and as shown by the arrow, the SR1 data storage area (random value memory 34) as new data. In this way, new random numbers are written and stored in the sound port random number storage SR0 and SR1 memory areas (random value memory 34) shown in FIG. 5B. Further, addition data Y=2× from the adder 52
When SR1+CY is output, the feedback circuit 12
The feedback value for the next random number generation operation is written and stored in the feedback value memory 78 as shown by the arrow. (Fourth step) When a new random number is written and stored in the sound port shown in FIG. 5B in this way, the circuit of the embodiment then functions as a circuit for generating noise waveforms as shown in FIG. do. That is, at the end of the third step, S representing the waveform number is latched in the latch circuit 66, and the waveform number S is latched in the latch circuit 66.
is supplied to the waveform memory 40 as indicated by the arrow. At the same time, the adder 52 outputs the calculation result Y=2×SR1+CY of the third step, and the lower 5 bits of this output are used as a sampling address signal to determine the sampling position of the waveform data as shown by the arrow in the waveform memory. 40. As a result, waveform data is read from the waveform memory 40 and latched into the waveform latch 54 as indicated by the arrow. Simultaneously with reading out such waveform data, in the circuit of the embodiment, data G0 defining the amplitude is read out from the sound port as indicated by the arrow and latched into the waveform latch 54. When the waveform data and gain are latched in the waveform latch in this way, the value is transferred to the DA converter 56 as shown by the arrow.
The data are multiplied by each data and simultaneously output as an analog random number waveform signal. In this manner, the circuit of the embodiment outputs the waveform data of the selected waveform as a randomly sampled read noise waveform signal based on the generated random number. In addition, in the circuit of the embodiment, by further providing a pair of waveform latch 54 and DA converter 56, the gain G1 of the sound port can be read out as shown in FIG. 5B.
It is also possible to output a noise waveform based on G1. After the noise signal outputs a waveform, data N is read out from the sound port shown in FIG. 5B as indicated by the arrow, and determines the operation of the next channel. By repeating the sampling readout of the predetermined random waveform data consisting of the first to fourth steps as many times as given by the above equation (1), the waveform data of the periodic waveform selected by the waveform number S is obtained. is output for one period as a noise waveform. Next, an example of a noise waveform of an arbitrary channel obtained using the circuit of the embodiment will be explained. First, it is assumed that the sound port shown in FIG. 5B of an arbitrary channel has the contents shown in FIG. 5C at the start of the sampling operation.
In this case, the frequency data F is decimal number F=77
Therefore, the carry of accumulated data B occurs 77 times out of 256 times (cycles) of updating data B. At this time, the sampling frequency F is f=93.75 F=7218.75 [Hz] according to equation (4) described later. Table 3 shows calculation data for each step during the noise waveform generation operation of this embodiment, and the sampling process of this embodiment will be discussed in detail based on this calculation data. Here, as is clear from Fig. 5C, the waveform number is S = 0110 (binary number) = 6
(hexadecimal number), and the waveform number S=
If each waveform data of the waveform selected by 6 (hexadecimal number) is expressed in correspondence with its physical address 0C0 to 0CF, the waveform data of this area will be as shown in Table 4. First, as described in detail in the first step, the circuit of the embodiment is connected to the shift pulse generator 2.
When operating as 0, the value of accumulated data B is updated by F=01001101 (binary number) as shown below.

【table】

[Table] When the circuit of the embodiment performs the update operation of accumulated data B as the shift pulse generator 20, the adder 32 (adder 28 in FIG. 1) is activated in the second cycle, sixth cycle, In the 12th cycle, it overflows and outputs the shift permission signal P=1, and the random number generator 22 outputs the shift permission signal P=1, and the circuit is activated once every 3 or 4 cycles.
function as In Table 3, the SH column represents the cycle in which the circuit functions as the random number generator 22.
As is clear from Table 3, the circuit of the embodiment functions as a random number generator in cycles N2, N6, N9, NC... When the circuit functions as the random number generator 22 in this way, the feedback value is read out from the feedback value memory 78 as described in detail in the second step, and the adder 52 (in the circuit shown in FIG. It is input to the carry input terminal CI of the device 36). This feedback value was set based on the following logical formula when the random number was generated last time, and [Feedback value] = ([Bit 15] [Bit 13]) ([Bit 12] [Bit 10]) (However, AB represents the exclusive OR of A and B.) In the embodiment, for example, when a random number is generated for the first time, the feedback value is (01) (01) =
1, and when the second random number is generated, its feedback value becomes (10)(00)=0. The feedback value column of Table 3 shows the feedback values obtained in this way. The circuit of the embodiment includes the second step and the third step.
As described in detail in the step, each time it functions as the random number generator 22, the feedback value is used to output a random number as shown below, and the random number memory 34, that is, the SR1 of the sound port shown in FIG. 5B, The random numbers in the SR2 memory area are updated sequentially.

[Table] The random number column of Table 3 shows the random numbers updated in this way. Each time a random number is output in this way, the circuit of the embodiment updates bits 8 to 8 of the updated random number as detailed in the fourth step.
The 5 bits of bit 12 are used as the waveform data sampling address of the waveform memory 40. The sampling addresses output in this way are listed in hexadecimal numbers starting from the first random number update count as follows. 0B, 16, 0D, 1B, 16, 0D, 1A, 14 09, 12, 04, 04, 12, 05, 0B, 17 Here, the waveform number specified by the sound port shown in Figure 5C is S=
0110 (binary) = 6 (hexadecimal), therefore,
Considering the waveform number S, the address input to the waveform memory 40 will be the following 9-bit value corresponding to the above numerical sequence. 0CB, 0D6, 0CD, 0DB, 0D6, 0CD,
0DA, 0D4 0C9, 0D2, 0C4, 0D9, 0D2, 0C5, 0CB,
0D7 The address shown in this way is a random address, unlike the address at the time of generation of the periodic waveform shown in the figure, so the waveform data selected by the waveform number S=6 shown in Table 4 is randomly selected by the address. Read out. Table 5 shows the waveform data that is randomly read in this example, and by multiplying this value by the gain G0 = 1010A, the noise waveform data shown in the waveform latch output column of Table 5 is sampled. It can be output. FIG. 15 shows the noise waveform sampled and output in this way, and as is clear from the figure, according to the circuit of the embodiment, the waveform data of the waveform selected by the waveform number S is By randomly sampling and reading, it becomes possible to output a desired noise waveform. In this embodiment, the feedback value memory 78 is used when operating the circuit as a random number generator.
Although the present invention is not limited to this example, the present invention is not limited to this, and the present invention is not limited to this.
It is also possible to directly input the output of the feedback circuit 12 to the adder 12 without using the adder 8. As explained above, according to the circuit of this embodiment, when the periodic waveform generation circuit and the noise waveform generation circuit are combined, the main parts of the circuit, such as the adder 52 and the waveform memory 40, can be shared. As a result, it is possible to increase the degree of integration of the entire circuit and reduce costs. (C-3) Examination of data Next, we will examine specific data when the circuit of the embodiment is used as a periodic waveform generation circuit and a noise waveform generation circuit. (a) Frequency of periodic waveform First, the specific readout frequency f of the periodic waveform obtained by the circuit of the embodiment will be considered. (Sampling period of channel) The circuit of the embodiment performs time-division access to the data in the RAM 50 in synchronization with the CPU bus cycle f _BC , and as mentioned above, the sampling period of one channel is equal to the CPU bus cycle. Since this corresponds to four periods of the cycle, the sampling period per channel is 4/f _BC . In the embodiment, as described above, there are 16 channels, so the sampling period of each channel is 16×(4/f _BC ). (Number of samplings per waveform) Also, considering the number of sampling operations performed to read out one waveform, the cumulative memory 46 is 21 bits, and the cumulative data B is stored in F every time sampling is performed.
Since the accumulated value B in the waveform memory 46 overflows until the next overflow occurs, that is, the number of samplings N performed while reading one waveform is 2 ²¹ / It becomes F. (Period of output waveform) Therefore, by multiplying the sampling period by the cumulative number of samplings, the period 1/f of the output waveform can be found as follows: 1/f=16×4/f _BC × 2 ²¹ /F The frequency f of the output waveform is f=f _BC・F/16×4×2 ²¹ ……(3). In this embodiment, since the CPU bus cycle frequency f _BC is f _BC =1.536MHz, the frequency of the output waveform is f≒0.011444·F (Hz). Therefore, if it is desired to obtain an output waveform of f=440 (Hz), frequency data of F=38448 may be set in the sound port shown in FIG. 5A. (b) Sampling frequency of noise waveform Next, the sampling frequency f of the noise waveform performed under the same conditions as the frequency of the periodic waveform will be considered. Since the random number sampling is performed every time the 8-bit accumulation memory 26 overflows, the sampling frequency is determined by the following equation in the same way as equation (3) above. f=f _BC・F/16×4×2 ₈ =2 ^-14・f _BC・F
=93.75·F [Hz] (4) Therefore, in order to obtain a sampling frequency of 3 [KHz], it is sufficient to set frequency data of F=32 in the sound port shown in FIG. 5B. Next, the random number generation period for each channel
Considering T _RND , T _RND is 2 ¹⁶ −1=65535 times the sampling period 1/f, and is given by the following equation. T _RND = 2 ¹⁶ -1/f = 2 ¹⁴ × (2 ¹⁶ -1)/f
_BC・F=699.04/F [seconds]……(5) Therefore, if F=32, T _RND =21.845
It is understood that this is [seconds]. [Effects of the Invention] As explained above, according to the present invention, by using a time-sharing method, the number of parts in the circuit is reduced, and as a result, the degree of integration of the entire circuit is increased, and a low-cost random number generation circuit is provided. It becomes possible to provide

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【table】 [Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of a random number generation circuit used in the present invention, FIG. 2 is an explanatory diagram of a conventional random number generation circuit, FIG. 3A is a diagram of the principle of a periodic waveform generation circuit,
Figure B is a principle diagram of a noise waveform generation circuit, Figure 4 is a block diagram showing a preferred embodiment of the present invention, and Figure 5 is a periodic waveform generation sound port and random numbers stored in the RAM shown in Figure 4. 6 to 8 are explanatory diagrams of the circuit shown in FIG. 4 operating as a periodic waveform generation circuit, and FIGS. 9 to 12 are diagrams showing the circuit shown in FIG. 4. An explanatory diagram when operating as a noise waveform generation circuit, Fig. 13,
FIG. 14 is a periodic waveform diagram formed using a periodic waveform generation circuit, and FIG. 15 is a noise waveform diagram formed using a noise waveform generation circuit. 12... Feedback circuit, 20... Shift pulse output section, 22... Random number generation section, 32... Shift circuit,
40...Waveform memory.

Claims (1)

[Scope of Claims] 1. An accumulation memory that stores an accumulated value; the accumulated value and externally inputted frequency data are added together, and this added value is written and stored in the accumulated value as a new accumulated value. a shift pulse output section that outputs a shift pulse based on a carry signal generated when the cumulative value of the first adder overflows; a random value memory and a second addition; a shift circuit which functions as a shift register by adding a multiple of the contents of the random value memory using a second adder to update the contents of the random value memory every time the shift pulse is input; a feedback circuit that feeds back a feedback signal to a carry input terminal of the adder, and a random number generating section that generates a predetermined random number in the random number memory, the first adder and the second adder. The random number generation circuit is characterized in that the same adder is shared in time division. 2. The random number generation circuit according to claim 1, wherein the accumulation memory and the random number memory are formed in different addresses of the same memory. 3. In the circuit according to claim 1 or 2, the shift pulse output section includes a timing generation circuit that generates a predetermined timing signal, and the timing signal and the digit output from the first adder. A random number generation circuit characterized by outputting an AND output with a rising signal as a shift pulse.