JPH0241766B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital proportional-integral circuit that obtains an output digital signal by adding proportional-integral characteristics to a binary input digital signal.

Configuration of Conventional Example and Its Problems FIG. 1 is an electrical connection diagram showing a conventional example of an analog proportional-integral circuit, and FIG. 2 is a waveform diagram for explaining its operation.

The components of the analog proportional-integral circuit are an operational amplifier 1, an input resistor 2, a feedback capacitor 3, and a feedback resistor 4. Now, when a potential difference occurs between the input voltages E ₁ and E ₂ , a current flows through the input resistor 2, and the feedback capacitor 3 is charged with charge, causing the output voltage E ₀ to change.
As shown in Figure 2, the output voltage E ₀ decreases when E ₁ > E ₂ (~t ₁ , t ₄ ~ _{t 5} ), and stops when E ₁ = E ₂ (t ₁ ~ t 5 ). _t2 , _t3 ~ _t4 , _t5 ~), and when _E1 < _E2 , the potential increases ( _t2 ~ _t3 ). The transfer function G _(s) of this circuit is G _(s) = 1 + sT ₂ /sT ₁ (1). However, T ₁ = CR ₁ , T ₂ = CR ₂ , C is the capacitance value of feedback capacitor 3, R ₁ is the resistance value of input resistor 2, R ₂ is the resistance value of feedback resistor 4, and s is the Laplace operator. . When formula (1) is expanded, G _(s) = 1/sT ₁ +T ₂ /T ₁ ...(2). That is, it has proportional-integral characteristics of integral and proportional. Note that the magnitude of the current flowing through the input resistor 2 is proportional to the potential difference between the input voltages E ₁ and E ₂ , so
The charging and discharging of the feedback capacitor 3 is proportional to the potential difference. However, the slope of the potential of the output voltage E ₀ shown in FIG. 2 changes in proportion to the potential difference between E ₁ and E ₂ .

When converting such a proportional-integral circuit into an integrated circuit (IC), three input/output pins and external CR components are required, which hinders the reduction in external components and the number of pins due to IC conversion. Ta. In addition, it was susceptible to variations in CR components, changes in power supply voltage, changes in temperature, changes over time, etc. Furthermore, if it is desired to switch the frequency characteristics to multiple modes using a mode command signal, there are problems such as the need for more external components.

Purpose of the Invention The present invention solves the above-mentioned conventional problems.
The present invention provides a digital proportional-integral circuit in which all components are digitalized and frequency characteristics can be switched by a mode command signal.

Structure of the Invention The present invention comprises: variable frequency dividing means for switching the frequency division ratio of clock pulses in response to a mode command signal; gate means for inhibiting the output of said variable frequency dividing means when an input digital signal is a predetermined value; an up-down counter which uses at least one most significant bit of the signal as an up-down signal input and the output of the gate means as a clock input; variable multiplication means that switches a coefficient by which the input digital signal is multiplied by the mode command signal; A digital proportional-integral circuit comprising an addition or subtraction means for adding or subtracting the output of the down counter and the output of the variable multiplication means, and obtaining an output digital signal corresponding to the mode command signal from the addition or subtraction means. All components are digitalized, and the gain in the low frequency region and the gain in the high frequency region, that is, the frequency characteristics, can be switched by a mode command signal. Further, the present invention is configured to use proportional frequency dividing means in place of the gate means, and in the proportional frequency dividing means, the output of the variable frequency dividing means is proportional to the absolute value of the difference between the input digital signal and a predetermined value. The performance of the proportional-integral circuit can be improved by configuring the frequency to be divided into frequencies and using this output as the clock for the up-down counter.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 is a block diagram showing one embodiment of the present invention, FIG. 4 is its operating waveform diagram, and FIG. 5 is a frequency characteristic curve showing proportional-integral characteristics.

In FIG. 3, 5 is a variable frequency dividing means, 6 is a gate means, 7 is an up/down counter, 8 is a variable multiplication means, 9 is an addition means, _D1 is a binary input digital signal, and _D2 is an up/down counter. The output of the down counter, _D3 is the output of the variable multiplication means, _D4 is the output digital signal, s1 is the clock pulse, s2 is the output of the variable frequency division means, and s3 is the output of the gate output stage.

The clock pulse s1 is frequency-divided by the variable frequency dividing means 5 at a predetermined frequency dividing ratio according to the mode command signal, and the frequency-divided output s2 is inputted to the gate means 6. In the gate means 6, when the input digital signal D ₁ is equal to the predetermined value D ₀ (D ₁ =D ₀ ), the divided output s2 is output.
is prohibited, and when they are not equal (D ₁ ≠D ₀ ), the divided output s2 is used as the gate output s3, and is used as the clock input of the up-down counter 7. On the other hand, at least one bit of the most significant bit of the input digital signal _D1 is input to the up-down counter 7 as an up-down signal, and the gate output s3 is counted up or down. Then, an output signal _D2 is obtained by integrating the input digital signal _D1 from the up-down counter 7. Further, the input digital signal _D1 is input to the variable multiplier 8, and multiplied by a coefficient K corresponding to the mode command signal. Then, in the addition means 9, the output _D2 of the up-down counter 7 and the variable multiplication means 8
The configuration is such that _{the added output D 4 is} obtained as an output digital signal.

To explain the operation of FIG. 3 with reference to FIG. 4, the operation of the up-down counter 7 is switched between up and down (or down and up) depending on whether the input digital signal _D1 is larger or smaller than a predetermined value. That is,
The output D ₂ has a relationship between D ₁ and D ₀ such that D ₁ > D ₀ (or D ₁ <
When D ₀ ), count up (t ₂ to t ₃ ), and D ₁ = D ₀
Counting stops when (t ₁ ~ _{t 2} , t ₃ ~ t ₄ , t ₅ ~), D ₁
When <D ₀ (or D ₁ >D ₀ ), count down (~
t ₁ , t ₄ to t ₅ ).

Here, to detect whether D ₁ >D ₀ or D ₁ <D ₀ , it is sufficient to use at least one most significant bit of the input digital signal D ₁ . That is, the input digital signal
When D ₁ is 6 bits and the predetermined value D ₀ is 100000 (this means that the most significant bit is 1 and the lower bits are all 0)
For example, if the most significant bit of D ₁ is 1, set D ₁ > D ₀ , and if it is 0, set D ₁ < D ₀ , then you can easily detect whether it is large or small. be. In this case, similar detection is possible even if the predetermined value D ₀ is set to 011111.

In the above example, input digital signal with predetermined value D ₀
D is set to 1/2 of ₁ , but 1/4, 3/4
It is also possible to set the value to a value of . In this case, the most significant two bits may be used as an up-down signal, and a logic circuit (decoder) for detection is required.

On the other hand, in the gate means 6, the input digital signal
D ₁ is decoded, and when D ₁ =D ₀ , a prohibition signal is obtained and gate output of the frequency-divided output s2 is prohibited.

Here, the time constant T ₁ in equation (2) can be obtained as T ₁ =1/ _CK (3). However, _CK is the frequency of the clock pulse input to the up-down counter 7. This clock frequency _CK is the frequency of a divided output s2 obtained by dividing the clock pulse s1 by the variable frequency dividing means 5 in accordance with the mode command signal.

Variable multiplication means 8 which multiplies the output D2 of the integrating circuit consisting of the variable frequency dividing means 5, the gate means 6, and the up-down counter ₇ and the input digital signal _D1 by a coefficient K.
If the output D ₃ of is added in the adding means 9, we get
The proportional element T ₂ /T ₁ in equation (2) can be added.
That is, T ₂ /T ₁ =K (4).

As described above, the proportional integral circuit can be fully digitalized, and the frequency dividing ratio of the variable frequency dividing means 5 can be switched according to the mode command signal, so that the frequency of the divided output s2 can be changed.
_1a , _1b , _1c ... are divided by 2π times, and the coefficients to be multiplied by the variable multiplier 8 are K _a , K _b , K _c ... As shown in FIG. 5, the object of the present invention is achieved. It is possible to switch the gain in the low frequency region and the gain in the high frequency region, that is, the frequency characteristics of the proportional-integral circuit.

Here, from equations (3) and (4), T ₂ = 1/ _CK ... (5) Therefore, as shown in Figure 5, for example, the corner frequency ₂ due to T ₂ can be set regardless of the mode command signal. If it is to be kept constant, the coefficient K may be changed in proportion to the clock frequency _CK . That is, frequencies _1a , _1b ,
This can be achieved by setting the coefficients for _1c as _Ka , _Kb , _Kc, etc. Note that this is an example in which the corner frequency ₂ is kept constant, and it goes without saying that the clock frequency _CK and the coefficient K can be changed to desired values using the mode command signal.

Note that the operation of the up-down counter 7 is expressed as D ₁
If the configuration is such that it counts down when >D ₀ and counts up when D ₁ <D ₀ , the addition means 9 is used as a subtraction means, and the output of the up-down counter 7 is
By subtracting the output D ₃ of the variable multiplier 8 from D ₂ , the output digital signal D ₄ relative to the input digital signal D ₁ can be made negative in polarity.

Next, FIG. 6 is a block diagram showing a second embodiment of the present invention, which differs from the embodiment in FIG.
Proportional dividing means 1 instead of gate means 6 in FIG.
This is the point using 0. D ₀ is a predetermined value, and s4 is the output of the proportional frequency dividing means 10. The proportional frequency dividing means 10 receives the frequency divided output s2 of the variable frequency dividing means 5, divides the frequency into a frequency proportional to the absolute value of the difference between the input digital signal _D1 and the predetermined value _D0 , and outputs the frequency divided output s4. This is used as the clock input for the up-down counter 7. As a result, an up count proportional to the absolute value of the difference between the input digital signal D ₁ and the predetermined value D ₀ |D ₁ −D ₀ |
It is possible to count down. This is exactly the first
This is a digital implementation of the conventional example shown in the figure in which the feedback capacitor is charged and discharged in proportion to the input potential difference. Here, the clock frequency of equation (3)
_CK is the lowest frequency of the output s4 of the proportional frequency dividing means 10;
That is, it is the frequency when |D ₁ −D ₀ |=1.

The up-down counter 7 of the first and second embodiments described above decodes the count output D ₂ and outputs D ₂
The input of clocks s3 and s4, which are input when is the maximum and minimum value, is prohibited, and when the maximum value is detected, the clock input is prohibited with the next down command, and when the minimum value is detected, with the next up command. Add a function to cancel. Thereby, overflow and underflow of the up-down counter 7 can be prevented.

It goes without saying that if a plurality of necessary clock pulses are prepared, the same purpose can be achieved by using a clock selection means based on a mode command signal instead of the variable frequency dividing means 5.

Effects of the Invention As is clear from the above explanation, all the components are digitalized, and the gain in the low frequency region and the gain in the high frequency region of the proportional-integral circuit can be individually switched according to the mode command signal, that is, the frequency characteristics can be adjusted to the desired frequency characteristics. It can be switched to a characteristic that is suitable for IC conversion,
Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is an electrical connection diagram showing the conventional configuration of an analog proportional-integral circuit, FIG. 2 is its operating waveform diagram, FIG. 3 is a block diagram of one embodiment of the digital proportional-integral circuit of the present invention, and FIG. 5 is a diagram of its operating waveforms, FIG. 5 is a diagram of its frequency characteristic curve, and FIG. 6 is a block diagram of another embodiment of the present invention. 5... variable frequency dividing means, 6... gate means, 7...
...Up-down counter, 8...Variable multiplication means,
9...Addition or subtraction means, 10...Proportional frequency division means.

Claims (1)

[Scope of Claims] 1. Variable frequency dividing means for switching the frequency division ratio of the clock pulse in response to a mode command signal, gate means for inhibiting the output of the variable frequency dividing means when the input digital signal is a predetermined value, and an up-down counter that uses at least one most significant bit of the signal as an up-down signal input and that uses the output of the gate means as a clock input; variable multiplication means that switches a coefficient by which the input digital signal is multiplied by the mode command signal; comprising an addition or subtraction means for adding or subtracting the output of the down counter and the output of the variable multiplication means;
A digital proportional-integral circuit characterized in that an output digital signal corresponding to the mode command signal is obtained from the addition or subtraction means. 2. variable frequency dividing means for switching the frequency division ratio of the clock pulse according to a mode command signal; and proportional frequency dividing means for dividing the output of the variable frequency dividing means into a frequency proportional to the absolute value of the difference between the input digital signal and a predetermined value. and an up-down counter which takes at least one most significant bit of the input digital signal as an up-down signal input and the output of the proportional frequency dividing means as a clock input, and switches a coefficient by which the input digital signal is multiplied by the mode command signal. It comprises variable multiplication means and addition or subtraction means for adding or subtracting the output of the up-down counter and the output of the variable multiplication means, and the addition or subtraction means generates an output digital signal corresponding to the mode command signal. A digital proportional-integral circuit characterized by the following: