JPH0241956B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a chroma signal processing circuit for a video signal reproducing machine that handles PAL (CCIR) signals, and in particular,
It is most suitable for use in a playback device capable of variable speed playback, such as a review. FIG. 1 shows a recording pattern on a tape when a PAL signal is recorded on a rotating two-head VTR. In this VTR, the A head is one of the rotating magnetic heads, while the B head is in the direction of drum rotation.
It is provided at 180° + α (advanced phase). For example, α is 0.5 of the angular interval (H interval) obtained by dividing 180° by 312.5 (the number of scanning lines in one field of the PAL system).
This is the angle equivalent to double (0.5H). On tape 1, the A head records odd field tracks (A track) T ₁ , T _{3 .} . . and the B head records even field tracks (B track) T ₂ , T ₄ . There is. The A track and the B track are recorded at different azimuths, as shown by the recording trace P _H of the horizontal synchronizing signal in FIG. If the inclination of the tracks is selected so that the difference in longitudinal arrangement between tracks A and B is 1H, the angular spacing between both heads is 180° + 0.5H, so the difference between tracks A and B is 1H.
Arrangement differences of 0.5H and 1.5H occur alternately with the tracks, and as a result, there are recording traces of horizontal synchronization signals between adjacent tracks in the direction perpendicular to the track longitudinal direction.
P _H are aligned. That is, recording is performed in a state where H alignment is achieved. When a PAL signal is recorded, one of the two chrominance components in the PAL signal (for example, the I signal) is transmitted with the phase reversed alternately for each scanning line, so if you focus on the chroma signal, it will be recorded. As shown by the hatching in FIG. 1, the pattern has opposite phases (I and ) every 1H. When the tape shown in Figure 1 is played back at variable speeds in modes such as queue and review (so-called picture search mode), the head scanning locus will span multiple tracks, and the sequential nature of the phase inversion for each 1H of the chroma signal will be disrupted. . On a screen produced by a reproduced signal in which this sequentiality is disrupted, normal colors and inverted colors (complementary colors) appear alternately each time the reproduced track changes. The present invention relates to a reproduced chroma signal processing circuit for obtaining a reproduced screen free of the color reversal phenomenon as described above,
In particular, it is an object of the present invention to provide a processing circuit that reliably detects a breakdown in line sequentiality of a reproduced chroma signal and performs correction with fewer errors. The reproduced chroma signal processing circuit of the present invention is a PAL
a first switch for switching between a reproduced chroma signal obtained by variable-speed reproduction of the signal by a video signal regenerator and a signal delayed by one horizontal scanning interval; and a reference signal of a subcarrier frequency located on the reference axis of the color vector. A second switch that switches between the two signals is phase-shifted by a predetermined amount, and the phase of the reproduced color burst signal whose phase is inverted for each horizontal scanning section with respect to the reference axis is compared with the output of the second switch. and a phase detector, the output of the phase detector is also configured to switch the first switch, the reference axis is the V axis of the color vector, and the predetermined amount is selected to be 180°. It is characterized by this. Embodiments of the present invention will be described below in comparison with conventional examples. FIG. 2 is a circuit diagram of a conventionally known line-sequential correction circuit for reproduced color signals of a PAL VTR. In Fig. 2, the reproduced chroma signal PB-C is divided into a route passing through the 1H delay line 2 and a route not passing through the 1H delay line 2, and these are selected by the changeover switch 3 in order to correct the line order of the chroma signal. The signal is led out to other circuits (such as a mixing circuit with a luminance system) via a gate switch 4. The chroma signal output from the switch 3 is also supplied to the limiter/burst gate 5, where the burst signal is generated by the burst gate pulse obtained from the monomulti 6 which operates in synchronization with the reproduction horizontal synchronization signal (reproduction H). Extracted.
This burst signal is given to a multiplier 7 for synchronous detection to detect its phase. A reference signal representing a normal burst phase is supplied from a reference signal forming circuit 8 to the other input of the multiplier 7. This reference signal forming circuit 8 is supplied with a 4.43 MHz reference subcarrier Ref locked to the reproduced pilot burst signal from an APC circuit (not shown). During recording, as shown in the vector diagram in Figure 3A, the APC is maintained even with alternating burst signals B _N (Nth line) and B _N+1 (N+1st line) whose phase is alternately inverted line by line with respect to the V axis.
Lock the circuit and APC with a phase of -90° average phase.
A subcarrier is generated, and as shown in FIG. 3B, the alternating burst and chroma signals are phase-inverted by 180°, and the APC subcarrier is delayed by 90°.
A pilot burst _PB obtained by gating this in the horizontal synchronization signal section is recorded. During playback, APC to playback pilot burst
The circuit is locked and a reference subcarrier Ref _sub in phase with the APC _sub of FIG. 3B is formed. Therefore,
This reference subcarrier is shown in Figure 3B.
By delaying the signal by 45° in the 45° shift circuit 9 and further delaying its output by 90° in the 90° shift circuit 10, reference signals Ref _N and Ref _N+1 which are in phase with the alternating burst are formed. These reference signals are transferred to the selector switch 11.
, f _H /2 pulses (f _H is the horizontal scanning frequency) are selected every 1H, and sent to the multiplier 7, where the reproduced burst signal is synchronously detected. The output of the changeover switch 11 is also supplied to the burst insertion gate switch 4 as a replacement burst signal. If the reference signal and the reproduced burst signal are in phase, a DC component is generated in the output of the low-pass filter 12, and when this is waveform-shaped by the Schmitt circuit 13, a detection signal as shown in FIG. 4A is generated at the burst signal position. This detection signal is sent to the adder 14, and the phase-adjusted pulse (Fig. 4B) of the reproduced horizontal synchronizing signal PB.
It is added to the signal differentiated by 5. The output of the adder 14 (FIG. 4C) is sent to the monomulti 16,
When there is a detection signal as shown in FIG. 4C, there is no negative trigger pulse, so the monomulti 16 does not operate. When the reproduced burst signal and the reference signal are in opposite phases, no detection output is generated from the multiplier 7, so the output of the adder 14 becomes as shown in FIG. works.
The output of the monomulti 16 is applied to a toggle type flip-flop 17, which is inverted, and the output of the changeover switch 3 is switched to the opposite phase (either 1H delay or no delay). As a result, the reproduced signal in which the line sequentiality (1H alternating inversion) of the chroma signal has been disrupted is corrected to match the reference signal. Next, FIG. 5 is a circuit diagram of a line-sequential correction circuit for color signals of a VTR according to the present invention. This correction circuit has various improvements over the conventional circuit shown in FIG. In FIG. 5, the reproduced chroma signal PB-C is
As in the figure, there are two routes: one that passes through the 1H delay line 2 and one that does not, and one of these is selected by the changeover switch 3. The output of the switch 3 is led out to a subsequent circuit via a burst insertion gate switch 4 and a pilot burst removal switch 20. The chroma signal applied to the reproduced burst signal phase inversion detection circuit 19 is not taken out from the output side of the changeover switch 3 as shown in FIG. The input, that is, the reproduced chroma signal PB-C is used. In the case of Figure 2, the burst phase detection signal is obtained from the signal after correcting the line-sequential collapse of chroma inversion, and the detected signal is fed back to the line-sequential correction circuit, so the detection delay is reduced. , and the changeover switch 3 is hunting (flapping operation) due to the time mismatch between the detection operation and the correction operation.
may cause. On the other hand, in the embodiment of FIG. 5, information about line-sequential distortion is directly obtained from the input reproduced chroma signal and correction is performed using feed forward, so the problem of hunting is avoided. In FIG. 5, the input reproduced chroma signal is sent to a burst gate switch 21 operated by a burst flag pulse BF, from which the burst signal is separated and sent to a multiplier 7 for synchronous detection. The other input of the multiplier 7 is supplied with the burst reference signal generated by the reference signal forming circuit 8 . In this embodiment, since the burst phase is detected by focusing only on the V-axis component, which is the inversion information of the burst signal, the reference signal generation circuit 8 detects the V-axis as shown in the vector diagram of FIG. 6A. 0° and 180° (π)
The reference signals Ref _N and Ref _N+1 are formed. These signals are the previously described 4.43M signal obtained from the APC circuit locked to the regenerated pilot burst signal.
The phase of the Hz reference subcarrier Ref _sub is adjusted by the phase adjuster 22, and the inverter 23 divides the phase into those with and without phase inversion, and these are selected alternately every 1H with the changeover switch 24. It is formed by The changeover switch 24 is switched by the f _H /2 pulse shown at D in the time chart of FIG.
This pulse is the reproduction horizontal synchronization signal PB.H in Fig. 7B.
The output of the PLL circuit 25 which is locked to the 1/2 frequency divider 2
It is formed by dividing the frequency in half by 6.
In the PLL circuit 25, the oscillation frequency is f _H (horizontal frequency)
The output of the VCO 27 is shaped by the shaping circuit 28, and this and the input horizontal synchronizing signal are compared by the phase discriminator 29, and the error output is smoothed by the loop filter 30 and then supplied to the control input of the VCO 27. , a pulse whose phase is locked to the reproduced horizontal synchronizing signal as shown in FIG. 7C is obtained from the output of the VCO 27. This f _H pulse is applied to the falling trigger type 1/2 frequency divider 2.
6, the f _H /2 pulse is formed to invert in the middle of each horizontal interval as shown in FIG. 7D. Since the changeover switch 24 for obtaining the 0 and π reference signals is switched by this f _H /2 pulse,
At a position far away from the horizontal synchronization signal as shown in Figure 7D.
A reference signal whose phase is alternately inverted to 0 and π for 1H is obtained. In the conventional circuit shown in FIG. 2, the reference signal was switched near the horizontal sync signal, so when a frequency or phase shift occurs in the reproduced horizontal sync signal during variable speed reproduction, the multiplier 7 There have been cases where the timings of the burst signal and the reference signal are shifted, resulting in erroneous detection. On the other hand, in this embodiment, since the reference signal is switched to 0 or π in the middle of the horizontal section, the above-mentioned inconvenience does not occur at all. Note that in the conventional circuit shown in Figure 2, the above f _H /2 pulse was formed by an AFC circuit of chroma reproduction system.
This is greatly affected by the drop in playback level when crossing different azimuth tracks, and in the part of the playback screen that corresponds to the noise bar, the f _H /2 pulse may become defective and cause false detection. Ta.
On the other hand, in the present embodiment shown in FIG. 5, a dedicated PLL circuit 25 is provided to generate the f _H /2 pulse, and the time constant of the loop filter 30 is made sufficiently longer than the period during which the noise bar occurs, so that the f _H /2 pulse is generated. Two pulses are always obtained with accurate phase. The reference signal formed as described above is sent from the output of the changeover switch 24 via the amplifier 31 to the multiplier 7, where it is synchronously detected with the reproduced burst signal (FIG. 7A). If the reproduced burst signal and the reference signal are in phase with respect to the V-axis component, a positive detection output DET as shown by the solid line in FIG. 7E is obtained in the burst period. Also, 1H of burst signal
When the sequential nature of the alternating phase inversions is disrupted and the reproduced burst signal and the reference signal have an opposite phase relationship with respect to the V-axis component, a detected output of opposite polarity as shown by the dotted line in FIG. 7E is obtained. The detection output of the multiplier 7 is applied to an integral filter 32 for suppressing high-frequency noise, and is integrated as shown in FIG. 7F. This integral filter 32 is an ideal filter matched to periodic pulses as shown in FIG. 7E, and is composed of, for example, a Miller integral circuit or a charge pump circuit. When the detected output has a reverse polarity, the filter output also has a reverse polarity as shown by the dotted line in FIG. 7F. The output of the filter 32 is sent to a Schmitts circuit 33 (or a level detection circuit), for example as shown in FIG.
A detection output is formed at the level shown by the chain line. This detection output is given to the set input of the RS flip-flop 34, and its Q output is applied to the changeover switch 3 of the chroma line sequential correction circuit as a chroma inversion detection signal.
sent to. The playback burst signal and the reference signal are V
If they are in phase with respect to the axial components, the flip-flop 34 remains set and its Q output "1" (seventh
In FIG. G), the changeover switch 3 is connected to the non-delay side, for example. When the reproduced burst signal and the reference signal have opposite phases with respect to the V-axis component, a filter output of opposite polarity is obtained as shown by the dotted line in FIG.
After being inverted at , it is applied to a Schmitt circuit 36 (which has the same trigger level as the Schmitt circuit 33). Therefore, in this case, since a reset signal is given to the flip-flop 34, its Q.
The output chroma inversion detection signal is inverted to level "0" as shown by the dotted line in FIG.
is switched to the opposite side (for example, to the 1H delay line 2 side). As a result, the sequentiality of the 1H alternate reversal of the chroma signal is maintained, and a reproduced screen without color reversal phenomenon can be obtained. In order to eliminate chattering in the outputs of the Schmitt circuits 33 and 36 and to ensure stable operation of the RS flip-flop 34, a latch circuit (D flip-flop) is connected between the outputs of the Schmitt circuits 33 and 36 and the input of the flip-flop 34. It may be inserted in between. A latch pulse is formed at the falling edge of the output of multiplier 7 (FIG. 7E). Further, in order to accurately detect the levels of the Schmitt circuits 33 and 36, a clamp circuit may be inserted before these Schmitt circuits, and an AC amplifier may be inserted after the integral filter 32. It is desirable that the clamp pulse be formed in the middle of the horizontal scanning section where there is no detection output from the multiplier 7. The output of the changeover switch 3 is sent to a burst insertion gate switch 4, and the reproduced burst signal is replaced with a replacement burst signal B'. As shown in the vector diagram of FIG. 6B, the switching burst signal is obtained by adding, in an adder 42, a signal obtained by phasing a π-phase reference signal using a 90° phase shifter 41 and a reference signal that is alternately inverted to 0 or π. formed by Note that the burst insertion gate switch 4 also outputs the variable speed playback mode signal even when the output of the AND gate 40 is output.
It is connected to the burst insertion side in the JOG section and in the burst flag pulse BF section. The output of the gate switch 4 is led out to a subsequent circuit through a pilot burst removal switch 20. This switch 20 is connected to the PLL circuit 25.
The pulse of FIG. 7 H whose pulse width is adjusted by the waveform shaping circuit 43 operating on the output of the VCO 27 (FIG. 7 C) and the reproduced horizontal synchronizing signal PB-H (FIG. 7 B)
The output of the OR gate 44 (FIG. 7I), which takes the OR with , is also turned off, thereby removing the pilot burst signal inserted into the horizontal synchronization signal section. In addition, when receiving black and white, ORGATE 4
The AND gate 45 after 4 is closed by the ACK signal, and the switch 20 is turned off. Next, an improvement in the discrimination ability (reduction in malfunctions) of chroma inversion discrimination using the V-axis detection method of this embodiment will be considered. First, in the conventional circuit, as shown in the vector diagram of FIG. 8A, a reference signal Ref, which is in phase with the alternating reproduction burst signals a _s and _s , is formed. The reproduced burst signal given to the multiplier 7 in FIG. (ω _c is the angular frequency of the subcarrier).
The orthogonal components n _x , n _y of the noise components are superimposed on the reproduced burst signals a _s and _s in the form of a normal curve, as shown by the vector a _s in FIG. 8A. If the power of this noise component is σ ² , then the square average values _x ² and _y ² of each orthogonal component each indicate the noise power σ ² . That is, _x ² = _y ² =σ ² (2) On the other hand, the reference signal given to the multiplier 7 is expressed as cos(ω _c t±π/4) (3). When the 1H alternate inversion of the reproduced burst signal and the reference signal are synchronized, the detection output of the multiplier 7 is [a _s cos (ω _c t±π/4) + n _x (t) cos ω _c t + n _y ( t) sinω _c t〕×cos(ω _c t±π/4)
...(4), and its DC component (output of filter 12)
teeth, Therefore, the noise power of the detection output from the multiplier 7 is: (n _x n _y is zero because it is a multiplication of orthogonal components and is mutually uncorrelated). Therefore, the detected output has an in-phase component a _s as shown, for example, by vector _s in FIG.
A normally distributed noise component with power σ ² is superimposed on the signal. When the 1H alternate inversion of the reproduced burst signal and the reference signal are asynchronous (reverse phase relationship), the detection output is [a _s cos (ω _c t±π/4) + n _x (t) cos ω _c t + n _y ( t) sinω _c (t)〕×cos(ω _c t〓π/4)
...(7), and its DC component is becomes. Therefore, in the case of non-synchronization, a DC component does not originally appear, but a noise component of power σ ² as shown at the origin in FIG. 8A mixes into the detected output. When the discrimination level (threshold level) of the detection output is set at a position of a _s /2 as shown by the dashed line in FIG. 8A, the error rate in discrimination of chroma phase inversion is minimized. That is, the shaded area in FIG. 8A
This is the probability that the area of E〓→〓 is incorrectly determined to be in phase even though it is originally in the same phase, and the probability that the area of the diagonal area E〓→〓 is incorrectly determined to be in phase even though it is originally in phase. The overall error rate is E=1/2E〓→〓+1/2E〓→〓...(9) Therefore, the discrimination level at which E is minimum is a _s /2
It is. This level can be determined by the addition ratio of the adder 14 shown in FIG. 2. For example, the output amplitude of the differentiating circuit 15 is set to 1 with respect to the amplitude of 2 of the detected signal. As can be seen from FIG. 8A, the greater the amplitude of the reproduced burst signal, the farther apart the noise distribution curves and, therefore, the error rate expressed by Equation 9 decreases. Next _, the discrimination ability of this embodiment will be explained with reference to the vector _diagram in FIG. Since it coincides with , it can be expressed as cos(ω _c t±π/2) ...(10). During synchronization, the multiplication output is [a _s cos (ω _c t±π/4) + n _x (t) cos ω _c t + n _y (t) sin ω _c t] × cos (ω _c t ± π/2)
...(11), and the DC component is It is. Therefore, when synchronizing

A detected component of [Equation] is generated, and a noise component n _y distributed according to the curve shown in FIG. 8B is superimposed on this component. The power of this noise component is _y ² =σ ² . In addition, in asynchronous mode, the multiplication noise output is [a _s cos (ω _c t±π/4) + n _x (t) cos ω _c t + _ny (t) sin ω _c t] × cos (ω _c t〓π/2)
...(13) and its DC component is becomes. Therefore, when asynchronous, the detected component has the opposite polarity to that when synchronized.

[Formula] is generated, and a noise component n _y (power σ ² ) distributed according to the curve in FIG. 8B is superimposed on this component. If the discrimination threshold level of chroma phase inversion is placed on the U axis in Figure 8B, the distance between this level and the noise curve is

[Formula], and therefore, the error rate of misclassification (area of the shaded area) is
Figure) is smaller than that. Detection output level from discrimination level U in Figure 8B

If the distance to [formula] is set to a _s /2 as before, the same error rate will result, but under this condition, the input of multiplier 7 is

[Formula] can be done

[Formula] Therefore, when comparing the S/N of the input signal between the conventional method and this method, becomes. In other words, in the V-axis detection method of this embodiment,
Even if the S/N is 3 dB worse, the error rate will be the same. As a result, it becomes possible to more accurately detect the collapse of line sequentiality of chroma phase inversion. This is particularly effective when the S/N of the reproduced signal is degraded. The effects of the present invention are as described above, but furthermore, since the 45° phase shift circuit 9 and the 90° phase shift circuit 10 are not required to generate the reference signal as in the conventional case, the circuit can be simplified. can.

[Brief explanation of the drawing]

Figure 1 is a diagram of the recording pattern on a tape when a PAL signal is recorded on a rotating two-head VTR.
Figure 2 is a circuit diagram of a conventionally known line-sequential correction circuit for the reproduced chroma signal of a PAL VTR;
3B is a vector diagram showing the alternating phase of the color burst signal of the PAL signal, FIG. 3B is a vector diagram showing the recording color burst signal and pilot burst signal, and FIG. 4 is a waveform diagram showing the operation of FIG. 2. Fig. 5 is a circuit diagram of a line-sequential correction circuit for reproduced chroma signals according to the present invention, Fig. 6A is a vector diagram showing the phase of a reference signal for color burst phase detection, and Fig. 6B shows the phase of a replacement burst signal. 7 is a time chart showing the operation of FIG. 5, FIG. 8A is a vector diagram explaining the conventional chroma inversion discrimination ability of FIG. 2, and FIG. 8B is a discrimination diagram of the chroma inversion discrimination method according to the present invention. It is a vector diagram showing abilities. The symbols used in the drawings are 1...Magnetic tape, 2...1H delay line, 3...Switch switch,
7... Multiplier, 19... Phase reversal detection circuit, 23
. . . Inverter, 24 . . . Changeover switch.

Claims (1)

[Claims] 1. A first switch that switches between a reproduced chroma signal obtained by variable-speed reproduction with a PAL signal video signal regenerator and a signal delayed by one horizontal scanning interval, and a subcarrier frequency reference located on the reference axis of the color vector. a second switch for switching between the signal and a signal obtained by shifting the phase of the same by a predetermined amount; and a second switch that changes the phase of the reproduced color burst signal whose phase is inverted for each horizontal scanning section with respect to the reference axis and the output of the second switch. and a phase detector for comparison, and is configured so that the first switch is switched by the output of the phase detector, and the reference axis is the V axis of the color vector, and the predetermined amount is
A reproduction chroma signal processing circuit characterized in that the angle is selected to be 180°.