JPH0243204B2 - - Google Patents

Description

[Detailed description of the invention]

(Technical Field) The present invention relates to a DC voltage control circuit used in a C-MOS IC or the like. (Prior Art) When it is necessary to operate an external circuit with a high voltage power supply, it is convenient that the CMOS-IC circuit can also be operated with the same power supply voltage and has a common current. Therefore, conventionally, C-MOS ICs have V _DD (high power supply potential input terminal) and V _SS (low power supply potential input terminal) with 3V,
By applying voltage such as 5V, 12V, 16V, etc.
I got the IC working. However, depending on the value of the power supply voltage of the IC used,
There was a large difference in the pattern area of IC chips with the same function. That is, in order to increase the withstand voltage of a MOS transistor, the distance between the source and drain must be increased. Therefore, the area occupied by the IC chip increases. for example,
If the C-MOS pattern area for a 3V withstand voltage is "1", it will be approximately "1.6" for a 5V withstand voltage, approximately "3.1" for a 12V withstand voltage, and approximately "5 to 6.4" for a 16V withstand voltage. For this reason, 12V or 16V withstand voltage ICs have 500 to 1000
MSI of 3000 elements or more is the limit.
In LSI, the chip area becomes too large, so
This resulted in a decrease in the quality of products and an increase in costs, making it virtually impossible to manufacture. Therefore, the withstand voltage of the IC internal circuit is reduced to a low voltage (for example,
5V withstand voltage), the interface with the external circuit of the IC is high withstand voltage (for example, 16V withstand voltage), and the external
There is a way to create different power supplies (5V and 16V) and input them to the IC, but this requires creating two dedicated stabilized power supplies outside the IC, which increases costs. Furthermore, even if the IC uses V _DD in both the low-voltage and high-voltage sections, two low-voltage input terminals are required: V _SS for the high voltage and V _SS ' for the low voltage. Three pins are required, which adds one pin compared to a normal IC. (Object of the Invention) This invention was made to eliminate the above-mentioned drawbacks of the conventional technology.
In addition to making it possible to realize
The purpose of this invention is to provide a DC voltage control circuit that can reduce the cost of ICs. (Structure of the Invention) A DC voltage control circuit of the present invention is connected between a high power supply potential input terminal, a first connection point, and the high power supply potential input terminal and the first connection point, and includes at least one
a load circuit consisting of a diode using two P-channel MOS FETs, a second connection point, an output terminal, an N-channel whose gate and drain are connected to the first connection point, and whose source is connected to the second connection point.
a first diode consisting of a MOS FET;
A first comprising an N-channel MOS FET having a gate connected to the first connection point, a drain connected to the high power supply potential input terminal, and a source connected to the output terminal.
a source follower circuit, a third connection point, a low power supply potential input terminal, a gate and a drain connected to the third connection point;
a second diode consisting of a P-channel MOS FET whose source is connected to the second connection point; a gate is connected to the third connection point; a drain is connected to the low power supply potential input terminal; and a source is connected to the output terminal. a second source follower circuit composed of a P-channel MOS FET connected to the terminal; a first resistance means connected between the third connection point and the low power supply potential input terminal; and a second resistance means connected between the terminal and the low power supply potential input terminal. (Example) Hereinafter, an example of the DC voltage control circuit of the present invention will be described based on the drawings. FIG. 1 is a circuit diagram of one embodiment. In FIG. 1, a high power supply potential input terminal (hereinafter abbreviated as V _DD ) 1 is connected to a P channel MOS FET (hereinafter referred to as P
-MOS) 3, one end of a resistor 4, and the drain of an N-channel MOS FET (hereinafter abbreviated as N-MOS) 8. The gate and drain of the P-MOS 3 are connected to the other end of the resistor 4, the gate of the N-MOS 8, and further to the gate and drain of the N-MOS 5 as a first diode. The connection portion between the gate and drain and the other end of the resistor 4 is a first connection point. The low power supply potential input terminal (hereinafter abbreviated as V _SS ) 2 is
The gate and drain of P-MOS 6 as a second diode through a resistor 7 as a first resistance means,
Further, it is connected to the gate of the P-MOS 9 and also directly connected to the drain of the P-MOS 9. The sources of N-MOS5 and P-MOS6 are connected. This N-MOS5 and P-MOS6
The connection of the source is the second connection point. Also, P
The connection point between the gate and drain of the -MOS6, one end of the resistor 7, and the gate of the P-MOS9 is the third connection point. The sources of N-MOS 8 and P-MOS 9 are connected to V _SS 2 through a potential output terminal (hereinafter abbreviated as V _SS ') 11 and a resistor 10 (resistance means) serving as a supply circuit. Next, the operation of the DC voltage control circuit of the present invention configured as described above will be explained, but before that, the diode characteristics will be described in advance. Diode characteristic V _fN (described for N MOS FET) is the voltage value when current begins to flow through the diode. Here, the diode characteristic V _fN and the threshold value V _TN have the following relationship. The relationship between the gate voltage V _G and drain current _ID of the N-MOS FET is shown in FIG. threshold voltage
As can be seen from the figure, V _TN is generally defined as the gate voltage value at which the transistor turns on when the drain current is 0 (or at an extremely small current value such as 1 μA). On the other hand, the diode characteristic formed by N-MOS FETs is also ideally V _TN , but since the diode does not operate unless a certain current (i) is passed through it, the diode characteristic V _fN is larger than V _TN . The same is true for P-MOS FETs, except that (+) on the horizontal axis in Figure 4 is changed to (-). Now, the operation will be explained. V _DD 1, V _SS 2
When a voltage equal to or less than V _TP (threshold voltage of P-channel MOS FET) or V _TN (threshold voltage of N-channel MOS FET) (V _TP ≒ V _TN ) is applied between P-MOS3, 6, 9, and N −MOS
5 and 8 do not operate, but the level of V _SS is generated at V _SS '11 through the resistor 10 (point A of characteristic I in FIG. 2). When the potential between V _DD 1 and V _SS 2 exceeds V _TP +V _TN , current begins to flow through the resistor 4, N-MOS 5, P-MOS 6, and resistor 7. N-MOS5 and P-MOS6 have their gates and drains connected and operate as diodes.
-MOS5 becomes N-MOS8, P-MOS6 becomes P-
A bias is added to each MOS9,
The same potential as the source potential of N-MOS5 and P-MOS6 is the source potential of N-MOS8 and P-MOS9 (i.e.
V _SS '11) (point B of characteristic I in Fig. 2). Here, the point that the same potential as the source potential of N-MOS5 and P-MOS6 is generated at the sources of N-MOS8 and P-MOS9 will be explained in detail. The N-MOS 5, 8 and the P-MOS 6, 9 have a configuration in which source follower circuits are connected as shown in FIGS. 5a and 5b (A and G, B and H are connected, respectively). Now, considering the source follower circuit in Figure 5a, the potential V _B at point B has dropped by the threshold voltage V _TN of the N-MOS8 from the potential V _C at point C, regardless of the potential V _D at point D. It is the electric potential (because it is a source follower circuit). That is, V _B =V _C -V _TN . On the other hand, the potential V _A at point A is a potential dropped from V _C by the diode characteristic V _fN of the diode composed of N-MOS5. That is, V _A =V _C −V _fN . Now, the relationship between the diode characteristic V _fN and the threshold voltage of the transistor is V _fN > V _TN , but this difference is minute and can be almost ignored when considering the potentials at points A to C. That is, V _fN ≒ V _TN
If you think about it, you can do it, so V _B = V _C − V _TN ≒ V _C − V _TN = V _A. In the source follower circuit of FIG. 5b, as described above, the potential V _H at point H is different from the potential V _E at point E and P
- It is determined by the threshold value V _TP of MOS6, and V _H =V _E +V _TP . The potential V _G at point G is expressed from the diode characteristics V _fP and V _E of the diode composed of the P-MOS 9, and becomes V _G =V _E +V _fP . Then, as above, V _fp > V _TP , but V _fP
Since ≒V _TP , V _H =V _E +V _TP ≒V _E +V _fP =V _G. The potential at point A or point G is N-MOS5 and P-
This is the source potential of the MOS 6, and the potential at point B or H is the source potential of the N-MOS 8 and P-MOS 9. Therefore, it can be seen that the source potentials are the same potential. At this time, current will flow through the resistor 10, but the resistance value of the resistor 10 may be arbitrarily changed depending on the current consumption of the system. As the potential between V _DD 1 and V _SS 2 increases further, the potential difference across resistor 4 increases to V _TP of P-MOS 3.
As a result, current also flows through the P-MOS 3 (the gate and drain of the P-MOS 3 are connected, and it operates as a diode). Therefore, the source potential of N-MOS5 (V _SS '1
1) becomes a limiter type, and even if the potential difference between V _DD 1 and V _SS 2 is increased further,
The potential difference between V _SS '11 and V _DD becomes saturated (point C of characteristic I in FIG. 2). As described above, the voltage of V _SS '11 with respect to the voltage between V _DD 1 and V _SS 2 is as shown in characteristic I in FIG. The potential difference applied to the limiter by the P-MOS3 at point C of characteristic I in Fig. 2 (approaching constant voltage characteristics) is the diode characteristic _VfP of the P-MOS3 and N-
It is the sum of the diode characteristic V _fN of MOS5 (V _fP
+ _VfN ). This diode characteristic is P-MOS3 and N-MOS3.
Although it varies depending on the resistance value of resistor 7 relative to the on-resistance of MOS 5, it is always V _fP > V _TP , V _fN > V _TN
becomes. In C-MOS, the potential of V _TN +V _TP is V _DD 1 and V _SS ′
11, it will work, so V _DD 1-
It will operate reliably if there is a voltage between V _SS '11 (V _fP + V _fN ). In terms of temperature characteristics, there is no problem since the limiter is formed by P-MOS3 and N-MOS5, so that it matches the temperature characteristic fluctuation between _VDD and _VSS '. Therefore, if the DC voltage control circuit and internal input/output circuit according to the present invention use a manufacturing process for high-voltage C-MOS transistors, and the internal logic circuit uses a manufacturing process for low-voltage C-MOS transistors, , the reduction in IC chip surface shrinkage can be measured. Note that in the circuit shown in FIG. 1 above, the resistor 4 may be omitted, but if it is present, the potential between V _DD 1 and V _SS 2 is equal to or higher than (V _TN + V _TP ), and the N-MOS 5 and P-MOS
6 has the advantage that the bias current flows through it. Without resistor 4, the potential between V _DD 1 and V _SS 2 would be (V _TN +
Since the bias current flows above 2V _TP ), the operating voltage of the bias circuit increases. In order to increase the potential difference between V _DD 1-V _SS '11 and increase the C-MOS operation margin in a low-voltage process, connect two or more diodes in multiple stages instead of one using P-MOS3 as shown in Figure 1. Or, consider the temperature characteristic margin and use a P-MOS3 diode.
During V _DD 1, it is sufficient to further increase the number of pairs of diodes made of P-MOS and diodes made of N-MOS. This example is shown in FIG. 3 as a second embodiment. In this second embodiment, the current flowing through the resistor 10 in FIG. 1 is also improved by widening the constant current region. High power supply potential input terminal (hereinafter abbreviated as V _DD ) 1 is P
It is connected to the source of -MOS12, the drain of N-MOS8, and one end of resistor 15. P-MOS
The gate and drain of No. 12 are connected to the source of P-MOS 3, and the gate and drain of P-MOS 3 are connected to the gate of N-MOS 8 and the gate and drain of N-MOS 5. The source of N-MOS5 is connected to the source of P-MOS6, and the gate and drain of P-MOS6 are connected to one end of resistor 7, the gate of P-MOS9, and N-MOS1.
A low power supply potential input terminal (hereinafter abbreviated as V _SS ) 2 is connected to the other end of the resistor 7 , the drain of the P-MOS 9 , and the sources of the N-MOS 13 and 14 . The sources of the N-MOS 8 and P-MOS 9 are connected to a potential output terminal (hereinafter abbreviated as V _SS ') 11 and to the drain of the N-MOS 14 through a resistor 10. Furthermore, the drain of N-MOS13 is resistor 15
The other end is connected to the gate of N-MOS14. FIG. 6 shows that in this second embodiment, V _DD
1. The potential applied to V _SS 2 and this causes V _SS ′
11 is a diagram showing potentials output to the circuit 11. As can be seen from this figure, V _DD is a single point potential, and V _SS takes a value that decreases from V _DD over time. The potential output from V _SS '11 changes depending on the potential applied to V _SS 2, and this is shown in the table below.

[Table] Next, the operation of the second embodiment shown in FIG. 3 will be explained with reference to FIG. 6 and the above table. V _DD 1 and
In a section where a potential lower than V _TN (threshold voltage of the N-channel MOS FET) is input between V _SS 2, V _SS '11 is in a high impedance (floating state). (Area) When a potential higher than V _TN is input between V _DD 1 and V _SS 2, no current flows through the diodes of P-MOS 12, 3, and 6 and the diode of N-MOS 5, so the voltage of N-MOS 13 The gate becomes "L" level, and the source-drain region is turned off. Therefore, the gate of N-MOS14 has a resistor 1.
Since the "H" level is transmitted through 5, the source-drain is turned on, and V _SS '11 is connected to the resistor 10.
Ground potential (V _SS ) is output through. (Area) When a potential of 3V _rP +V _fN is input between V _DD 1 and V _SS 2, the diode by P-MOS12, 3, and 6
Current begins to flow through the diode by N-MOS5. The diode by N-MOS5 is N-
In MOS8, the diode by P-MOS6 is P-
A bias is added to each MOS9,
Figure 3: Point J (diode with N-MOS5 and P
-The same potential as the midpoint of the diode by MOS6)
V _SS '11. However, since the N-MOS 13 turns off when the voltage drop occurring across the resistor 7 is less than V _TN ,
The N-MOS 14 turns on, and the output of V _SS '11 is obtained by dropping the voltage from the potential at point J (V _DD - (2V _fP + V _fN ) by the resistor 10. (Area) V _DD 1 and V When a potential of 3V _fP + 2V _fN is input between _SS 2, N-MOS13 turns on and N-MOS14
Since the gate of N-MOS becomes “L” level,
14 is turned off between the source and drain. Therefore, a potential at point J in FIG. 3 (voltage lower than V _DD by 2V _fP +V _fN ) is generated at V _SS '11. (Area) Even if the potential difference between V _DD 1 and V _SS 2 increases further, a limiter is applied by the diodes formed by P-MOS12, 3 and N-MOS 5, and V _SS '11 increases.
The potential difference with respect to V _DD becomes saturated. The potential difference applied to this limiter is the aforementioned 2V _fP +V _fN , and compared with the C-MOS operation guaranteed power supply voltage V _TP + V _TN , it is more than V _fP (V _fP > V _TP , V _fN
>V _TN ). Furthermore, unlike the first embodiment, there is no current flowing through the resistor 10, resulting in low power consumption. Therefore, since the resistance value of the resistor 10 can be made small, when the potential between V _DD 1 and V _SS 2 is low,
V _SS ' is almost V _SS , and the power supply voltage range can be wider than in the first embodiment. As described above, in the second embodiment, (1) the constant voltage region is wide; (2) The impedance between V _DD and V _SS varies depending on the voltages of V _DD and V _SS , and the current value flowing through this impedance means is kept low, making it possible to reduce power consumption. It has the following advantages. In addition, in the second embodiment shown in FIG.
A load circuit is configured by MOS12 and P-MOS3. Also, resistor 10, N-MOS13, N
-The MOS 14 and the resistor 15 constitute a second resistance means. (Effects of the Invention) As described above, according to the DC voltage control circuit of the present invention, the inside of the IC is a logic circuit that operates at a normal low voltage, and the input/output section operates at the same power supply voltage as the external circuit. It can be configured to have an input/output circuit. In addition, this circuit can be configured with a resistor and a transistor, so it is easy to integrate into an IC, and the 12V
It is possible to significantly reduce the chip area by applying it to highly integrated ICs with a 16V breakdown voltage. Accordingly, costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the DC voltage control circuit of the present invention, FIG. 2 is an input/output voltage characteristic diagram of the first embodiment, and FIG. 3 is a circuit diagram of a DC voltage control circuit of the present invention. 4 is a characteristic diagram for explaining the relationship between diode characteristics and threshold value, and FIG. 5 is a circuit diagram of the second embodiment, a part of the circuit of the first embodiment is extracted to explain the operation FIG. 6 is an input/output voltage characteristic diagram of the second embodiment. 1...High power supply potential input terminal, 2...Low power supply potential input terminal, 3, 6, 9, 12...P channel
MOS FET, 5, 8, 13, 14...N channel MOS FET, 4, 7, 10, 15...Resistance,
11... Potential output terminal.

Claims (1)

[Claims] 1. A high power supply potential input terminal, a first connection point, and at least one P-channel MOS connected between the high power supply potential input terminal and the first connection point.
A load circuit consisting of a diode using an FET, a second connection point, an output terminal, and an N channel whose gate and drain are connected to the first connection point and whose source is connected to the second connection point.
a first diode consisting of a MOS FET;
A first comprising an N-channel MOS FET having a gate connected to the first connection point, a drain connected to the high power supply potential input terminal, and a source connected to the output terminal.
a source follower circuit, a third connection point, a low power supply potential input terminal, and a P channel whose gate and drain are connected to the third connection point and whose source is connected to the second connection point.
a second diode consisting of a MOS FET;
a second source follower circuit composed of a P-channel MOS FET having a gate connected to the third connection point, a drain connected to the low power supply potential input terminal, and a source connected to the output terminal; and a second resistance means connected between the output terminal and the low power supply potential input terminal. . 2. The load circuit includes: a diode consisting of a P-channel MOS FET whose source is connected to the high power supply potential input terminal and whose drain and gate are connected to the first connection point; and between the high power supply potential input terminal and the first connection point. 2. The DC voltage control circuit according to claim 1, comprising a resistor connected between the DC voltage control circuit and the resistor. 3. The load circuit includes a first diode including a first P-channel MOS FET whose source is connected to the high power supply potential input terminal and whose drain and gate are commonly connected; and a first diode whose source is the first P-channel MOS FET.
and a second diode comprising a second P-channel MOS FET whose drain and gate are connected to the first connection point. DC voltage control circuit. 4. The second resistance means includes a first N-channel MOS FET whose gate is connected to the third connection point and whose source is connected to the low power supply potential input terminal, and between the high power supply potential input terminal and the first a resistor connected between the drain of the N-channel MOS FET, and a gate of the first N-channel MOS FET;
a second N-channel MOS FET whose drain is connected to the low power supply potential input terminal; and a resistor connected between the drain of the second N-channel MOS FET and the output terminal. A DC voltage control circuit according to claim 1.