JPH0243270B2 - - Google Patents
Info
- Publication number
- JPH0243270B2 JPH0243270B2 JP57058096A JP5809682A JPH0243270B2 JP H0243270 B2 JPH0243270 B2 JP H0243270B2 JP 57058096 A JP57058096 A JP 57058096A JP 5809682 A JP5809682 A JP 5809682A JP H0243270 B2 JPH0243270 B2 JP H0243270B2
- Authority
- JP
- Japan
- Prior art keywords
- speed
- signal
- cylinder
- acceleration
- speed command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001133 acceleration Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
- G11B5/58—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
- G11B5/596—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
Landscapes
- Control Of Position Or Direction (AREA)
- Control Of Velocity Or Acceleration (AREA)
- Control Of Electric Motors In General (AREA)
- Moving Of Head For Track Selection And Changing (AREA)
Description
【発明の詳細な説明】
発明の対象
本発明は磁気デイスク装置に係り、特にアクセ
ス可動部の速度制御回路に関する。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a magnetic disk drive, and more particularly to a speed control circuit for a movable access section.
従来技術
従来の磁気デイスク位置決め系における速度制
御は、制御しようとするアクセス可動部速度を目
標点までの残りシリンダ毎に前もつて階段状に決
めておき、これに現実のキヤリツジ速度信号ある
いは定数値等から作つたシリンダ毎にノコギリ状
に変化するスムーズ信号を合成して速度命令信号
とした。しかしこの従来のスムーズ信号は、速度
制御後の現実キヤリツジ速度あるいは定数値から
発生させているため階段状速度信号を連続的にで
きない欠点があつた。Prior Art In speed control in a conventional magnetic disk positioning system, the speed of the access movable part to be controlled is determined stepwise in advance for each remaining cylinder up to the target point, and then an actual carriage speed signal or constant value is applied to the speed. A speed command signal was created by synthesizing smooth signals that varied in a sawtooth pattern for each cylinder. However, since this conventional smooth signal is generated from the actual carriage speed after speed control or from a constant value, it has the disadvantage that it is not possible to produce a step-like speed signal continuously.
発明の目的
本発明の目的は、残りのシリンダに応じて前も
つて記録あるいは決めてある階段状速度命令信号
および予定加速度から、連続的に変化する円滑な
速度命令信号を提供することにある。OBJECTS OF THE INVENTION It is an object of the present invention to provide a smooth speed command signal that varies continuously from a step speed command signal and a predetermined acceleration that are previously recorded or determined depending on the remaining cylinders.
発明の総括的説明
アクセス可動部の速度制御における速度命令は
アクセス系の能力加速度にもとづいて階段状に決
めてある。従つてこの階段状速度命令を連続にす
るには、上記アクセス系の能力加速度の積分補正
で可能であるということに注目し、能力加速度を
記録できるメモリーあるいはハードウエア回路を
速度制御部に搭載した。General Description of the Invention Speed commands for controlling the speed of the access movable part are determined in a stepwise manner based on the acceleration capacity of the access system. Therefore, in order to make this stepped speed command continuous, we focused on the fact that it is possible to make an integral correction of the capacity acceleration of the access system, and installed a memory or hardware circuit in the speed control unit that can record the capacity acceleration. .
発明の実施例
本発明の実施される磁気デイスク装置アクセス
速度制御部概要を第１図により説明する。Embodiments of the Invention An overview of a magnetic disk device access speed control section in which the present invention is implemented will be explained with reference to FIG.
磁気デイスク装置の読み書き用ヘツド及びサー
ボヘツド（以降アクセス可動部と呼ぶ）を現在位
置決めしているシリンダから次の目標シリンダに
移動（以降シークと呼ぶ）させる時の速度制御に
ついて動作説明する。 The operation of speed control when moving the read/write head and servo head (hereinafter referred to as the access movable part) of the magnetic disk device from the currently positioned cylinder to the next target cylinder (hereinafter referred to as seek) will be explained.
残りシリンダカウンタ１は、目標シリンダと現
在シリンダの差つまり移動シリンダ量１２をカウ
ンタに記録し、アクセス可動部の運動開始後に発
生するシリンダパルス（ヘツドがシリンダを越す
毎に発生されるパルス）１９によつてその内容を
１つずつ減じ残りシリンダ量１３として出力す
る。速度変換器２は、残りシリンダ量１３を受け
て階段状速度命令信号１６を位置の関数として発
生させる。一方加速度変換器３は、残りシリンダ
量１３を受けて速度制御を行つている時の予定加
速度信号１４を位置の関数として発生する。スム
ーザ回路４は、この予定加速度信号を受けシリン
ダパルス１９毎に積分を繰返し、シリンダパルス
間の速度変化つまりスムーザ信号１５を発生す
る。階段状速度命令信号１６は、速度命令合成器
１７によりスムーザ信号１５と合成され速度命令
アンプ５によつて増巾された後、アクセス可動部
を制御する速度命令信号１８となる。 The remaining cylinder counter 1 records the difference between the target cylinder and the current cylinder, that is, the moving cylinder amount 12, and records the cylinder pulse 19 generated after the access movable part starts moving (the pulse generated every time the head passes a cylinder). Therefore, the content is subtracted by one and output as the remaining cylinder amount 13. The speed converter 2 receives the remaining cylinder quantity 13 and generates a stepped speed command signal 16 as a function of position. On the other hand, the acceleration converter 3 receives the remaining cylinder amount 13 and generates a planned acceleration signal 14 as a function of position when performing speed control. The smoother circuit 4 receives this planned acceleration signal and repeats integration for each cylinder pulse 19 to generate a speed change between cylinder pulses, that is, a smoother signal 15. The stepped speed command signal 16 is combined with the smoother signal 15 by a speed command synthesizer 17 and amplified by a speed command amplifier 5, and then becomes a speed command signal 18 for controlling the access movable part.
この速度命令信号１８は、エラーアンプ６、パ
ワーアンプ７、アクセス可動部の駆動要素である
VCM（ボイスコイルモータ）８、速度検出器９及
び速度フイードバツク回路１０からなる速度制御
ループに供給され可動部速度２０を決める。 This speed command signal 18 is a driving element for the error amplifier 6, the power amplifier 7, and the access movable part.
The signal is supplied to a speed control loop consisting of a VCM (voice coil motor) 8, a speed detector 9, and a speed feedback circuit 10 to determine the moving part speed 20.
以下、本発明の一実施例を第２図により説明す
る。なおその動作波形を第３図に示す。 An embodiment of the present invention will be described below with reference to FIG. The operating waveforms are shown in FIG.
本回路の主要部は1024ビツトのリードオンリー
メモリー５０、４チヤンネルのアナログスイツチ
５１、メモリーバツフア用の演算増巾器５２、積
分回路を構成するアナログスイツチ５３、演算増
巾器５４及び速度命令アンプ用演算増巾器５５か
ら成立つ。 The main parts of this circuit are a 1024-bit read-only memory 50, a 4-channel analog switch 51, an arithmetic amplifier 52 for memory buffer, an analog switch 53 forming an integral circuit, an arithmetic amplifier 54, and a speed command amplifier. It is established from the operational amplifier 55.
残りシリンダ量１３は、1024ビツトのリードオ
ンリーメモリー５０のアドレス選択を行う。その
アドレスの内容は20〜23の出力を通してアナログ
スイツチ５１を開閉する。アナログスイツチ５１
は、20に対してｉアンペア、21に対して2iアンペ
ア、22に対して4iアンペア、23に対して8iアンペ
アの電流を出力する。メモリーバツフア用演算増
巾器５２は、この電流を電圧に変換する。以上の
動作により残りシリンダ量１３に対応した予定加
速度信号１４が得られる。 The remaining cylinder amount 13 selects the address of the 1024-bit read-only memory 50. The contents of that address open and close analog switch 51 through outputs 20 to 23 . analog switch 51
outputs i amps for 2 0 , 2i amps for 2 1 , 4i amps for 2 2 , and 8i amps for 2 3 . The memory buffer operational amplifier 52 converts this current into voltage. By the above-described operation, a planned acceleration signal 14 corresponding to the remaining cylinder amount 13 is obtained.
予定加速度信号１４は、演算増巾器５４、積分
用キヤパシタ５４から成る積分器及びアナログス
イツチ５３によつてシリンダパルス１９毎にイニ
シヤライズする放電回路を通してシリンダパルス
間の速度変化量つまりスムーザ信号１５に変換さ
れる。 The planned acceleration signal 14 is converted into a speed change amount between cylinder pulses, that is, a smoother signal 15, through a discharging circuit that is initialized every cylinder pulse 19 by an integrator consisting of an arithmetic amplifier 54 and an integrating capacitor 54, and an analog switch 53. be done.
ここでスムーザ信号１５は、階段状速度信号１
６と演算増巾器５５によつて合成された速度命令
信号１８になる。 Here, the smoother signal 15 is the stepped speed signal 1
6 and arithmetic amplifier 55 to obtain a speed command signal 18.
本実施例によれば、残りシリンダ位置に対応し
た既知加速度を積分して得られた速度変化量を、
これまた同上既知加速度でもつて減速変化してい
る階段状速度信号と合成することにより連続した
円滑な速度信号が得られる。この結果VCM駆動
電流は滑らかとなり、アクセス可動部に誘起され
る異常振動を低下させるのに効果がある。 According to this embodiment, the amount of speed change obtained by integrating the known acceleration corresponding to the remaining cylinder position is
A continuous and smooth speed signal can be obtained by combining the same known acceleration with the step-like speed signal which is decelerating and changing. As a result, the VCM drive current becomes smooth, which is effective in reducing abnormal vibrations induced in the access movable part.
発明の効果
本発明によれば、速度命令が連続・円滑になる
のでパワーアンプ電流に含まれる高周波成分を低
下させることが出来、その結果アクセス可動部の
異常振動を低下し得た。Effects of the Invention According to the present invention, since the speed command becomes continuous and smooth, it is possible to reduce the high frequency component contained in the power amplifier current, and as a result, it is possible to reduce abnormal vibration of the access movable part.
第１図は、速度制御系全体ブロツク図、第２図
は、加速度変換器とスムーザ回路部分図、第３図
は、スムーザ回路動作図である。
１……残りシリンダカウンタ、２……速度変換
器、３……加速度変換器、４……スムーザ回路、
５……速度命令アンプ、６……エラーアンプ、７
……パワーアンプ、８……VCM（ボイスコイルモ
ータ）、９……速度検出器、１０……速度フイー
ドバツク回路、１１……速度フイードバツク信
号、１２……移動シリンダ量（デイジタル量）、
１３……残りシリンダ量（デジタル量）、１４…
…予定加速度信号、１５……スムーザ信号、１６
……階段状速度命令信号、１７……速度命令合成
器、１８……速度命令信号、１９……シリンダパ
ルス、２０……可動部速度、５０……リードオン
リーメモリ、５１……アナログスイツチ、５２…
…演算増巾器、５３……アナログスイツチ、５４
……演算増巾器、５５……演算増巾器、５６……
積分用キヤパシタ。
FIG. 1 is an overall block diagram of the speed control system, FIG. 2 is a partial diagram of an acceleration converter and smoother circuit, and FIG. 3 is an operational diagram of the smoother circuit. 1... Remaining cylinder counter, 2... Speed converter, 3... Acceleration converter, 4... Smoother circuit,
5...Speed command amplifier, 6...Error amplifier, 7
... Power amplifier, 8 ... VCM (voice coil motor), 9 ... Speed detector, 10 ... Speed feedback circuit, 11 ... Speed feedback signal, 12 ... Moving cylinder amount (digital amount),
13... Remaining cylinder amount (digital amount), 14...
...Planned acceleration signal, 15...Smoother signal, 16
... Stepped speed command signal, 17 ... Speed command synthesizer, 18 ... Speed command signal, 19 ... Cylinder pulse, 20 ... Moving part speed, 50 ... Read only memory, 51 ... Analog switch, 52 …
... Arithmetic amplifier, 53 ... Analog switch, 54
... Arithmetic amplifier, 55... Arithmetic amplifier, 56...
Integral capacitor.
Claims (1)
ヘツド及びサーボヘツドを目標シリンダにアクセ
スしリード・ライトを行なわせる磁気デイスク装
置において、速度制御過程の加速度を前もつて記
録したメモリーないしハードウエアー回路を含む
速度命令スムーザ回路を設けたことを特徴とする
磁気デイスク装置。1. A magnetic disk device that allows a read/write head and a servo head to access a target cylinder and perform read/write operations through speed control and position control, including a memory or hardware circuit that records the acceleration of the speed control process in advance. A magnetic disk device characterized by being provided with a speed command smoother circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57058096A JPS58177571A (en) | 1982-04-09 | 1982-04-09 | magnetic disk device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57058096A JPS58177571A (en) | 1982-04-09 | 1982-04-09 | magnetic disk device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58177571A JPS58177571A (en) | 1983-10-18 |
| JPH0243270B2 true JPH0243270B2 (en) | 1990-09-27 |
Family
ID=13074417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57058096A Granted JPS58177571A (en) | 1982-04-09 | 1982-04-09 | magnetic disk device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58177571A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2573904B1 (en) * | 1984-11-29 | 1987-01-02 | Bull Sa | METHOD FOR MOVING A MOBILE SYSTEM MOVED BY AN ELECTRIC MOTOR FOLLOWING A GIVEN PATH |
-
1982
- 1982-04-09 JP JP57058096A patent/JPS58177571A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58177571A (en) | 1983-10-18 |
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