JPH0244164B2 - - Google Patents
Info
- Publication number
- JPH0244164B2 JPH0244164B2 JP58054477A JP5447783A JPH0244164B2 JP H0244164 B2 JPH0244164 B2 JP H0244164B2 JP 58054477 A JP58054477 A JP 58054477A JP 5447783 A JP5447783 A JP 5447783A JP H0244164 B2 JPH0244164 B2 JP H0244164B2
- Authority
- JP
- Japan
- Prior art keywords
- differential
- differential amplifier
- transistors
- differential pair
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】 本発明は差動増幅器に関するものである。[Detailed description of the invention] The present invention relates to a differential amplifier.
第１図は従来の一般的な例を示す。アナログ信
号は入力端子４−１，５−１から差動増幅回路１
６−１に入力される。差動増幅回路１６−１はエ
ミツタ共通の差動ペアトランジスタ９−１，１０
−１を有し、入力端子４−１，５−１はそれらの
ベースにそれぞれ接続されている。前記差動ペア
トランジスタ９−１，１０−１の共通エミツタは
電流スイツチ用トランジスタ１１−１のコレクタ
に接続されている。以上の様な差動増幅回路がｎ
個（ｎ≦２）（１６−１から１６−ｎ）存在し、
それぞれの差動ペアトランジスタ９−１，１０−
１〜９−ｎ，１０−ｎのコレクタは各々出力端子
２，３に共通に接続されると共に、一端が電源端
子１に接続されている負荷抵抗７，８の他端にも
各々接続され、又電流スイツチ用トランジスタ１
１−１〜１１−ｎのエミツタは共通に接続され、
さらに駆動用電流源１２に接続されている。電流
スイツチ用トランジスタ１１−１〜１１−ｎのベ
ースはマルチプレクサの出力など選択信号が印加
され、差動ペアトランジスタ９−１，１０−１〜
９−ｎ，１０−ｎの活性、不活性を決定する。通
常はｎ組のアナログ入力端子から一組だけを選択
し、増幅する多チヤンネル入力一出力の選択増幅
器として使われる。 FIG. 1 shows a conventional general example. Analog signals are sent from input terminals 4-1 and 5-1 to differential amplifier circuit 1.
6-1. The differential amplifier circuit 16-1 includes a differential pair of transistors 9-1 and 10 with common emitters.
-1, and input terminals 4-1 and 5-1 are connected to their bases, respectively. The common emitters of the differential pair transistors 9-1 and 10-1 are connected to the collector of a current switch transistor 11-1. The differential amplifier circuit as described above is n
There are (n≦2) (16-1 to 16-n),
Each differential pair transistor 9-1, 10-
The collectors of 1 to 9-n and 10-n are commonly connected to output terminals 2 and 3, respectively, and also connected to the other ends of load resistors 7 and 8, each of which has one end connected to power supply terminal 1, Also, current switch transistor 1
The emitters of 1-1 to 11-n are connected in common,
Furthermore, it is connected to a driving current source 12. A selection signal such as the output of a multiplexer is applied to the bases of the current switch transistors 11-1 to 11-n, and differential pair transistors 9-1, 10-1 to
Determine the activity and inactivity of 9-n and 10-n. Usually, it is used as a multi-channel input/one output selective amplifier that selects and amplifies only one set from n sets of analog input terminals.
従来の一般的な例においては、ｎ個の差動増幅
回路のうち選択されずに不活性状態である差動増
幅回路の差動ペアトランジスタのベースに信号が
印加された場合、信号を受けた差動ペアトランジ
スタのコレクタ・ベース容量CJCによつて入力端
子・出力端子間が直結カツプリングされ、選択さ
れなかつたトランジスタへの入力信号が出力端子
に現われていた。すなわち、選択されていない入
力端子から出力端子までの利得と、選択された入
力端子から出力端子までの利得との比であるチヤ
ンネル分離度が悪いという欠点があつた。 In a typical conventional example, when a signal is applied to the base of a differential pair transistor of a differential amplifier circuit that is not selected among n differential amplifier circuits and is in an inactive state, the signal is received. The input terminal and output terminal were directly coupled by the collector-base capacitance C JC of the differential pair transistors, and the input signal to the unselected transistor appeared at the output terminal. That is, the channel separation ratio, which is the ratio of the gain from an unselected input terminal to an output terminal to the gain from a selected input terminal to an output terminal, is poor.
本発明の目的は、上記チヤンネル分離度を向上
させた差動増幅回路を提供することにある。 An object of the present invention is to provide a differential amplifier circuit with improved channel separation.
本発明の差動増幅回路は、選択的に動作状態と
なる複数の差動回路における差動ペアトランジス
タのコレクタと共通負荷との間にダイオードをコ
レクタ電流の流れる向きに接続したことを特徴と
している。 The differential amplifier circuit of the present invention is characterized in that a diode is connected in the direction of collector current flow between the collectors of differential pair transistors and a common load in a plurality of differential circuits that are selectively activated. .
第２図に本発明の実施例を示す。第１図と対応
するものには同一番号を付してある。単位となる
差動増幅回路１６−１…１６−ｎの１つである差
動増幅回路１６−１はアナログ入力信号を受ける
入力端子４−１，５−１が、エミツタ共通の差動
ペアトランジスタ９−１，１０−１のベースにそ
れぞれ接続されている。差動ペアトランジスタ９
−１，１０−１の共通エミツタ接続点は電流スイ
ツチ用トランジスタ１１−１のコレクタに接続さ
れている。又差動ペアトランジスタ９−１，１０
−１のそれぞれのコレクタには、シヨツトキーダ
イオード１４−１，１５−１のカソード側がそれ
ぞれ接続されている。以上の様な差動増幅回路が
１６−１から１６−ｎまでのｎ個（ｎ≧２）存在
し、それぞれのシヨツトキーダイオード１４−
１，１５−１〜１４〜ｎ，１５−ｎのアノードは
各々出力端子２，３に共通に接続されると共に、
一端が電源端子１に接続されている負荷抵抗７，
８の他端にも各々接続されている。又電流スイツ
チ用トランジスタ１１−１〜１１−ｎのエミツタ
は共通に接続され、さらに駆動用電流源１２に接
続されている。 FIG. 2 shows an embodiment of the present invention. Components corresponding to those in FIG. 1 are given the same numbers. The differential amplifier circuit 16-1, which is one of the unit differential amplifier circuits 16-1...16-n, has input terminals 4-1, 5-1 that receive analog input signals, and is a differential pair transistor with a common emitter. They are connected to the bases of 9-1 and 10-1, respectively. Differential pair transistor 9
The common emitter connection point of -1 and 10-1 is connected to the collector of current switch transistor 11-1. Also, differential pair transistors 9-1, 10
The cathodes of Schottky diodes 14-1 and 15-1 are connected to the respective collectors of -1. There are n differential amplifier circuits as described above from 16-1 to 16-n (n≧2), and each shot key diode 14-
The anodes of 1, 15-1 to 14 to n, 15-n are commonly connected to the output terminals 2 and 3, respectively, and
a load resistor 7 whose one end is connected to the power supply terminal 1;
8 are also connected to the other ends. Further, the emitters of the current switch transistors 11-1 to 11-n are connected in common, and further connected to a driving current source 12.
本発明においては、差動ペアトランジスタのコ
レクタと出力端子２，３との間にダイオード１４
−１，１５−１…１４−ｎ，１５−ｎを挿入した
ことが従来と異なる。この為不活性状態の差動増
幅回路においては、従来は入力端子４−１，５−
１…４−ｎ，５−ｎと出力端子２，３が交流的に
は、差動ペアトランジスタのコレクタ・ベース間
容量CJCによつて直結カツプリングされていたが、
本発明ではトランジスタのコレクタ・ベース間容
量CJCとダイオードの接合容量CJのシリーズ
Ｃ＝CJC×CJ／CJC＋CJ
となりカツプリング容量は著しく減少し、選択さ
れてない入力端子から利得は大巾に小さくなる。
つまりチヤンネル分離度は向上し、一例では
25dB以上向上した。又ダイオード挿入による差
動利得への影響はまつたく無い。 In the present invention, a diode 14 is connected between the collector of the differential pair transistor and the output terminals 2 and 3.
-1, 15-1...14-n, 15-n are inserted, which is different from the conventional method. For this reason, in a differential amplifier circuit in an inactive state, input terminals 4-1, 5-
1...4-n, 5-n and output terminals 2 and 3 were directly coupled in AC terms by the collector-base capacitance CJC of the differential pair transistor,
In the present invention, the series of the collector-base capacitance C JC of the transistor and the junction capacitance C J of the diode is C = C JC × C J /C JC + C J , so the coupling capacitance is significantly reduced, and the gain is reduced from the unselected input terminal. It becomes extremely small.
In other words, channel separation is improved, and in one example
Improved by more than 25dB. Furthermore, the insertion of diodes has little effect on the differential gain.
以上の様に、本発明によりチヤンネル分離度は
著しく向上する。又、わずかダイオードを加える
だけであり、特にシヨツトキーダイオードにおい
てはNPNトランジスタと同一の領域に形成する
ことも可能であり、集積回路化した場合チツプ面
積の増大はほとんど無い。 As described above, according to the present invention, the degree of channel separation is significantly improved. In addition, only a small number of diodes are added, and in particular, a Schottky diode can be formed in the same region as an NPN transistor, and when integrated into an integrated circuit, there is almost no increase in chip area.
上記例においては、差動ペアトランジスタが
NPN型、負荷が抵抗の場合を示したが、PNPト
ランジスタの差動ペアトランジスタを用いても、
負荷が抵抗以外であつても同様の効果が得られる
ことは言うまでもない。また、ダイオードもシヨ
ツトキー型に限らず、どのような形式のものでも
良い。 In the above example, the differential pair transistors
Although the NPN type and the case where the load is a resistor are shown, even if a differential pair of PNP transistors is used,
It goes without saying that similar effects can be obtained even if the load is other than resistance. Further, the diode is not limited to the Schottky type, and may be of any type.
第１図は差動増幅回路の従来例を示す回路図、
第２図は本発明の一実施例を示す回路図である。
１…電源端子、２，３…出力端子、４−１，５
−１〜４−ｎ，５−ｎ…差動入力端子、６−１〜
６−ｎ…差動回路選択端子、７，８…負荷抵抗、
９−１，１０−１〜９−ｎ，１０−ｎ…差動ペア
トランジスタ、１１−１〜１１−ｎ…電流スイツ
チ用トランジスタ、１２…駆動用電流源、１４−
１，１５−１〜１４−ｎ，１５−ｎ…シヨツトキ
ーダイオード、１６−１〜１６−ｎ…差動増幅回
路。
Figure 1 is a circuit diagram showing a conventional example of a differential amplifier circuit.
FIG. 2 is a circuit diagram showing one embodiment of the present invention. 1...Power terminal, 2,3...Output terminal, 4-1,5
-1 to 4-n, 5-n...differential input terminal, 6-1 to
6-n... Differential circuit selection terminal, 7, 8... Load resistance,
9-1, 10-1 to 9-n, 10-n...differential pair transistors, 11-1 to 11-n...current switch transistors, 12...driving current source, 14-
1, 15-1 to 14-n, 15-n... Schottky diode, 16-1 to 16-n... differential amplifier circuit.
Claims (1)
第２のトランジスタを含む複数の差動回路と、こ
れら差動回路の中の選択されたものに動作電流を
供給する手段と、前記複数の差動回路のための共
通の負荷とを有する差動増幅回路において、前記
複数の差動回路の各々の前記第１および第２のト
ランジスタのコレクタと前記共通の負荷との間に
コレクタ電流が流れる向きにダイオードを設けた
ことを特徴とする差動増幅回路。1 a plurality of differential circuits each including a first and a second transistor connected in a differential manner; means for supplying an operating current to selected ones of the differential circuits; and a common load for a differential circuit, the direction in which a collector current flows between the collectors of the first and second transistors of each of the plurality of differential circuits and the common load. A differential amplifier circuit characterized in that a diode is provided in the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5447783A JPS59181711A (en) | 1983-03-30 | 1983-03-30 | Differential amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5447783A JPS59181711A (en) | 1983-03-30 | 1983-03-30 | Differential amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59181711A JPS59181711A (en) | 1984-10-16 |
| JPH0244164B2 true JPH0244164B2 (en) | 1990-10-03 |
Family
ID=12971743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5447783A Granted JPS59181711A (en) | 1983-03-30 | 1983-03-30 | Differential amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59181711A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2600844A1 (en) * | 1986-06-27 | 1987-12-31 | Commissariat Energie Atomique | DOUBLE DIFFERENTIAL SOURCE AMPLIFIER WITH FOUR INDEPENDENT INPUTS |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55138981A (en) * | 1979-04-16 | 1980-10-30 | Matsushita Electric Ind Co Ltd | Signal amplifying circuit |
| JPS5884512A (en) * | 1981-11-16 | 1983-05-20 | Matsushita Electric Ind Co Ltd | Signal amplifying circuit |
-
1983
- 1983-03-30 JP JP5447783A patent/JPS59181711A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59181711A (en) | 1984-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0121703B2 (en) | ||
| JPS59117343A (en) | Output multiplexer with 1-gate delay | |
| US4833421A (en) | Fast one out of many differential multiplexer | |
| JPH0329513A (en) | Line driver | |
| JPH0244164B2 (en) | ||
| US4177392A (en) | Current switching networks | |
| JPH0124377B2 (en) | ||
| US4260955A (en) | Current amplifier with regenerative latch switch | |
| JP2897522B2 (en) | Current mirror circuit | |
| JPS59117825A (en) | Semiconductor switching device | |
| JPH0733463Y2 (en) | Data transmission circuit | |
| JPH0528825Y2 (en) | ||
| JP2710362B2 (en) | Ternary logic circuit | |
| JPS605663Y2 (en) | Video signal switch | |
| JP2573612B2 (en) | Current switching type logic circuit | |
| JPH026684Y2 (en) | ||
| JPS5924195Y2 (en) | transistor circuit | |
| SU936378A1 (en) | Power amplifier | |
| JPH10511813A (en) | Non-separable integrated circuit board | |
| JPS5869117A (en) | Switching circuit | |
| JPH0251291B2 (en) | ||
| JPH0219648B2 (en) | ||
| JPH02112007A (en) | Reference voltage generation circuit | |
| JPS60235515A (en) | Operational amplifier | |
| JPS6197862A (en) | semiconductor equipment |