JPH0244404B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential amplifier having differential inputs and differential outputs, and in particular to a differential amplifier suitable for implementation in a monolithic integrated circuit.

Conventionally, circuits suitable for N-channel MOS monolithic integration have been proposed as differential amplifiers, but the range of application is limited due to restrictions on the input/output voltage range.

The object of the present invention is to provide a CMOS device that is free from such limitations.
The object of the present invention is to provide a circuit suitable for monolithic integration.

Another object of the present invention is to provide circuit configuration means that can avoid restrictions on the input/output operating voltage range imposed by the common mode feedback circuit portion of the conventional circuit.

The differential amplifier according to the present invention has first and second differential amplifier stages each having a pair of input terminals and a pair of output terminals, and a current sense circuit and a current mirror circuit of the second differential amplifier stage. , the current sense circuit, a circuit connection that leads the output of the current sense circuit to the input of the current mirror circuit, and a circuit connection that leads the output of the current mirror circuit to the active load current control element of the first differential amplifier stage. It is made up of.

According to one aspect of the present invention, a common source differential stage configured of first, second, and first conductivity type field effect transistors (hereinafter abbreviated as FETs), and a voltage source between the common source point and the first power supply terminal are provided. Current source circuit connection and third
A first differential amplifier circuit consisting of a dynamic load circuit configured with a fourth FET of the second conductivity type, and a fifth and sixth FET of the second conductivity type whose sources are both connected to the second current terminal. The configured differential stage and the source are both the first
the seventh and eighth first conductivity type connected to the power supply terminal of
a second operational amplifier circuit consisting of an active load circuit constituted by an FET, and a gate and a source of the fifth operational amplifier circuit;
a ninth second conductivity type FET whose gate and source are each commonly connected to the gate and source of the FET; and a tenth second conductivity type FET whose gate and source are respectively commonly connected to the gate and source of the sixth FET; 11th 12th
a current mirror circuit in which the common connection between the gates of each of the first conductivity type FETs and the drain of the 11th FET is used as an input, and the drain of the 12th FET is used as an output; and a 13th second conductivity type FET whose gates and drains are commonly connected.
and a common mode feedback circuit comprising an output of the current mirror circuit at the common connection point and a circuit to each gate of the third and fourth FET,
A circuit connection of the gate of the FET to the first and second differential input terminals, a circuit connection of the drain of the fifth and seventh FET to the first output terminal, and a second output terminal of the drain of the sixth and eighth FET. A differential amplifier is obtained having at least a circuit connection to the gate of the seventh and eighth FETs and a common connection to the common mode feedback input terminal of the gates of the seventh and eighth FETs.

This will be explained below with reference to the drawings.

Figure 1 shows an example of a conventional differential amplifier with an NMOS configuration.
His paper “A Family of Differential NMOS
Analog Circuits for PCM Codec Filter Chip”
IEEE Journal of Solid-State Circuits, vol.
This is a technology disclosed in SC-17, NO-6, Dec, 1982.

FETs 1 and 2 constitute an input differential stage 201. Depletion FETs 3 and 4 constitute an active load circuit 202, and together with FETs 1 to 4 serve as a current source.
A differential amplification stage is configured with FET50.

Furthermore, the differentially connected FETs 5 and 6 constitute an output differential stage 203, and the depletion FETs 7 and 8
constitutes the active load circuit 204, and these and the FET 51 serving as a current source constitute a second differential amplification stage. Circuits 206 and 207 are input 1
This is an offset compensation circuit between output terminals 01 and 102 and output terminals 103 and 104.

Current source from the common source connection point of FET5 and 6
The circuit connection to the gate of the FET 50 is a common-mode feedback loop, which contributes to stable biasing of the common-mode output potential of the first differential amplifier stage and the common-mode input potential of the second differential amplifier stage. Further, series circuits 207 and 206 of capacitors and FETs are frequency compensation circuits.

By the way, the common-mode output bias potential of the input stage of the circuit shown in Figure 1 is determined by the gate-source voltage (VGS) of FET 50 and the VGS of FET 5 or 6.
The potential is 2×VGS from the power supply terminal 110 of .
Therefore, the common mode input voltage range in which the first stage transistors 1 and 2 operate linearly is approximately 1VGS to 2.5VGS, which is a very narrow voltage range.

On the other hand, the common mode output voltage range of the output stage differential amplifier stage is
Since the gates of FETs 5 and 6 are in-phase biased to a potential of 2.VGS, the voltage range is limited to approximately 2.times.VGS or more.

Generally, differential amplifiers that do not have a wide common-mode input/output voltage range have the disadvantage that their range of application is extremely limited.

The circuit in which FETs 3, 4, 7, and 8 of the NMOS circuit in Figure 1 are replaced with P-channel FETs is a complementary type.
Although it can be easily realized using MOS (CMOS) circuit technology,
The output impedance of P channel FET is depletion MOS (FET3, 4, 7, 8)
The common mode output voltage range can only be expanded by being superior to the output impedance of (the impedance considering the gate-source short circuit).

Figure 2 shows the IEEE Jovrnal of Solid State Circ.
―uits, Vol―SC―6, No6, Dec, 1971, the paper “A High―Voltage Monolithic
This is another conventional example of a differential amplifier using bipolar transistors, which is disclosed in "OPertional Amplifier". By using opposite conductivity type transistors, the common mode input voltage range is expanded.

FIG. 3 shows an example in which a circuit equivalent to that in FIG. 2 is constructed using a CMOS integrated circuit.

The differential FETs 5 and 6 of the differential amplifier stage in the output stage are P-channel type, and the load circuits 7 and 8 are N-channel type.
Although the common mode input voltage range is expanded by using FETs, the common mode output voltage range cannot be expanded without using more effective circuit means.

Next, the basic configuration of the present invention will be shown with reference to FIG.

In FIG. 4, a first (input stage) differential amplifier stage 200 is connected to input terminals 101 and 102, and a second (output stage) is connected to output terminals 103 and 104.
A stable DC bias point is waited for by providing a current sense circuit 220 for detecting the operating current of the second stage 210 and feeding it back to the active load of the first stage. The terminal 105 is the differential stage 21
0 bias voltage (V _B ) terminal.

The configuration of the output stage amplifier 210 used in the present invention will be explained with reference to FIG. In Figure 5, Nch FET7 and 8 are active loads, Pch FET5,
6, 9, 10 are differential stages 5, 6 and current sense
It constitutes FET differential stages 9 and 10. This provides a differential amplifier circuit capable of output amplitude up to the power supply. Here, Pch FETs 5 and 9 connect Pch FETs to terminals 121 that receive output signals from the previous stage.
FETs 6 and 10 are similarly connected to differential input terminals 1222. Terminal 123 is a sense current output terminal.

A specific embodiment of the differential amplifier circuit according to the present invention will be described with reference to FIG. Note that parts common to those in FIG. 1 are given the same numbers.

Current mirror circuit 205 and P channel FET1
3 and FETs 9 and 10, a common mode feedback loop is configured to stably bias the common mode output voltage of the first stage and the differential stage 203 of the output stage differential amplifier. The common mode output potential of the input stage differential amplifier is connected to the second power supply terminal 120.
is the potential point of the VGS1 stage of FET 5 or 6. Therefore, the common mode input voltage of the first differential amplifier stage has been significantly expanded. In other words, the common mode input range is approximately 2 VGS higher than the first power supply terminal. The voltage range has been expanded from the potential to a potential approximately 1VGS below the second power supply terminal. On the other hand, the common mode output voltage range is determined by the operating voltage range of the output terminal of the second differential amplifier stage, and this terminal voltage operating range is expanded to the voltage range between the first and second power supply terminals. However, the range of linear operation is from the power supply voltage (VGS-
V _T ) is narrowed by only one step, and even this range is significantly expanded compared to the conventional example.

The common mode voltage of the second (output) stage differential amplification is connected to the feedback circuit (β-Net
-work) makes it stable.

Another embodiment of the present invention will be described with reference to FIG.

This embodiment is constructed using bipolar transistors. The input stage differential circuit includes a differential input pair made up of NPN transistors B1 and B2 whose bases are connected to input terminals 101 and 102,
It is constituted by a mirror type load circuit constituted by PNP transistors B3, B4, and B13. The output stage differential circuit includes input PNP transistors B5 and B6, sense PNP transistor B9,
B10 and NPN load transistors B7, B8
Composed by. Transistors B9, B10
The collector of is input to a mirror circuit constituted by transistors B12 and B11.

It is clear that this embodiment also operates in the same manner as the embodiment of FIG.

As explained above, the differential amplifier of the present invention significantly expands the common-mode input/output voltage range, and provides an effective differential amplifier circuit that can be applied to a wide range of applications.

Furthermore, the present invention can be configured without particularly increasing the number of constituent elements compared to the conventional example, and the CMOS configuration significantly increases the open loop gain of the common mode loop and the differential gain from differential input to differential output. This provides a differential amplifier that has been improved and has a wide range of applications in the art.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional differential amplifier with an NMOS configuration, Figure 2 is a circuit diagram showing a conventional differential amplifier with a bipolar transistor configuration, and Figure 3 is a circuit diagram showing a conventional differential amplifier with a bipolar transistor configuration.
A circuit diagram showing a conventional differential amplifier circuit with a CMOS configuration,
FIG. 4 is a block diagram showing the basic configuration of the present invention.
FIG. 5 is a circuit diagram of an output stage differential circuit according to the present invention,
FIG. 6 is a circuit diagram showing a specific embodiment of the invention, and FIG. 7 is a circuit diagram showing another embodiment of the invention. 1-10...FEI, B1-B13...Bipolar transistor.

Claims (1)

[Claims] 1 first and second driving transistors having control electrodes connected to the first and second input terminals, respectively; and a first supplying current to each common electrode of the first and second driving transistors. a current source, and first and second transistors connected to respective output electrodes of the first and second driving transistors.
an active load, the first and second driving transistors, the first current source, and the first and second active loads are interconnected to obtain first and second differential outputs. a connecting means forming a differential amplifier circuit; third and fourth driving transistors each receiving the first and second differential outputs on control electrodes; and the third and fourth driving transistors. and a first active load electrically connected to each of the output electrodes of the third and fourth driving transistors to obtain mutually complementary output signals. and a second output terminal, a first current sensing transistor whose common electrode and control electrode are respectively connected to the common electrode and control electrode of the third driving transistor, and a first current sensing transistor whose common electrode and control electrode are respectively connected to the common electrode and control electrode of the third driving transistor; A second current sensing transistor connected to the common electrode and a control electrode of the driving transistor, respectively, and a current obtained in the output electrodes of the first and second current sensing transistors. 1. A differential amplifier comprising: control means for controlling the current of one active load.