JPH0245230B2 - - Google Patents
Info
- Publication number
- JPH0245230B2 JPH0245230B2 JP57044705A JP4470582A JPH0245230B2 JP H0245230 B2 JPH0245230 B2 JP H0245230B2 JP 57044705 A JP57044705 A JP 57044705A JP 4470582 A JP4470582 A JP 4470582A JP H0245230 B2 JPH0245230 B2 JP H0245230B2
- Authority
- JP
- Japan
- Prior art keywords
- feature
- memory
- character
- result
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
- G06V30/10—Character recognition
- G06V30/16—Image preprocessing
- G06V30/166—Normalisation of pattern dimensions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
- G06V30/10—Character recognition
Landscapes
- Engineering & Computer Science (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Theoretical Computer Science (AREA)
- Image Processing (AREA)
- Character Discrimination (AREA)
Description
【発明の詳細な説明】
(技術分野)
本発明は、高速で簡単な特徴正規化回路に関す
るものである。TECHNICAL FIELD The present invention relates to a fast and simple feature normalization circuit.
(背景技術)
従来、文字認識方法としては、例えば橋本新一
郎編著「文字認識概論」(昭和57年3月20日発行)
電気通信協会第110〜113頁に記載された
Glucksmanの方法あるいは位相構造化法による
認識法等がある。(Background technology) Conventionally, as a character recognition method, for example, "Introduction to Character Recognition" edited by Shinichiro Hashimoto (published March 20, 1980)
Published in Telecommunications Association, pages 110-113
There are recognition methods such as Glucksman's method or topological structuring method.
Glucksmanの方法は、第2図に示すように、
文字パターン領域のなかの白地の各点がどういう
状況のもとでの点であるかを、その点から上下左
右方向に文字パターンを観測することによつて解
析するものである。つまり、ある点から上下左右
方向に直線を伸ばして文字を見たとき、文字線に
ぶつからなければ0、1回ぶつかれば1、そして
2回以上ぶつかれば2と定義する3値符号化を行
う。例えば第2図の点Pは、この方法により、
(2012)と符号化される。ただし、方向は左上下
右の順に表している。 Glucksman's method, as shown in Figure 2,
This method analyzes the situation under which each point on a white background in a character pattern area exists by observing the character pattern in the vertical, horizontal, and vertical directions from that point. In other words, when looking at a character by extending a straight line from a certain point in the vertical and horizontal directions, ternary encoding is performed in which the character is defined as 0 if it does not collide with the character line, 1 if it collides once, and 2 if it collides two or more times. For example, point P in Figure 2 can be obtained using this method.
(2012). However, the directions are shown in the order of left, top, right.
これら各点毎に付与される符号を特徴と呼ぶ。
Glucksmanの方法では、識別処理は、各符号
(すなわち各特徴)の種類とその領域の面積(言
うなれば、各特徴の出現個数の計数結果)とをも
とに行われる。 The code assigned to each of these points is called a feature.
In Glucksman's method, identification processing is performed based on the type of each code (that is, each feature) and the area of the region (in other words, the result of counting the number of appearances of each feature).
また、位相構造化法による文字認識の場合、識
別処理は入力文字パターンに存在する高次化特徴
の種類とその個数をもとに行われる。 Furthermore, in the case of character recognition using the topological structuring method, identification processing is performed based on the type and number of higher-order features present in the input character pattern.
前述のような文字認識方法においては、文字図
形パターンより抽出して作成した特徴パターンを
格納した特徴パターンレジスタ内の各特徴の出現
個数を計数した後に、文字の大きさの変動特に手
書文字の書き手による大きさの違い等を吸収する
為に、前記計数結果を文字の大きさ等により正規
化を行なうことが多い。(1)式はその正規化の式の
例である。 In the character recognition method described above, after counting the number of occurrences of each feature in a feature pattern register that stores feature patterns extracted from character/figure patterns, changes in character size, especially handwritten characters, are calculated. In order to absorb differences in size depending on the writer, the counting results are often normalized based on the size of the characters. Equation (1) is an example of the normalization equation.
Fi=fi×C/Δx×Δy (1)
但し、fiは各特徴iの出現個数の計数結果、Δx
及びΔyは文字外接枠の水平方向及び垂直方向の
長さ、Cは整数化定数、Fiは特徴iの正規化結果
である。しかしながら、上式の例の様に正規化の
為には乗算及び割算の機能が必要であり、装置化
の場合に複雑な回路となり、又各特徴iの出現個
数を計数した後に乗算及び割算を行なう為に処理
時間の低下を招いていた。 F i =f i ×C/Δx×Δy (1) However, f i is the result of counting the number of appearances of each feature i, Δx
and Δy are the horizontal and vertical lengths of the character circumscribing frame, C is an integerization constant, and F i is the normalization result of feature i. However, as in the example above, normalization requires multiplication and division functions, which results in a complicated circuit when converted into a device, and multiplication and division after counting the number of occurrences of each feature i. The processing time was reduced due to the calculation.
(発明の課題)
本発明は従来の技術の上記欠点を改善するもの
で、その目的は、高速で簡単な構成の特徴正規化
回路を提供することにあり、その特徴は、文字図
形パターンより複数の特徴を抽出して作成した特
徴パターンを格納する特徴パターンレジスタ内の
各特徴iの出現個数の計数結果fiを文字の大きさ
に従つて式;
Fi=fi×C/Δx×Δy
fi:各特徴iの出現個数の計数結果
C;整数化定数
Δx、Δy;文字外接枠のたて方向及び横方向の長
さ
Fi;正規化結果
により正規化する特徴正規化回路において、Δx
及びΔyの値を格納するレジスタと、該レジスタ
の出力をアドレス入力として受容し当該アドレス
にC/Δx×Δyを格納する固定メモリと、各特徴i
に対応した記憶番地を有しかつ初期値がクリアさ
れている特徴メモリと、前記特徴パターンレジス
タを走査して各特徴iがそれぞれ検出される都
度、前記特徴メモリの各特徴i対応の記憶番地の
内容と前記固定メモリの出力とを加算し、その和
を前記特徴メモリの前記記憶番地に再格納する加
算器と、該加算器による加算を各特徴i毎にそれ
ぞれの出現個数の計数結果であるfi回だけ繰返し
実行する為の手段とを有するごとき特徴正規化回
路にある。(Problem of the Invention) The present invention aims to improve the above-mentioned drawbacks of the conventional technology, and its purpose is to provide a feature normalization circuit that is fast and has a simple configuration. The count result f i of the number of occurrences of each feature i in the feature pattern register that stores the feature pattern created by extracting the features is calculated according to the font size; F i = f i ×C/Δx × Δy f i : Result C of counting the number of occurrences of each feature i; Integerization constants Δx, Δy; Length F i in the vertical and horizontal directions of the character circumscribing frame; In the feature normalization circuit that normalizes based on the normalization result, Δx
and Δy, a fixed memory that receives the output of the register as an address input and stores C/Δx×Δy at the address, and a memory address corresponding to each feature i and whose initial value is Each time each feature i is detected by scanning the cleared feature memory and the feature pattern register, the content of the memory address corresponding to each feature i in the feature memory and the output of the fixed memory are added; an adder for re-storing the sum in the memory address of the feature memory; and means for repeatedly performing addition by the adder f i times, which is the result of counting the number of occurrences of each feature i. It is in the feature normalization circuit as shown in FIG.
(発明の構成及び作用)
第1図は、本発明の文字認識装置内における実
施例の構成図であり、1はアドレス番号としての
特徴番号入力、2は文字幅レジスタ、3は文字高
さレジスタ、4はROMにより構成される固定メ
モリ、5は加算器、6は特徴メモリである。な
お、特徴パターンレジスタ(図示せず)には、予
め入力文字図形パターンより複数の特徴を抽出し
て作成した特徴パターンを格納している。(Structure and operation of the invention) FIG. 1 is a block diagram of an embodiment in the character recognition device of the invention, in which 1 is a feature number input as an address number, 2 is a character width register, and 3 is a character height register. , 4 is a fixed memory constituted by ROM, 5 is an adder, and 6 is a feature memory. Note that a feature pattern register (not shown) stores a feature pattern created in advance by extracting a plurality of features from an input character/figure pattern.
本実施例は、前記(1)式の実施例である。固定メ
モリ4(以後ROMと称する)は入力を文字幅
(Δx)及び文字高さ(Δy)とする固定メモリで
あり、Δx及びΔyで番地指定された記憶内容は下
記の(2)式で表わされる。 This example is an example of the above formula (1). Fixed memory 4 (hereinafter referred to as ROM) is a fixed memory whose inputs are character width (Δx) and character height (Δy), and the memory contents specified by addresses by Δx and Δy are expressed by the following equation (2). It will be done.
C/Δx×Δy (2)
但しCは(1)式の整数化定数であり、本実施例で
はC=100、(2)式の結果すなわちROMの出力は
2進数表現の実数型である。(例10進表現で0.5の
時ROMの出力は0.1、.は小数点)本実施例の動
作は以下の通りである。 C/Δx×Δy (2) where C is an integer conversion constant in equation (1), and in this embodiment, C=100, and the result of equation (2), that is, the output of the ROM, is a real number type expressed in binary. (For example, when the value is 0.5 in decimal notation, the output of the ROM is 0.1, and . is a decimal point.) The operation of this embodiment is as follows.
まず、あらかじめ特徴メモリ6の内容をクリア
しておく。次に、入力文字パターンの文字外接枠
の大きさを文字幅レジスタ2及び文字高さレジス
タ3にセツトしておく。特徴番号入力1として特
徴iの特徴番号iが特徴メモリ6のアドレス指定
のために入力されると、特徴メモリ6のi番地の
内容が読み出され、文字幅レジスタ2及び文字高
さレジスタ3により番地指定されたROMの内容
と加算器5により加算され、再び特徴メモリ6の
i番地に書き込まれる。以上説明した各特徴iの
特徴番号iの入力から特徴メモリに書き込むまで
の処理は、複数の特徴を抽出して作成した特徴パ
ターンを格納する特徴パターンレジスタを走査手
段(図示せず)を用いてスキヤン(走査)して各
特徴iがそれぞれ検出されるたび毎に繰返され、
最終的に各特徴i毎にそれぞれの出現個数の計数
結果であるfi回だけ繰返して行われることにな
る。最終的な特徴メモリ6のi番地の内容の整数
部は、(1)式で示される特徴iの正規化した結果で
ある。 First, the contents of the feature memory 6 are cleared in advance. Next, the size of the character circumscribing frame of the input character pattern is set in the character width register 2 and character height register 3. When feature number i of feature i is input as feature number input 1 to specify the address of feature memory 6, the contents of address i of feature memory 6 are read out, and are read out by character width register 2 and character height register 3. The contents of the ROM specified by the address are added by the adder 5, and the result is written to address i of the feature memory 6 again. The process from inputting the feature number i of each feature i to writing it into the feature memory as described above is performed by using a scanning means (not shown) to scan a feature pattern register that stores feature patterns created by extracting multiple features. It is repeated each time each feature i is detected by scanning,
Ultimately, the process is repeated f i times, which is the result of counting the number of occurrences of each feature i. The integer part of the final content at address i in the feature memory 6 is the normalized result of feature i shown by equation (1).
以上説明した様に、本実施例は、(1)式を下記(3)
式の様に変形して実行したことにほかならない。 As explained above, in this example, equation (1) is transformed into the following equation (3).
This is nothing more than a transformation and execution as in the formula.
Fi=C/Δx×Δy×fi (3)
つまり、C/Δx×Δy(ROMの出力)を特徴iの
出現個数倍することにより、正規化した結果を本
実施例では計算している。 F i =C/Δx×Δy×f i (3) In other words, in this example, the normalized result is calculated by multiplying C/Δx×Δy (ROM output) by the number of occurrences of feature i. .
以上説明した様に本実施例は、乗算、割算を行
なうことなく、又文字認識装置における特徴パタ
ーンレジスタのスキヤンと同時に特徴の正規化し
た結果を加算という演算のみにより計算すること
ができるので、高速な処理を簡単な回路で実現で
きる利点がある。 As explained above, in this embodiment, calculations can be made only by adding the normalized results of features at the same time as scanning the feature pattern register in the character recognition device without performing multiplication or division. It has the advantage of achieving high-speed processing with a simple circuit.
(発明の効果)
本発明は、固定メモリ及び加算回路を使用する
ことにより特徴の計数と正規化を同時に行なつて
いるので、高速で簡単な回路構成をもつた文字認
識装置を実現することができる。(Effects of the Invention) Since the present invention simultaneously performs feature counting and normalization by using a fixed memory and an addition circuit, it is possible to realize a character recognition device that is fast and has a simple circuit configuration. can.
第1図は本発明の実施例の構成図であり、第2
図は従来のGlucksmanの方法による特徴抽出を
例示した図である。
1……特徴番号入力、2……文字幅レジスタ、
3……文字高さレジスタ、4……固定メモリ、5
……加算器、6……特徴メモリ。
FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG.
The figure is a diagram illustrating feature extraction using the conventional Glucksman method. 1...Characteristic number input, 2...Character width register,
3...Character height register, 4...Fixed memory, 5
...Adder, 6...Feature memory.
Claims (1)
作成した特徴パターンを格納する特徴パターンレ
ジスタ内の各特徴iの出現個数の計数結果fiを文
字の大きさに従つて式; Fi=fi×C/Δx×Δy fi;各特徴iの出現個数の計数結果 C;整数化定数 Δx、Δy;文字外接枠のたて方向及び横方向の長
さ Fi;正規化結果 により正規化する特徴正規化回路において、Δx
及びΔyの値を格納するレジスタと、該レジスタ
の出力をアドレス入力として受容し当該アドレス
にC/Δx×Δyを格納する固定メモリと、各特徴i に対応した記憶番地を有しかつ初期値がクリアさ
れている特徴メモリと、前記特徴パターンレジス
タを走査して各特徴iがそれぞれ検出される都
度、前記特徴メモリの各特徴i対応の記憶番地の
内容と前記固定メモリの出力とを加算し、その和
を前記特徴メモリの前記記憶番地に再格納する加
算器と、該加算器による加算を各特徴i毎にそれ
ぞれの出現個数の計数結果であるfi回だけ繰返し
実行する為の手段とを有することを特徴とする特
徴正規化回路。[Scope of Claims] 1. The count result f i of the number of occurrences of each feature i in a feature pattern register that stores a feature pattern created by extracting a plurality of features from a character/figure pattern is calculated according to the size of the character. ; F i = f i ×C/Δx × Δy f i ; Result of counting the number of occurrences of each feature i C; Integer conversion constants Δx, Δy; Length of character circumscribing frame in vertical and horizontal directions F i ; Normal In the feature normalization circuit that normalizes based on the normalization result, Δx
and Δy, a fixed memory that receives the output of the register as an address input and stores C/Δx×Δy at the address, and a memory address corresponding to each feature i and whose initial value is Each time each feature i is detected by scanning the cleared feature memory and the feature pattern register, the content of the memory address corresponding to each feature i in the feature memory and the output of the fixed memory are added; an adder for re-storing the sum in the memory address of the feature memory; and means for repeatedly performing addition by the adder f i times, which is the result of counting the number of occurrences of each feature i. A feature normalization circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57044705A JPS58163077A (en) | 1982-03-23 | 1982-03-23 | Feature normalizing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57044705A JPS58163077A (en) | 1982-03-23 | 1982-03-23 | Feature normalizing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58163077A JPS58163077A (en) | 1983-09-27 |
| JPH0245230B2 true JPH0245230B2 (en) | 1990-10-08 |
Family
ID=12698829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57044705A Granted JPS58163077A (en) | 1982-03-23 | 1982-03-23 | Feature normalizing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58163077A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0439612U (en) * | 1990-08-01 | 1992-04-03 |
-
1982
- 1982-03-23 JP JP57044705A patent/JPS58163077A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0439612U (en) * | 1990-08-01 | 1992-04-03 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58163077A (en) | 1983-09-27 |
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