JPH0247105B2 - - Google Patents
Info
- Publication number
- JPH0247105B2 JPH0247105B2 JP59202253A JP20225384A JPH0247105B2 JP H0247105 B2 JPH0247105 B2 JP H0247105B2 JP 59202253 A JP59202253 A JP 59202253A JP 20225384 A JP20225384 A JP 20225384A JP H0247105 B2 JPH0247105 B2 JP H0247105B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- sealing
- lsi
- sealing resin
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特に大規模集積回路装置
（Large Scale Integration 以下「LSI」とい
う。）の樹脂による封止の方法の改善に関するも
のである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an improvement in the method of sealing semiconductor devices, particularly large scale integrated circuit devices (hereinafter referred to as "LSI"), with resin. .
第３図は従来のLSIを樹脂封止したものの断面
図で、１は外部リード端子、２はダイパツド、３
はLSIチツプ、４はISIチツプ３と外部リード端
子１とを電気的につなぐAl細線、５は封止樹脂
である。従来の封止方法においては封止樹脂５は
第３図に示すように製品の最終形態を一度の工程
で封止するのが通例である。工程の単純化という
点からは上述の方法が最善と考えられてきた。
Figure 3 is a cross-sectional view of a conventional LSI sealed with resin, where 1 is an external lead terminal, 2 is a die pad, and 3 is a resin-sealed LSI.
4 is an LSI chip, 4 is an Al thin wire that electrically connects the ISI chip 3 and the external lead terminal 1, and 5 is a sealing resin. In conventional sealing methods, the sealing resin 5 usually seals the final form of the product in one step, as shown in FIG. The above method has been considered the best in terms of process simplification.
以上のような従来の方法では、LSIチツプ３の
寸法の増加につれて封止樹脂５が硬化する際のス
トレスが無視しえなくなりつつあり、著しい場合
においては、LSIチツプ３表面の周辺部分のAl配
線パターン（図示せず）またはAl細線４を変形
させることが本発明者等により確認されている。
In the conventional method as described above, as the size of the LSI chip 3 increases, the stress caused when the sealing resin 5 hardens becomes impossible to ignore, and in severe cases, the Al wiring around the surface of the LSI chip 3 is damaged. The inventors have confirmed that the pattern (not shown) or the Al thin wire 4 can be deformed.
また、封止樹脂５は第４図に示すように、エポ
キシ樹脂部分６とLSIチツプ３との熱膨張係数を
近づけるためにフイラー７と称する充填材とから
なつており、通常合成石英の粉末がフイラー７と
して用いられているが、LSIチツプ３の表面に接
触しているフイラー７ａが局所的に非常に大きな
圧力をLSIチツプ３に及ぼすことによりLSIの誤
動作を招くことも本発明者等により確認されてい
る。この現象は、LSIチツプ３のパターンが微細
化し、信号電荷が微弱になるほど、且つ封止樹脂
５のストレスが大きいLSIチツプ３の周辺部程著
しいという問題点があつた。 Furthermore, as shown in FIG. 4, the sealing resin 5 is made of a filler called a filler 7 in order to bring the thermal expansion coefficients of the epoxy resin portion 6 and the LSI chip 3 closer together, and is usually made of synthetic quartz powder. Although the filler 7a is used as the filler 7, the inventors have also confirmed that the filler 7a, which is in contact with the surface of the LSI chip 3, locally exerts extremely large pressure on the LSI chip 3, causing malfunction of the LSI. has been done. This phenomenon is problematic as it becomes more pronounced as the pattern of the LSI chip 3 becomes finer, the signal charge becomes weaker, and the stress on the sealing resin 5 is greater at the periphery of the LSI chip 3.
本発明はこのような問題点を解決するためにな
されたもので、半導体チツプ周辺部への封止樹脂
のストレスの集中を緩和できるような封止方法を
得ることを目的としている。 The present invention has been made to solve these problems, and an object of the present invention is to provide a sealing method that can alleviate the stress concentration of the sealing resin on the periphery of a semiconductor chip.
この発明の封止方法は半導体チツプの中央部と
両端部とを別工程で樹脂封止するものである。
In the sealing method of the present invention, the center and both ends of a semiconductor chip are sealed with resin in separate steps.
この発明では、半導体チツプの中央部と両端部
とを別工程で樹脂封止することによつて封止樹脂
のストレスの集中を緩和する。
In this invention, concentration of stress on the sealing resin is alleviated by sealing the center and both ends of the semiconductor chip with resin in separate steps.
第１図Ａ、Ｂはこの発明の一実施例の各工程段
階での状態を示す断面図で、前述の第３図の従来
例と同一符号は同等部分を示し、その説明は重複
を避ける。この実施例ではまず第１図Ａに示すよ
うに、LSIチツプ３の中央部を封止樹脂５ａで封
止、硬化させる。次いで、第１図Ｂに示すように
残余の部分を封止樹脂５ｂで封止して、樹脂封止
を完結する。
FIGS. 1A and 1B are cross-sectional views showing the state of an embodiment of the present invention at each step of the process. The same reference numerals as in the conventional example shown in FIG. In this embodiment, first, as shown in FIG. 1A, the center portion of the LSI chip 3 is sealed and hardened with a sealing resin 5a. Next, as shown in FIG. 1B, the remaining portion is sealed with a sealing resin 5b to complete the resin sealing.
第２図Ａ、Ｂはこの発明の他の実施例の各工程
段階での状態を示す断面図で、この実施例では、
まず第２図Ａに示すように、LSIチツプ３の両端
部を封止樹脂５ｂで封止、硬化させ、次いで第２
図Ｂに示すように残余の中央部を封止樹脂５ａで
封止して、樹脂封止を完結する。 FIGS. 2A and 2B are cross-sectional views showing the state at each process step of another embodiment of the present invention, and in this embodiment,
First, as shown in FIG. 2A, both ends of the LSI chip 3 are sealed and hardened with a sealing resin 5b, and then a second
As shown in FIG. B, the remaining central portion is sealed with a sealing resin 5a to complete the resin sealing.
上記実施例ではLSIチツプを対象としたが、半
導体チツプ一般に広く適用できることは勿論であ
る。 In the above embodiment, the target is an LSI chip, but it goes without saying that the present invention can be widely applied to semiconductor chips in general.
以上説明したように、この発明では半導体チツ
プを樹脂封止するに際してその中央部と両端部と
を別工程で一方を封止、硬化させてから他方を封
止するようにしたので、硬化に伴うストレスの発
生を大幅に低減でき、半導体チツプへの悪影響も
極めて少なくすることができる。
As explained above, in this invention, when sealing a semiconductor chip with resin, the central part and both ends are sealed in separate steps, and one is cured and then the other is sealed. The occurrence of stress can be significantly reduced, and the adverse effects on semiconductor chips can also be extremely reduced.
第１図Ａ、Ｂはこの発明の一実施例の各工程段
階での状態を示す断面図、第２図Ａ、Ｂはこの発
明の他の実施例の各工程段階での状態を示す断面
図、第３図は従来の樹脂封止LSIの断面図、第４
図はその封止樹脂部分の詳細を示す拡大部分断面
図である。
図において、３は半導体チツプ（LSIチツプ）、
５ａは中央部封止樹脂、５ｂは両端部封止樹脂で
ある。なお、各図中同一符号は同一または相当部
分を示す。
FIGS. 1A and B are sectional views showing the state of one embodiment of the present invention at each process step, and FIGS. 2A and B are sectional views showing the state of another embodiment of the present invention at each process step. , Figure 3 is a cross-sectional view of a conventional resin-encapsulated LSI, Figure 4 is a cross-sectional view of a conventional resin-encapsulated LSI.
The figure is an enlarged partial sectional view showing details of the sealing resin portion. In the figure, 3 is a semiconductor chip (LSI chip),
5a is a center sealing resin, and 5b is a both end sealing resin. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
に一方を樹脂で封止し硬化させてから他方を樹脂
で封止することを特徴とする半導体装置の樹脂封
止方法。1. A method for resin-sealing a semiconductor device, which comprises individually sealing the central portion and both ends of a semiconductor chip with a resin, curing the central portion, and then sealing the other portion with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59202253A JPS6178126A (en) | 1984-09-25 | 1984-09-25 | Resin sealing process for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59202253A JPS6178126A (en) | 1984-09-25 | 1984-09-25 | Resin sealing process for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6178126A JPS6178126A (en) | 1986-04-21 |
| JPH0247105B2 true JPH0247105B2 (en) | 1990-10-18 |
Family
ID=16454482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59202253A Granted JPS6178126A (en) | 1984-09-25 | 1984-09-25 | Resin sealing process for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6178126A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06254747A (en) * | 1993-03-03 | 1994-09-13 | Daishowa Seiki Co Ltd | Tool attaching position regulating method and measuring tool for regulation |
-
1984
- 1984-09-25 JP JP59202253A patent/JPS6178126A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06254747A (en) * | 1993-03-03 | 1994-09-13 | Daishowa Seiki Co Ltd | Tool attaching position regulating method and measuring tool for regulation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6178126A (en) | 1986-04-21 |
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