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JPH0247844B2 - SERAMITSUKUBARISUTA - Google Patents
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JPH0247844B2 - SERAMITSUKUBARISUTA - Google Patents

SERAMITSUKUBARISUTA

Info

Publication number
JPH0247844B2
JPH0247844B2 JP56176000A JP17600081A JPH0247844B2 JP H0247844 B2 JPH0247844 B2 JP H0247844B2 JP 56176000 A JP56176000 A JP 56176000A JP 17600081 A JP17600081 A JP 17600081A JP H0247844 B2 JPH0247844 B2 JP H0247844B2
Authority
JP
Japan
Prior art keywords
heat
ceramic
resistant insulating
insulating layer
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56176000A
Other languages
Japanese (ja)
Other versions
JPS5877203A (en
Inventor
Mikio Sumyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56176000A priority Critical patent/JPH0247844B2/en
Publication of JPS5877203A publication Critical patent/JPS5877203A/en
Publication of JPH0247844B2 publication Critical patent/JPH0247844B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Thermistors And Varistors (AREA)

Description

【発明の詳細な説明】 本発明はセラミツクバリスタに関するものであ
つて、その目的とするところは異常電圧又は過大
な侵入サージによつて破損されることのない自己
防御作用を備えたセラミツクバリスタを提供する
ことにある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ceramic varistor, and its purpose is to provide a ceramic varistor with a self-protection function that will not be damaged by abnormal voltage or excessive intrusion surge. It's about doing.

酸化亜鉛を主体とするセラミツクバリスタは、
酸化亜鉛にビスマス、アンチモン、コバルト、マ
ンガン等の金属酸化物を添加して混合成形し、
1000〜1300℃で焼結して形成され、すぐれた非直
線電圧抵抗特性を有するので各種電気回路のサー
ジ吸収器として広く用いられている。第1図は従
来のセラミツクバリスタを示している。1はセラ
ミツク基板で、その表面および裏面には、銀又は
銅、あるいはアルミニユーム等の導電性金属の焼
き付け、メツキあるいは溶射等によつて平面電極
2,2′を形成している。3,3′は平面電極2,
2′に半田付けされたリード線である。
Ceramic varistors are mainly made of zinc oxide.
Metal oxides such as bismuth, antimony, cobalt, and manganese are added to zinc oxide and mixed and molded.
It is formed by sintering at 1000-1300°C and has excellent non-linear voltage resistance characteristics, so it is widely used as a surge absorber in various electrical circuits. FIG. 1 shows a conventional ceramic varistor. Reference numeral 1 denotes a ceramic substrate, on the front and back surfaces of which planar electrodes 2, 2' are formed by baking, plating, or spraying a conductive metal such as silver, copper, or aluminum. 3, 3' are plane electrodes 2,
This is the lead wire soldered to 2'.

ところで上記構造のセラミツクバリスタは、定
格最大値以上の異常電圧が印加されたとき、ある
いは耐量以上の過大サージが侵入したときは短
絡、破壊されるので、回路に遮断器又は電流ヒユ
ーズを接続してこれを異常電圧および過大サージ
から保護している。本発明はこの点にかんがみ、
セラミツクバリスタそれ自体に異常電圧および過
大サージに対する防御機能を付与することによ
り、遮断器、電流ヒユーズ等を省略し、配線基板
を簡素化することを意図するものである。
By the way, the ceramic varistor of the above structure will short circuit or be destroyed if an abnormal voltage exceeding the maximum rated value is applied or if an excessive surge exceeding the withstand capacity enters, so connect a circuit breaker or current fuse to the circuit. This protects it from abnormal voltages and excessive surges. In view of this point, the present invention
By providing the ceramic varistor itself with a protective function against abnormal voltages and excessive surges, circuit breakers, current fuses, etc. are omitted, and the wiring board is intended to be simplified.

本発明の実施例を第2図、第3図および第4図
によつて説明する。第2図において、4は長方形
のセラミツク基板で、その表面および裏面の中央
部には若干の巾をもつ耐熱絶縁層5,5′が設け
てある。この耐熱絶縁層5,5′は耐熱ガラスあ
るいはアルミナなどの耐熱性無機絶縁材料を焼付
け、溶射などの方法によつて数十μm程度の厚さ
に形成される。第3図において、6,6′は表面
および裏面の中央部に設けた前記耐熱絶縁層5,
5′の両側に分離して設けた平面電極で、巾の狭
い渡り電極7,7′によつて連通されている。平
面電極6,6′は銀又は銅あるいはアルミニユー
ムの焼付け、メツキ、溶射などの方法によつて形
成される。渡り電極7,7′は比較的融点の低い
アルミニユーム等の易溶性金属の溶射あるいは蒸
着によつて耐熱絶縁層5,5′の上に形成され、
その厚さは数ミクロンないし30μmである。8,
8′は表面および裏面の共通電極7,7′の中心部
に半田付けされたリード線である。リード線8,
8′を半田付けしたセラミツク基板4は、その表
面をエポキシ樹脂などによつてコーテイングされ
る。第4図は本発明の他の実施例である。この実
施例は耐熱絶縁層および渡り電極を含む上記の構
造をセラミツク基板の表面にのみ設け、裏面には
第1図の平面電極2′と同様な裏面電極9を設け、
これにリード線8′が半田付けしてある。
Embodiments of the present invention will be described with reference to FIGS. 2, 3, and 4. In FIG. 2, reference numeral 4 denotes a rectangular ceramic substrate, and heat-resistant insulating layers 5, 5' having a certain width are provided at the center of its front and back surfaces. The heat-resistant insulating layers 5, 5' are formed of a heat-resistant inorganic insulating material such as heat-resistant glass or alumina to a thickness of about several tens of micrometers by baking or thermal spraying. In FIG. 3, 6 and 6' are the heat-resistant insulating layers 5 provided at the center of the front and back surfaces,
These are planar electrodes provided separately on both sides of the electrode 5', and are communicated with each other by narrow bridge electrodes 7, 7'. The plane electrodes 6, 6' are formed by baking, plating, thermal spraying, or other methods of silver, copper, or aluminum. The transition electrodes 7, 7' are formed on the heat-resistant insulating layers 5, 5' by thermal spraying or vapor deposition of easily soluble metal such as aluminum having a relatively low melting point.
Its thickness is from several microns to 30 μm. 8,
8' is a lead wire soldered to the center of the common electrodes 7, 7' on the front and back sides. Lead wire 8,
The surface of the ceramic substrate 4 to which 8' is soldered is coated with epoxy resin or the like. FIG. 4 shows another embodiment of the invention. In this embodiment, the above structure including a heat-resistant insulating layer and a transition electrode is provided only on the front surface of the ceramic substrate, and a back electrode 9 similar to the planar electrode 2' in FIG. 1 is provided on the back surface.
A lead wire 8' is soldered to this.

次に本発明のセラミツクバリスタの作用を説明
する。いま、過大サージの侵入によつて第5図に
示すようにセラミツク基板4に短絡aが発生した
とする。このときの短絡電流はリード線8から渡
り電極7,7′を通過してリード線8′に流れるか
ら易溶性金属よりなる渡り電極7,7′は通過電
流によつて溶断される。溶断の個所はb又はb′若
しくはその双方である。短絡の場所がaと反対側
のa′の場合は、溶断の個所はc又はc′若しくはそ
の双方である。第4図の実施例の場合は、溶断の
個所はb又はcのみとなる。すなわち、渡り電極
7,7′は電流ヒユーズとして作用するからその
材料、厚み、巾、長さは遮断電流によつて設定さ
れる。第1図の従来のセラミツクバリスタにおい
ては、短絡が発生すると短絡電流によつてセラミ
ツク基板に低抵抗の貫通孔を生じ、この貫通孔を
通過する過大電流のジユール熱によつてセラミツ
ク基板が焼損するが、本発明は渡り電極の溶断に
よつてこれを未然に防止するばかりでなく、短絡
が発生した後も、残りの半分がセラミツクバリス
タとしての作用を保持している。
Next, the function of the ceramic varistor of the present invention will be explained. Now, suppose that a short circuit a occurs in the ceramic substrate 4 as shown in FIG. 5 due to the intrusion of an excessive surge. At this time, the short-circuit current flows from the lead wire 8 through the transition electrodes 7, 7' to the lead wire 8', so that the transition electrodes 7, 7' made of easily soluble metal are fused by the passing current. The melting point is b or b' or both. If the short circuit is at a' on the opposite side of a, the melting point is at c or c' or both. In the case of the embodiment shown in FIG. 4, the only part that is fused is b or c. That is, since the transition electrodes 7, 7' act as current fuses, their material, thickness, width, and length are determined by the breaking current. In the conventional ceramic varistor shown in Fig. 1, when a short circuit occurs, a through hole with low resistance is created in the ceramic substrate due to the short circuit current, and the ceramic substrate is burnt out due to the excessive current passing through this through hole. However, the present invention not only prevents this from occurring by melting down the transition electrode, but also allows the remaining half to maintain its function as a ceramic varistor even after a short circuit occurs.

以上述べたように本発明のセラミツクバリスタ
は、セラミツク基板4の表面および裏面の中央部
に若干の巾をもつ耐熱絶縁層を設け、この耐熱絶
縁層の両側に分離された平面電極を前記セラミツ
ク基板4の表面および裏面に左右対称に形成し、
前記2分された平面電極を前記耐熱絶縁層の上に
形成した巾の狭い易溶性金属よりなる渡り電極よ
つて連通させ、この渡り電極の中心にリード線を
半田付けした構造を有するので、定格最大値以上
の異常電圧が印加されたとき、あるいは耐量以上
の過大サージが侵入したときには渡り電極が溶断
してセラミツクバリスタの破壊焼損を未然に防止
する。したがつて、セラミツクバリスタを保護す
るための遮断器又は電流ヒユーズの必要がないか
ら配線基板が簡素化され、冒頭で述べた本発明の
目的を達成する作用効果を有する。
As described above, in the ceramic varistor of the present invention, a heat-resistant insulating layer having a certain width is provided at the center of the front and back surfaces of the ceramic substrate 4, and planar electrodes separated on both sides of the heat-resistant insulating layer are attached to the ceramic substrate. Formed symmetrically on the front and back sides of 4,
The bisected plane electrodes are connected to each other by a narrow cross-over electrode made of easily soluble metal formed on the heat-resistant insulating layer, and a lead wire is soldered to the center of the cross-over electrode, so that the rated When an abnormal voltage exceeding the maximum value is applied, or when an excessive surge exceeding the withstand capacity enters, the crossover electrode melts to prevent destruction and burnout of the ceramic varistor. Therefore, since there is no need for a circuit breaker or a current fuse to protect the ceramic varistor, the wiring board is simplified, and this has the effect of achieving the object of the present invention as stated at the beginning.

【図面の簡単な説明】[Brief explanation of drawings]

第1図:従来のセラミツクバリスタを示す図
で、イは平面図、ロは側面図、第2図:本発明の
セラミツク基板の実施例を示す図で、イは平面
図、ロは側面図、第3図:本発明のセラミツクバ
リスタの実施例を示す図で、イは平面図、ロは側
面図、第4図:本発明のセラミツクバリスタの他
の実施例の側面図、第5図:本発明のセラミツク
バリスタの作用説明図。 記号、4……セラミツク基板、5,5′……耐
熱絶縁層、6,6′……平面電極、7,7′……渡
り電極、8,8′……リード線、9……裏面電極。
Fig. 1: A diagram showing a conventional ceramic varistor, in which A is a plan view and B is a side view. Fig. 2: A diagram showing an embodiment of the ceramic substrate of the present invention, in which A is a plan view and B is a side view. Figure 3: Diagrams showing an embodiment of the ceramic varistor of the present invention, A is a plan view, B is a side view, Figure 4: A side view of another embodiment of the ceramic varistor of the present invention, Figure 5: Main view. FIG. 2 is an explanatory diagram of the action of the ceramic varistor of the invention. Symbol, 4... Ceramic substrate, 5, 5'... Heat resistant insulating layer, 6, 6'... Planar electrode, 7, 7'... Crossover electrode, 8, 8'... Lead wire, 9... Back electrode .

Claims (1)

【特許請求の範囲】[Claims] 1 セラミツク基板の表面および裏面の少なくと
も一方の面の中央部に若干の幅をもつ耐熱絶縁層
を設け、この耐熱絶縁層の両側に分離された平面
電極を前記セラミツク基板面に左右対称に形成
し、前記2分された平面電極を前記耐熱絶縁層の
上に設けた幅の狭い易溶性金属よりなる渡り電極
によつて連通させ、この渡り電極の中心部に、リ
ード線を半田付けしたことを特徴とするセラミツ
クバリスタ。
1. A heat-resistant insulating layer having a slight width is provided in the center of at least one of the front and back surfaces of a ceramic substrate, and planar electrodes separated on both sides of this heat-resistant insulating layer are formed symmetrically on the surface of the ceramic substrate. , the bisected plane electrodes are communicated with each other by a narrow cross-over electrode made of an easily soluble metal provided on the heat-resistant insulating layer, and a lead wire is soldered to the center of the cross-over electrode. Ceramic barista features.
JP56176000A 1981-11-02 1981-11-02 SERAMITSUKUBARISUTA Expired - Lifetime JPH0247844B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56176000A JPH0247844B2 (en) 1981-11-02 1981-11-02 SERAMITSUKUBARISUTA

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56176000A JPH0247844B2 (en) 1981-11-02 1981-11-02 SERAMITSUKUBARISUTA

Publications (2)

Publication Number Publication Date
JPS5877203A JPS5877203A (en) 1983-05-10
JPH0247844B2 true JPH0247844B2 (en) 1990-10-23

Family

ID=16005951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56176000A Expired - Lifetime JPH0247844B2 (en) 1981-11-02 1981-11-02 SERAMITSUKUBARISUTA

Country Status (1)

Country Link
JP (1) JPH0247844B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0523638U (en) * 1991-08-13 1993-03-26 アルプス電気株式会社 Double super heterodyne system tuner

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105304243A (en) * 2015-11-12 2016-02-03 郑品章 Voltage dependent resistor (VDR)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0523638U (en) * 1991-08-13 1993-03-26 アルプス電気株式会社 Double super heterodyne system tuner

Also Published As

Publication number Publication date
JPS5877203A (en) 1983-05-10

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