JPH0248935B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a stack device for realizing a high performance stack machine architecture represented by the B6500 manufactured by Burroughs Corporation in the United States, which is a famous commercial computer. More specifically,
Relating to a stack device that enables a stack area corresponding to each mode to always exist on a high-speed register stack in a stack machine architecture that has multiple internal states defined as supervisor mode and user mode. .

Stack machine architecture was typically implemented by using a main memory device and an address pointer to indicate its address, and controlling the pointer in a last-in-first-out (LIFO) manner.

However, high performance cannot be achieved with this method of fetching and processing data necessary for arithmetic processing from a slow main memory.

For this reason, in order to realize such an architecture with high performance, a method has been used in which a high-speed register for storing data is provided in an arithmetic processing unit.

However, conventional computers are equipped with only one pair of such high-speed registers, as typified by the Burroughs B6500.

On the other hand, in a computer, execution of a control program, execution of a user program, etc. are usually performed in a time-divided manner. In this case as well, these programs are executed using the pair of high speed registers. For this reason, each program is executed by saving the contents of the high-speed register to the main memory or restoring the data saved in the main memory. That is, when switching programs, it is necessary to save and restore data, resulting in wasted time for switching.

The object of the present invention is to solve these conventional drawbacks, and to provide a plurality of register stacks consisting of a large number of words corresponding to each mode in a central processing unit, and to efficiently manage these register stacks. This is realized by

Another object of the present invention is to provide a stack device that efficiently implements a stack mechanism required in a stack machine architecture having a plurality of internal modes.

In particular, when executing instructions that process multiple words simultaneously in a stack machine architecture that has multiple internal modes, a stack device that is equipped with a register stack storing all necessary data for each mode is required. This is what we provide.

Still another object of the present invention is to use PASCAL and ALGOL.
It provides the basic stack structure of a high-level language computer that specifically processes structured programming languages such as .

According to the present invention, there is an internal mode specifying means for specifying a plurality of internal states, a plurality of blocks, each block consisting of a plurality of words, controlled in a first-in, first-out format, and corresponding to the internal states. a plurality of register stacks, a plurality of status display means for indicating the valid state of each block of the plurality of register stacks, and a plurality of addressing pointers for indicating word addresses within the blocks;
A main memory device that stores data evicted from a plurality of register stacks in a last-in, first-out format, and a plurality of main memory addresses corresponding to an internal state indicating the latest valid data area of the main memory device. The pointer and the result of the button movement,
When there are no more non-empty blocks in the register stack, the oldest full block in the register stack is ejected to the location indicated by the main memory address pointer corresponding to the internal state in the main memory; When an empty block is generated in the register stack as a result of a pop operation, the register stack corresponding to the internal state is loaded from the main memory into the oldest empty block in the register stack. and a control means for performing control between the register stack and the main memory, and controls the register stack so that data necessary for arithmetic control of all internal states is always present in the register stack. can get.

Next, an embodiment using the present invention will be described in detail. In this embodiment, a case will be described in which the internal mode has two registers, the register stack has three blocks, and one block consists of four words.

The figure shows a block diagram of this embodiment, including an internal mode specifying means 1 that defines two internal states, a register stack 21 to 23 consisting of three blocks for the first internal state, and a register stack 21 to 23 consisting of three blocks for the first internal state. Status display means 3 indicating the valid status of stacks 21 to 23
1 to 33, an addressing pointer 20 indicating the word address of the register stack 21 to 23, a register stack 41 to 43 consisting of three blocks for the second internal state, said register stack 41 to 43 status display means 51 to 53 indicating the valid status of the register stacks 41 to 4;
Addressing pointer 4 indicating the word address of 3
0, a main memory device 6, a main memory address pointer 71 corresponding to the first internal state, a main memory address pointer 72 corresponding to the second internal state, and a control means 8.

Internal mode designation means 1 is a 1-bit flip-flop, which is a commercially available D-type flip-flop IC.
This is realized using TI's SN7474.

Register stacks 21 to 23 and 41 to 43
consists of register files of 4 words each, and is commercially available.
This is achieved by combining the IC SN74189 manufactured by TI. The four words within each block are specified by two-bit addresses (00 to 11).

Status display means 31 to 33 and 51 to 53 are register stacks 21 to 23 and 41 to 43.
Each bit indicates a valid state corresponding to a 1-bit flip-flop.

Addressing pointers 20 and 40 are 2-bit flip-flops implemented with commercially available ICs.
And one of the four words in one block
Select one.

The main memory device 6 corresponds to the main memory of a conventional computer and is realized by a commercially available IC memory. Then, data overflowing from the register stacks 21 to 23 and 41 to 43 is accumulated.

Main memory address pointers 71 and 72 indicate addresses of the main memory 6, and the main memory 6, register stacks 21 to 23, and register stack 4.
It is used when transferring between 1 and 43. It is then realized using a commercially available binary counter IC.

The control means 8 includes an internal mode designation means 1, register stacks 21 to 23 and 41 to 43, status display means 31 to 33 and 51 to 53, address designation pointers 20 and 40, a main memory device 6, and a main memory address pointer 71. and 72, and is realized by combining commercially available gate circuits and ICs such as flip-flops.

Next, before describing the stack mechanism in this embodiment in detail, the relationship between internal modes and register stacks will be described.

The internal mode specifying means 1 is a 1-bit flip-flop, and defines two states, "0" and "1".

When the internal mode specifying means 1 is in the 0 state, the register stacks 21 to 23 and the status display means 3
1 to 33, addressing pointer 20, and main memory address pointer 71 are operatively selected.

That is, register stacks 21 to 23 become valid and are used as objects of calculation. Data transfer between main memory device 6 and register stacks 21 to 23 is performed using main memory address pointer 71.

On the other hand, when the internal mode designation means 1 is in the "1" state, the register stacks 41 to 43, the status display means 51 to 53, the address designation pointer 40, and the main memory pointer 72 are selected to be operable. That is, register stacks 41 to 43 become valid and are used as computation targets. Data transfer between main memory device 6 and register stacks 41 to 43 is performed using main memory address pointer 72.

Next, regarding the stack mechanism in this embodiment, the case where the internal mode designation means 1 is "0" will be described in detail.

When data is set (called pushed) from register stack 21 to 23 by a stack operation, block 21 → block 22 →
The blocks are accumulated in the order of block 23 → block 21...
Conversely, when data on the register stack is discarded (called popped), block 23→
Block 22→block 21→block 23, etc. are processed in this order.

First, it is assumed that processing is started in a state in which data is not stored in all blocks of register stacks 21 to 23 (referred to as empty). At this point, the status display means 31 to 33 are at "0" and the address designation pointer 20 is at "11".

First, the push operation will be explained.

Processing starts, data from an arithmetic unit (not shown) passes through the signal line 10, and the internal mode specifying means 1
When selected by and sent via signal line 100, it is pushed to address 00 of register stack 21 (an address created by adding "1" to the current value of address designation pointer 31). When the push operation is continued, the address of register stack 21 is
Proceed as 01 → 10 → 11. Further, when a push operation is performed, the data moves to address 00 of the register stack 22. At this point, the status display means 31 is set to "1". Subsequently, when a push operation is performed on the register stack 22, the push operation advances from address 01 to 10 to 11, and when a push operation is performed again, the push operation moves to address 00 of the register stack 23. At this point, the status display means 32 is set to "1", and the register stacks 21 and 2 are set to "1".
2 are full and the status display means 31 and 32 are set to "1" to indicate a valid state, so that the block of register stack 21 is connected to signal line 1.
11, signal lines 200 and 210 to the main memory device 6 pointed to by the main memory address pointer 71, and are evicted. At this time, the address of the main memory address pointer 71 is updated by adding the number of evicted words. The status display means 31 is then reset to "0". The push operation continues, and after the register stack 23 becomes full and the address designation pointer 20 becomes "11", when another push operation is performed, the data is stored at address 00 of the register stack 21.

Then, the status display means 33 is set to "1" and the register stack 22 is ejected to the main memory 6. The push operation proceeds in the same manner.

Next, the pop operation will be explained.

Now, the push operation is progressing and the register stack 2 is
1 and 22 are full, the register is moved to the register stack 23, and the address designation pointer 20 is set to "01".
Suppose that it shows At this time, the register stack 21 has been ejected to the main memory 6, and the status display means 31 has become "0". If a pop operation is performed at this point, the data at address 01 of register stack 23 will be transferred to signal lines 123, 100 and 1.
0 to the arithmetic unit. At this time, the address designation pointer 20 changes from "01" to "00".
Furthermore, when a pop operation occurs, register stack 2
The data at address 00 of No. 3 is sent to the arithmetic unit. After that, when the pop operation continues, the process moves to the register stack 22, and the data at address 11 of the register stack 22 is sent. At this time, the status display means 32 changes from "1" to "0". Also, the block pointed to by the main memory address pointer 71 is fetched from the main memory 6 and set in the register stack 21, and the status display means 31 changes from "0" to "1". That is,
When one block of the register stack becomes empty due to a pop operation, it is set from the main memory 6 into the already empty register stack.
Of course, this operation is performed when data that has been evicted is stored in the main storage device 6.

The case where the internal mode specifying means 1 is "0" has been described above, but the process is performed in exactly the same way when the internal mode specifying means 1 is "1".

Control for performing the operations described above is achieved by control means 8. A detailed implementation method of the control means 8 will be omitted since a sequential circuit that performs the above operations can be easily implemented using ordinary gate circuits and flip-flops.

This embodiment has been described in detail above.

Although this embodiment deals with a case where there are two internal states, the present invention can also be applied to many more cases. Also, although the register stack is composed of three blocks, it may be composed of more blocks. Furthermore, during a push or pop operation, the blocks constituting the register stack are connected in a ring-like order; however, this is not limited to this method, and for example, a random method may be used.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. In the figure, reference numeral 1 is internal mode designation means, 21 to 23 and 41 to 43 are register stacks, 31 to 33 and 51 to 53 are status display means, 20 and 40 are address designation pointers, and 6
71 and 72 are main memory address pointers, and 8 is a control means, respectively.

Claims (1)

[Claims] 1. An internal mode specifying means that defines a plurality of internal states, and a plurality of blocks, each block consisting of a plurality of words, controlled in a first-in/first-out format, and a plurality of register registers corresponding to the internal states. a plurality of status display means indicating the valid state of each block of the plurality of register stacks; a plurality of addressing pointers indicating word addresses within the block; A main memory device that stores data in a last-in, first-out format; a plurality of main memory address pointers corresponding to the internal state indicating the latest valid data area of the main memory device; When there are no more non-empty blocks in the register stack, the oldest full block in the register stack is ejected to the location indicated by the main memory address pointer corresponding to the internal state in the main memory;
When an empty block occurs in the register stack as a result of a pop operation, an internal function is executed to fetch the latest block in the main memory from the main memory into the oldest empty block in the register stack. It is provided with a control means that performs sequential control between the register stack corresponding to the state and the main memory, and data necessary for arithmetic control for all internal states is always present in the register stack. A multi-stack device characterized in that it is controlled so as to