JPH024934B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to a so-called multiprocessor system consisting of a plurality of processors, particularly a processor unit capable of communicating data either synchronously or asynchronously. The present invention relates to a multiprocessor system equipped with a multiprocessor system.

[Prior art and its problems]

FIG. 1 is an explanatory diagram for explaining a data communication method between processors in a general multiprocessor system. In the figure, MUT is the master unit, SUT1 and SUT2 are slave units, and the master unit MUT is the processor PR.
In addition, the slave unit SUT has a processor.
A PR, a control circuit CT, and a common memory CM are provided, and these are connected to each other via a common bus BS. Data communication between processors in such systems is typically done synchronously or asynchronously through a common memory.

In other words, as shown in figure A, the synchronous type
Common memory CM from processor PR on slave side
The control circuit CT provides an interrupt trigger signal for synchronization to the processor PR on the master side by sending data to the processor PR. When the master side processor PR receives this trigger signal, it starts the interrupt processing service routine of the program and performs data exchange processing with the common memory CM. Note that the numbers marked with circles in FIG. 1A represent the activation order.

As shown in Figure B, in the asynchronous type, the master side processor PR reads and writes data to the common memory CM at appropriate times, and does not receive any synchronization commands to obtain this timing. This method does not impose any special restrictions on the startup order. Instead, when using the common memory CM, it is necessary to perform exclusive control by the control circuit CT in order to avoid confusion in data communication due to simultaneous use between processors. As a simple example, when the master processor attempts to use the common memory CM while the slave processor is using it, the control circuit CT generates a signal that causes the master processor to wait. This is done by focusing on the standby request terminal (corresponding to the READY terminal for some processors) that the processor has and its functions.

Usually, one of the above methods is adopted depending on the purpose of the system, but problems may occur in the following cases, for example.

B. If you want to respond flexibly to differences in the system of each unit, for example, in Figure 1, the master unit MUT and slave unit
Synchronized with SUT1 for high-speed processing.
On the other hand, it is better to make the unit more versatile, such as when using an asynchronous system to perform relatively slow processing between the master unit MUT and slave unit SUT2, which reduces the cost of hardware assembly and component mounting. It may be advantageous in terms of system operation, and it may also be reasonable from a system operation perspective.

(b) When distributing processing to each unit throughout the system, if there are uncertainties in conditions such as processing speed, processing content, timing, etc., or if the method cannot be clearly defined or is not desired, If the system configuration is fixed to one method, the system must be changed when a problem arises due to that method. In other words, it is not convenient if you want to respond flexibly.

[Purpose of the invention]

The present invention was made under these circumstances, and it is an object of the present invention to provide a highly flexible multiprocessor system with a simple and inexpensive configuration.

[Key points of the invention]

The present invention provides at least one of the processors constituting the multi-system with a control unit that sends either an interrupt signal or a standby signal, and a selection means that selects which one to send. Data communication can be performed either synchronously or asynchronously, allowing for a highly flexible system configuration.

[Embodiments of the invention]

FIG. 2 is a system configuration diagram showing an embodiment of the invention, and FIG. 3 is a configuration diagram showing a specific example of a control circuit according to the invention. That is, although the system configuration is almost the same as that shown in FIG. 1, the specific feature is that the control system CT used here is specifically configured as shown in FIG. 3. 3 shows one of the slave-side processors and the master-side processor among the processors in FIG. The basic concept of the operation control method is the same. In addition, although a control circuit is shown here that selects and controls the synchronous and asynchronous methods from processor 1 (slave side) to processor 2 (mask side), even if this relationship is reversed, This is similar.

In FIG. 3, 3 is a common memory used for data communication with processors 1 and 2;
is a selector, AB is an address bus, DB is a data bus, and CB is a control bus that sends read signals RD, write signals WT, etc. In addition, 6 grants the right to use the common memory 3 to either processor 1 or 2.
7 is a multiplexer that selects whether to use the processor 1 in a synchronous or asynchronous manner; 8 and 9 are address decoders; 10 to 1;
3 is a temporary memory (latch) element, 14 and 15 are data bus buffers, and 16 and 17 are this buffer 1.
18 is a control logic for reading and writing the common memory 3, _T1 is a processor 1,
The standby terminal _T2 is also an interrupt terminal.

The functions and operations will be explained below.

First, in order to perform data communication between processors in a synchronous manner, the processor 1 reads and writes data to the common memory 3, and also sends a certain code signal to the data bus DB by a program, for example. A predetermined pulse TG rising from a low (L) level to a high (H) level is generated using the latch element 11. The synchronizing signal SY for temporarily storing data in the latch element 11 is generated by giving a specific code to the decoder 8 according to a program and decoding this code. The above pulse TG is controlled by the control unit 6.
This signal is applied to the interrupt control terminal _T2 of the processor 2 via the processor 2, so that the processor 2 starts up the interrupt processing service routine. This interrupt service routine allows the processor 2 to read and write data to the common memory 3. At this time, the lower switch of the multiplexer 7 is selected by the output CS of the latch element 12 which operates in the same manner as the latch element 11 described above.

On the other hand, in the asynchronous method, the processor 2 reads and writes to the common memory 3 as appropriate, and the processor 1 uses the common memory 3 through this gap. When the processor 2 attempts to use the common memory 3 while the processor is running, the control unit 6 automatically issues a wait signal WAIT.
The processor 2 is placed in a standby state through a standby terminal _T1 . Note that if the processor 1 is released from standby at the same time as the use of the common memory ends, the control unit 6 performs control so that the processor 2 can use the common memory 3. Specifically, when the processor 1 uses the common memory 3, it issues a use request signal as a predetermined code according to the program, and causes the latch element 10 to latch it through the data bus DB, so that the latch signal RQ1 is “H”
During this period, even if the processor 2 issues the common memory 3 usage request signal RQ2, a WAIT request is made to the processor 2. Note that this is done in the same way even if the position of the processor is reversed. The latch signal RQ1 is obtained by decoding the address given by the program by the address decoder 8 and giving it to the latch element 10 as a synchronization signal, and also giving it predetermined data from the processor. It is. On the other hand, the request signal RQ2 from the processor 2 side is also obtained by passing a predetermined code issued by the program of the processor 2 to the data bus DB and latching it to the latch element 13, but the synchronization is the same. The address signal generated by the program is applied to the decoder 9 via the bus AB, and the decoding output is used for the processing. By doing so, the right to use the common memory 3 can be controlled so that only one processor has exclusive use of it.

The selection of the synchronous type or asynchronous type using the same control circuit is performed as follows.

That is, the control signal from the control unit 6 is given to the processor 2 via the multiplexer 7, and the selection of the switch in the multiplexer 7 is determined by the processor 1.
A predetermined code according to the program is applied to latch element 1.
2 and its output signal CS is used. For example, if there are only two lines, the standby request signal line and the interrupt signal line, the output from the latch element 12 is 1.
For example, when the bit is "L", the standby request signal line can be selected, while when it is "H", the interrupt signal line can be selected. Note that if two or more signal lines are required, this can be easily handled by simply increasing the number of output bits from the latch element 12.

FIG. 4 is a block diagram showing a modification for selecting a multiplexer. That is, in the above example, a predetermined code signal given by the program of the processor 1 is used, but an "H" or "L" signal can be latched by a manually operated switch SW as shown in FIG. A similar effect can be achieved by latching element 12. The timing signal for causing the latch element 12 to latch data can be a pulse signal obtained by decoding the signal on the address bus AB by the decoder 8, as in the case of FIG. Further, R shown in FIG. 4 is an input protection resistor, and VP5 is a power supply. thus,
It becomes possible to select whether data communication is to be performed synchronously or asynchronously by manual operation or by a program, thereby providing a highly flexible multiprocessor system. Note that if this is done using a program, it can be set when the program is started.

FIG. 5 is a block diagram showing a specific example of the control logic 18 of FIG. In FIG. 5, _S1 is a signal for enabling the common memory 3, and this is an output signal from the selector 5 driven by the output of the address decoded by the decoder 8. S ₂ is a write signal, NAND gate NA
and the inverter gate IN, the signal S ₁ ,
It is used to enable the memory 3 for a time specified by the logical sum of _S2 , whichever is longer, and is "L" when writing to the memory and "H" when reading.

FIG. 6 is a block diagram showing a specific example of the peripheral portion of the data buffer circuit. In the same figure, 14 and 15 are data bus buffers, OR1 and 2 are OR gates,
IN is an inverter gate, _S1 is a memory enable signal, _S2 is a write signal, and _S0 is a buffer switching signal, and this switching signal _S0 controls opening and closing of a gate (not shown) in the buffer. TE ₁ ,
_TE2 are enable terminals of buffers 14 and 15, respectively, and OR gates OR1 and OR2 which take the logical sum of the above-mentioned switching signal _S0 and the above-mentioned enable signal _S1 .
As a result, the buffers 14 and 15, which are, for example, known tri-state buffers, are turned on.
At this time, the switching signal _S0 is inverted by the inverter IN and is applied to the OR gate OR1 of the buffer 14, so when one buffer is enabled, the other buffer is disabled. Become. TD ₁ and TD ₂ are the terminals that determine the direction of the bus, and as mentioned above, they are used for the write signal.
For example, when this is "L", the direction of the bus is from _the processor side to the memory side, data is written, and it becomes "H".
In this case, reading is performed from the memory side to the processor side.

FIG. 7 is a block diagram showing a specific example of the control unit in FIG. 3. In Figure 7,
NA1-5 are NAND gates, IN1-3 are inverter gates, _S0 is a switching signal, RQ1 and 2 are output signals of latch elements 10 and 13, respectively, and _S3 and _S4 are output signals of decoders 8 and 9, respectively.

Here, for example, when the processor 1 wants to use the common memory 3, the request signal RQ1 is set to "H" level. At this time, if there is no request signal RQ2 from the processor 2 side and it is at the "L" level, the switching signal _S0 will be at the "L" level due to the logic configuration of the circuit, and the common memory 3 can be used by the processor 1. Become. In this state, the WAIT request signals for processors 1 and 2 are both at the "H" level. Next, when the processor 2 makes a request to use the common memory and the request signal RQ2 changes from "L" to "H", the switching signal _S0
The logic of is held "L", but since the enable signal _S4 from the processor 2 becomes "H", the output of the NAND gate NA2 becomes "L" and a WAIT request is applied to the processor 2. After that, when the processor 1 finishes using the common memory 3 and changes the request signal RQ1 from "H" to "L", the switching signal _S0 changes from "L" to "H", and this changes at the inverter IN1. Since it is set to “L” and given to NAND gate NA2, its output is “L” →
When the signal becomes "H", the WAIT request is canceled and the common memory 3 can be used by the processor 2. Note that an RS type flip-flop is formed by NAND gates NA3 and NA4 in the figure, and thereby the signals from the processors 1 and 2 are mutually exclusive switched. Note that the operation when processor 2 is using the common memory is the same as above, and in this state, processor 1
issues a usage request to processor 1.
A WAIT request will be issued.

〔Effect of the invention〕

According to the present invention, in a multiprocessor system in which data is exchanged between a plurality of processors via a common memory, the control is performed to enable data exchange between the processors in either a synchronous or asynchronous manner. By providing a control circuit to perform the method and a selection circuit to select the method,
Since it can be incorporated into multiple systems extremely easily, it has the advantage of being able to be flexibly handled regardless of differences in system objectives or synchronization methods.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining a data communication method between processors in a general multiprocessor system, FIG. 2 is a system configuration diagram showing an embodiment of the present invention, and FIG. 3 is a control circuit according to the present invention. 4 is a block diagram showing a modification of the multiplexer selection method. FIG. 5 is a block diagram showing a specific example of the control logic. FIG. 6 is a block diagram showing a specific example of the data bus buffer peripheral circuit. FIG. 7 is a block diagram showing a specific example of the control unit. Code explanation, 1, 2, PR...Processor, 3,
CM...Common memory, 4, 5...Selector, 6...Control unit, 7...Multiplexer, 8, 9
...Decoder, 10-13...Temporary storage (latch) element, 14, 15...Data bus buffer, 16-1
8 control logic, MUT...master unit, SUT
1, 2, N...Thrube unit, CT...Control circuit,
BS...Common bus, AB...Address bus, DB...Data bus, CB...Control bus, SW...Manual switch, IN, IN1~3...Inverter gate, NA, NA1~5...NAND gate, OR1,2
…orgate.

Claims (1)

[Claims] 1. In a multiprocessor system in which a plurality of processors, each having at least a standby request element and an interrupt request element, communicate data with each other via a common memory, at least one of the processors has a It controls by sending either an interrupt signal to perform data communication with the common memory in a synchronous manner or a standby request signal to perform data communication with the common memory in an asynchronous manner to its own or other processor. and a selection means for temporarily storing a predetermined signal and selecting only one of the interrupt or standby request signal from the control means based on the stored output, and the selection means synchronizes either one of the interrupts or the standby request signal. A multiprocessor system characterized by selecting a method for data communication.