JPH0250504B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor system including a plurality of processors and devices shared by these processors.

A multiprocessor system is a system in which multiple processors are used as devices (e.g., memory, process input/output devices, or peripherals such as typewriters, floppy disks, CRTs, etc.). This is a system configuration commonly adopted when sharing. Usually, a multiprocessor system with a bus configuration using a common bus is used as a high-speed and inexpensive method.

A conventional device of this type is shown in FIG. In FIG. 1, 11 to 1n are a plurality of n processors, 2 is a bus controller, 3 is a bus switching device, 4a to 4b are shared devices, 51 to 5n are local buses, and 6 is a common bus.

The bus controller 2 controls the common bus 6.

Next, the operation will be explained. In the configuration shown in FIG. 1, each processor 11 to 1n is connected to a shared device 4.
When attempting to use a, 4b, bus request signals REQ1 to REQn are sent to the bus controller 2. When the bus controller 2 receives this bus request signal, it issues a command to the bus switching device 3 to connect the common bus 6 to any one of the local buses 51 to 5n of the processor concerned. In this way, each of the processors 11-1n can occupy the shared devices 4a, 4b.

By the way, in a stand-alone system with one processor, when a device issues a request to the processor, an interrupt control method is generally used. In other words, when an emergency processing request is made to the processor on the device side (for example, for process input, timing is generated from an external signal, for peripheral equipment, etc., a status change signal such as job completion, data full, or data empty) is generated. ), set an interrupt number for each request factor, and send an interrupt to the processor to generate the corresponding interrupt.
Recognize the No. and execute the corresponding interrupt processing. Interrupts are performed on a device-by-device basis, and the number of interrupt numbers required is equal to the number of devices that require interrupts.

Now, in a multiprocessor system configuration as well, interrupt requests may be made from the shared device to the processor, and interrupt control is required. However, interrupt control in a multiprocessor system is much more complex than in the standalone system, and a request from a shared device must be interrupted by any corresponding processor. That is, when there are n shared devices that have interrupt requests, it is necessary to determine which of the n processors the m interrupt requests should be made to.

In the conventional system configuration, shared devices 4a, 4
There is no particular interrupt control from b, and the following methods were used to deal with it. That is, as a method for requesting an interrupt from the shared devices 4a and 4b, an interrupt data signal is provided through the common bus 6, and each processor (all processors) always periodically scans (scans by program) to detect the occurrence of an interrupt. A method of recognizing the device, or a method of using the same interrupt control method (dedicated device) as a standalone system by connecting the device that requires interrupts to the local bus of the interrupt destination processor instead of placing it as a shared device and treating it as a dedicated device. And so on.

Since the conventional multiprocessor system is configured as described above, the corresponding processors 11 to 1
When an interrupt request is made from the shared devices 4a, 4b to the shared device 4a, 4b, a drop in the interrupt response during program scan of each processor 11 to 1n, or when the device is exclusive to a specific processor, etc. processors cannot share the device;
Further, when a device is made exclusive, there is a drawback that the system becomes expensive because the number of exclusive devices is equal to the number of processors that require the device.

This invention was made to eliminate the drawbacks of the conventional ones as described above, and it recognizes shared interrupts and provides an interrupt number table to determine the processor to which the interrupt occurs. 1 shared device interrupt
It is an object of the present invention to provide a multiprocessor system that can be used for any number of processors, including one or more processors, is inexpensive, and does not reduce system efficiency.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, 7 is an interrupt number table. Interrupt requests from shared devices 4a and 4b are
It is sent to the bus controller 2' as an IT request signal ITR through the common bus 6, and when the bus controller 2' generates an IT recognition signal, the IT No. corresponding to the shared device is sent to the bus controller 2'. The bus controller 2' sends interrupt requests to the respective processors 11-1n as IT request signals ITR1-ITRn.

Further, FIG. 3 shows the interrupt number table of the shared device. Assuming that there are m shared devices that require interrupts, the interrupt numbers are IT0 to IT(m-1), and the memory is allocated one address (one word) at a time in response to each IT request signal. One bit is assigned in each word to indicate whether a processor is necessary or not. For example, in Figure 3, IT0 is processor 11, cpu.
1, IT2 is processor 1
3. The settings are as follows: interrupts are applied to two CPUs, cpu3, processor 1n, and cpun, at the same time.

FIG. 4 is a flow chart of the control operation of the bus controller 2' showing the operation of the present invention.

Next, the operation of the present invention will be explained with reference to FIGS. 3 and 5. First, all interrupts from the shared devices 4a, 4b on the common bus 6 and below are under the control of the bus controller 2'. shared device 4a,
When an IT request signal is generated from 4b to the common bus 6, the bus controller 2' receives the signal via the signal line connected to the common bus 6.
Recognize that an interrupt request has occurred. When the bus controller 2' receives the IT request signal, it sends an IT recognition signal to each shared device 4a, 4b via the signal line and the common bus 6. When the shared device that has generated the IT request signal among the shared devices receives the IT recognition signal from the bus controller 2', it sends the IT No. to the bus controller 2' via the common bus 6 and the data bus connected to this common bus 6. Send to. This IT No. corresponds to an arbitrary shared device, and the bus controller 2' recognizes from which shared device the interrupt request has been made. Next, the bus controller 2'
refers to the interrupt number table 7 in order to determine which processors 11 to 1n should receive an interrupt request. Since the interrupt number table stores interrupt destination processor numbers corresponding to IT numbers, the corresponding processor number (cpu number) is read out. Next, the bus controller 2' generates an IT request signal and an IT number corresponding to the interrupt factor to cause an interrupt to the corresponding processor. The number of processors is n, and the interrupt factor is
In the case of a factor requiring timing synchronization of 1n, it is necessary to sequentially interrupt n processors, and interrupt requests are made sequentially from processor 11 to processor 1n. That is, a maximum of n interrupt requests are made for one interrupt factor.

In the above embodiment, the interrupt number table 7 is under the control of the bus controller 2', and the interrupt destination processor number is set in advance.
Table 7 may be regarded as one of the shared devices below the common bus, and in such a case, the interrupt destination processor number can be arbitrarily set from the processor side at any time.

As described above, according to the present invention, since an interrupt number table is provided for interrupts from shared devices, each processor can receive interrupts from any shared device, and each shared device can Since it is now possible to interrupt any processor, the performance of the processor can be improved, devices can be shared, and an inexpensive and efficient system configuration can be constructed.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing a conventional multiprocessor system, FIG. 2 is a system diagram showing a multiprocessor system according to an embodiment of the present invention, and FIG. 3 is a system diagram showing interrupt destination processor numbers corresponding to shared devices. FIG. 4 is a flowchart showing the operation of the present invention. 11...1n...Processor, 2, 2'...Bus controller, 3...Bus switching device, 4a, 4b...Shared device, 51, 5n...Local bus, 6...Common bus, 7...Interrupt No. table. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. A plurality of processors each having a local bus, a common bus that can be shared by the processors, and a plurality of shared devices that are connected to the common bus and can be shared by the processors; A bus controller connected to each of the above processors and the common bus to control the common bus and control interrupt requests from the shared device; a bus switching device that selects any one of the local buses and connects it to the common bus according to the output; and a bus switching device that selects any one of the local buses and connects it to the common bus; each processor has a function of transmitting a bus request signal to the bus controller when using the shared device, and the bus controller The bus switching device has a function of receiving a request signal and issuing a command to the bus switching device to connect one of the local buses of the processor to the common bus, and the bus switching device receives the command. It has a function to receive and connect one of the local buses of the processor to the common bus, and the shared device connects the common bus with one of the local buses of the processor.
The bus controller has a function of sending the IT request signal to the bus controller, and the bus controller receives the IT request signal, recognizes the interrupt cause, refers to the interrupt number table, and sends the corresponding arbitrary number of processors. It has a function to send an IT request signal corresponding to the above-mentioned interrupt request. A multiprocessor system characterized by: