JPH025055B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current switch circuit using field effect transistors, and particularly to an accurate and high-speed current switch circuit for analog current that requires high precision.

FIG. 1 shows a conventional example of a differential current switch circuit. 2 is a current source, and the current of this current source 2 is output from the output terminal 7 or 8 depending on the control signal sent to the control terminal 6 by the current switch 1, and the terminal that is not in the output state is turned off. The current switch 1 is composed of field effect transistors (hereinafter abbreviated as FETs) 9 and 10 whose sources are commonly connected, and the gate of the common gate FET 9 is connected to a voltage source 3 (this voltage (The source may be any bias voltage generating circuit.) It is biased by this output, and the source common connection point is connected to the output of the current source 2 via the terminal 4. The gate of the switch FET 10 is connected to the control terminal 6, the drain of the common gate FET 9 is connected to the first output terminal 7, and the drain of the switch FET 10 is connected to the second output terminal 8. Since the gate voltage of the FET 10 has a large amplitude and a highly accurate output current cannot be obtained from this second output terminal 8, it is normally connected to an arbitrary current absorbing section such as a power supply terminal. However, if particularly high precision is not required, this conventional example operates as a current switch in which complementary output currents are obtained from terminals 7 and 8 depending on a pulsed control signal supplied to terminal 6.

The level of the control signal supplied to terminal 6 is low;
FET10 turns off, FET9 turns on, and output terminal 7
In the "closed state" of the switch where a current output is obtained from
Assuming that it is composed of FETs, the equivalent circuit is shown in Figure 1B, as is well known to those skilled in the art.
It can be approximated by the schematic circuit shown in . That is, FET9 is represented as a parallel circuit of current source i ₉ and output impedance r ₀ , and current source 2 is composed of a FET that is almost equivalent to FET9 as described above, so this is a parallel circuit with current source i ₉ and output impedance r 0. Represented by a parallel circuit with output impedance r ₀ , FET 9 and current source 2
The entire equivalent circuit of is shown by the series connection of these two parallel circuits.

Let us now consider the amount of change △I _{7 in the output current I 7 that} occurs when the voltage V ₇ at the output terminal 7 changes by △V ₇ in the conventional example shown in FIG. It is clear that if the voltage at terminal 7 changes by ΔV ₇ , the voltage at terminal ₄ V ₄ changes by ΔV 4. Assuming that the gate bias of FET9 supplied from voltage source 3 is constant, the voltage at terminal 4 is
A positive change in V ₄ causes the gate-source voltage of FET 9 to decrease and the current in current source i ₉ to decrease, so the current in current source i ₉ is
It changes by gm・(−△V ₄ ). The amount of change in the output current I ₇ △I ₇ is the same as the amount of change in the current flowing in the parallel circuit of the current source i ₉ and the output impedance r ₀ , so △I ₇ = (△V ₇ − △V ₄ ) /r ₀ +gm・(−△V ₄ )=
(△V ₇ −△V ₄ )/r ₀ −gm・△V ₄ (1). The amount of change in the output current ΔI ₇ is also the same as the amount of change in the current flowing through the parallel circuit of the current source i ₈ and the output impedance r ₀ . FET that constitutes current source 2
Since the gate bias of is constant and its source is connected to ground, the current in current source i ₈ does not substantially change. Therefore, the amount of current change △I ₇ can also be expressed as △I ₇ = △V ₄ /r ₀ (2). Obtaining △I ₄ from equation (2) and substituting it into equation (1), △I ₇ = 1/(2+gm・r ₀ ) r ₀・△V ₇ 1/(gm・r ₀ ) r ₀・△V ₇ (3). That is, in the conventional example shown in FIG. 1, when the voltage at the output terminal 7 changes by ΔV ₇ , the change in output current ΔI ₇ becomes 1/(gm·r ₀ )r ₀ . As a result of the experiment, the fluctuation rate of the output current with respect to the voltage amplitude (fluctuation) at the terminal 7 was 0.006%/V. The voltage amplitude of terminal 7 is
When allowed up to 10V, the variation in current _I7 is 0.06%, and this conventional circuit cannot be applied to a high-precision D/A converter of 10 bits or more. 10 bit D/A
The converter allows current value fluctuations of approximately 0.05% or less.

From equation (3), the output conductance of this circuit is △I ₇ / △V ₇ = 1/(gm・r ₀ ) r ₀ (4), and the output impedance is △V ₇ / △I ₇ = (gm・r ₀ ) r ₀ (5).

Furthermore, this conventional example requires a bias circuit as a voltage source 3 that generates a predetermined bias voltage from the power supply voltage in addition to the power supply voltage, and this bias circuit may be an independent voltage source supplied from the outside. Alternatively, the bias voltage supply circuit may be formed inside the integrated circuit, but in any case, additional circuit means are required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a current switch circuit that generates a stabilized output current by suppressing fluctuations in output current due to voltage fluctuations at a current output terminal in a switch-on state.

Another object of the present invention is to achieve a high performance current switch circuit without the need for an additional bias voltage source, and which is suitable for construction in a monolithic integrated circuit using field effect transistors. Our goal is to provide the following.

The current switch circuit according to the present invention includes first and second potential terminals, a circuit node, a constant current source connected between the first potential terminal and the circuit node and generating a constant current, a current output terminal, and the a first field effect transistor connected between a circuit node and the current output terminal; a first field effect transistor connected between the first potential terminal and a gate of the first field effect transistor and connected to the circuit node; a second field effect transistor having a gate, a control signal input terminal, a second field effect transistor having a gate connected between the first potential terminal and the gate of the first field effect transistor and connected to the control signal input terminal; In the field effect transistor of No. 3, when the control signal input terminal assumes a first voltage level, the field effect transistor becomes conductive, causing the first field effect transistor to be cut off, and the control signal input terminal enters a second voltage level. a third field effect transistor that is in a cut-off state when assuming a voltage level; and a gate connected between the second potential terminal and the gate of the first field effect transistor and connected to the circuit node. a fourth transistor of a different conductivity type or a depletion type fourth transistor connected between the second potential terminal and the gate of the first field effect transistor;
, and when the control signal input terminal assumes the second voltage level, the second field effect transistor and the fourth field effect transistor input the circuit node, and the first field effect transistor It is characterized by acting as an inverting amplifier that supplies the output to the gate of the effect transistor.

Since the configuration consisting of the second, third, and fourth transistors described above is equivalent to a gate circuit normally used in logic integrated circuits, such a gate circuit can be used in a high-precision current switch, and has a large It is easy to apply to large-scale integrated circuits (LSI), etc.
Furthermore, this current switch circuit has almost ideal off-characteristics in the open state, while in the closed state, the inverting amplifier and feedback loop consisting of the first transistor, second and fourth transistors operate. This stabilizes the output current, making it possible to create highly accurate monolithic IC analog circuits, such as digital-to-analog converters.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows a current switch circuit according to one embodiment of the present invention. The circuit is composed of a constant current source 2 and a switch circuit 20, and the constant current source 2 is connected between the ground and a node 44 of the circuit 20. The switch circuit 20 has a complementary MOS (CMOS) configuration, and in addition to the node 44, it has a current output terminal 47, a control signal input terminal 46, and first and second potential terminals 6.
2 and 61. The first potential terminal 62 is grounded, and the second potential terminal 61 is supplied with a power supply voltage. The drain 24 of the first N-channel FET 21 is connected between the current output terminal 47 and the node 44.
One source 22 current path is connected between the gates 23 and 31 of the FET 21 and the first potential terminal 62.
N-channel FET53 is connected. FET5
The gate 32 of No. 3 is connected to the node 44 (the source 22 of the FET 21). FET gate 23,
A third N-channel FET 54 is also connected between 31 and the first potential terminal 62, and its gate 33
is connected to the control signal input terminal 6. FET
Between the gates 23 and 31 of 21 and the second potential terminal 61, there is a P channel FET as a circuit means.
55 and 56 are connected in series, FET55
The gate of FET 56 is connected to terminal 46, and the gate of FET 56 is connected to node 44 (gate 32 of FET 53).

Now, when the control signal to the terminal 46 takes a high level as the first voltage level, the FET 55 is turned off and the FET 54 is turned on, so regardless of the level of the node 44, the gate 2 of the FET 21 is
3 and 31 are at low level, and FET 21 is turned off. As a result, the current output terminal 47 is turned off and no current output is obtained. On the other hand, when the control signal to the terminal 46 takes a low level as the second voltage level, the FET 55 is turned on and the FET 54 is turned off.
Therefore, the level of FET 21 to gates 23 and 31 is controlled by the level of node 44 and FETs 53 and 56. If the FET 21 is in the cut-off state, its source 22, that is, the node 44 (gate 32 of the FET 53) is at a low level, so the FET 56 is turned on, the FET 53 is turned off, and the gates 23 and 31 of the FET 23 are set at a high level. Therefore, FET 21 becomes conductive, and the level at node 44 rises. This level increase causes the levels of the gates 23 and 31 of the FET 21 to decrease due to the action of the FETs 53 and 56. In this way, when the control signal input terminal 46 is at a low level, both the FETs 53 and 56 are conductive, and the node 44 is used as an input, and in response to a voltage change at the same input, the change is a change in the reaction direction. Then, the output that amplifies the change is sent to the gate 23 of FET 21.
It works as an inverting amplifier that outputs Through the feedback loop between the inverting amplifier and FET21, FET2
The gate of 1 is stabilized at a certain voltage level, which is the level that makes it conductive. Therefore, a constant current can be obtained from the current output terminal 47 that is stabilized against voltage changes to the terminal.

FIG. 3 shows another embodiment of the invention. Components that are the same as those in FIG. 2 are indicated by the same numbers, and their explanations will be omitted. In this embodiment, an enhancement depletion type NMOS (E/D NMOS) configuration is used. Therefore, the gate 23 of FET21,
The circuit means provided between 31 and the second potential terminal 61 is composed of a depletion FET 57. In addition, current source 2 is also a depression FET.
It consists of 50.

The circuit operation of this embodiment is the same as that of FIG. 2, but since the FET 57 is of the depression type, the second potential terminal 61 is connected to the control signal input terminal 46 both when the control signal input terminal 46 is at a high level and when it is at a low level. and FET21
In the embodiment shown in FIG. 2, a current path is formed between the gates 23 and 31 of the second potential terminal 61 when the control signal input terminal 46 is at a low level.
A current path is formed between the gates 23 and 31 of the FET 21 and the gates 23 and 31 of the FET 21.

The circuit portion 30 of FETs 53 to 56 in FIG. 2 has a CMOS configuration, as is well known.
This is the NOR gate itself, and the circuit portion of FETs 53, 54 and 57 in Figure 3 is also 30.
is also a NOR gate with an E/D NMOS configuration. Therefore, the circuits of FIGS. 2 and 3 are constructed using the constant current source 2 and the FET as shown in FIG.
21 and a NOR gate 30.
When terminal 46 is at a high level, the output of NOR gate 30 is at a low level, cutting off FET 21, while when terminal 46 is at a low level,
NOR gate 30 can be viewed as an inverter. However, as described above, it does not act as an inverter for digital logic operation, but rather acts as an inverting amplifier to stabilize the voltage level at the gate 23 of the FET 21.

FIG. 4B shows still another embodiment of the present invention.
In this example, a P-channel FET is used as the first
It is used as FET121, and its source 12
2 (node 144) is the first node of the NAND gate 130.
connected to input 132, gate 123 is NAND
It is connected to the output 131 of the gate 130.
A second input 133 of NAND gate 130 is connected to control signal input terminal 146 . terminal 14
6 is at a low level, the output of the NAND gate 130 is at a high level, and the FET 121 is cut off. On the other hand, when terminal 146 is at high level,
As is clear from the internal transistor circuit configuration, the NAND gate 130 acts as an inverting amplifier with the node 144 as an input and the gate 123 of the FET 121 as an output. Outputting current.

As explained above, the current switch of the present invention is constructed using a simple logic gate as a control circuit, which has conventionally been implemented as a logic integrated circuit, and is a circuit means suitable for a monolithic integrated circuit. Furthermore, since feedback bypass is performed, an additional bias circuit for creating a predetermined bias voltage from the power supply voltage is not required.

Furthermore, a major feature of the present invention is that when the FET 21 is in the on state, the output impedance looking into the current switch circuit of the present invention from the terminal 47 is extremely high, which is an improvement of about one order of magnitude compared to the conventional example described above. It is a fact that In other words, the change in the output current with respect to the voltage change at the terminal 47 is extremely small compared to the conventional example. That is, assuming that the current source 2 is constituted by an FET equivalent to the FET 21 as described above, the equivalent circuit when the FET 21 is in a conductive state is shown in FIG. 1B. However, FET21
The gate of is biased not by a fixed bias voltage but by a NOR gate 30 as an inverting amplifier. Therefore, the gain of the inverting amplifier is set to -μ (>1), and the potential change at the output terminal 47 is △V ₀
If the potential change at the terminal 44 based on the equation is △V ₁ , then
The current change of the current source _i9 is (-μ)·gm·( _-V1 ). gm is the transconductance of FET21. Therefore, in the circuit according to the present invention, the change in output current △I ₀ due to the change in potential △V ₀ is expressed by equation (1),
It can be expressed by the following equations (6) and (7) in the same way as equation (2).

△I ₀ = (△V ₀ −△V ₁ )/r ₀ + (-μ)・gm・(-
△V ₁ ) (6) △I ₀ = △V ₁ /r ₀ (7) Calculating △V ₁ from equation (7) and substituting it into equation (6), △I ₀ = 1/(2−μ・gm・r ₀ ) r ₀・△V ₀ 1/−μ(gm・r ₀ ) r ₀・△V ₀ (8). In other words, the voltage change at the output terminal 47 △
The change in output current △I ₀ with respect to V ₀ is 1/μ (gm・
r ₀ ) r ₀ , and as is clear from equation (3), the change in output current is extremely small compared to the conventional circuit due to the effect of the inverting amplifier by the NOR gate 30.
It has been stabilized.

From equation (8), the output conductance △I ₀ /△V ₀ and the output impedance (reciprocal of the output conductance) △V ₀ /△I ₀ in the on state of this current switch are respectively △I ₀ /△V ₀ = 1/-μ・(gm・r ₀ )・r ₀ (9) △V ₀ /△I ₀ = −μ・(gm・r ₀ )・r ₀ (10). Therefore, the output impedance is approximately μ
It is twice as much improved as the conventional circuit. That is,
The higher the output impedance, the more the current source exhibits constant current source characteristics that generate a constant output current regardless of voltage changes at the current output terminal.The circuit of the present invention exhibits constant current characteristics when the current switch is on. The output current is stabilized.

Gain μ of inverting amplifier by NOR gate 30
It is easy to increase the amount by more than 10 times.

In experiments conducted by the inventor, the output voltage
Output current variation is 0.00375 for 10V amplitude at V ₀
%, and the fluctuation rate was 0.000375%/V. This value has been improved by about 16 times compared to the conventional example. The least bit (LSB) value in a 12-bit D/A converter is approximately 0.025% of the full scale value.
Even if an error equivalent to 1LSB is allowed, the output amplitude in the conventional example is suppressed to about 4V, but when the current switch of the present invention is used, an output amplitude of about 64V is allowed.

FIG. 5 shows another embodiment of the current switch circuit of the present invention, in which the control circuit is composed of a composite AND NOR circuit. When the level of the first control terminal 241 is at a high level, the gate 230
The output 231 of will be at a low level, and the FET 221 will be cut off. Therefore, the terminal 241 operates as an inhibit input terminal. When the level of the second terminal 242 is low while the level of the terminal 241 is low and there is no inhibition state, the gate 230 inputs the terminal 232 regardless of the level of the third terminal 246.
It operates as an inverting amplifier that outputs terminal 231.
The FET 221 is feedback biased and turned on.
That is, the terminal 242 operates as a forced drive input terminal. When the first input terminal 241 is at a low level and the second input terminal 242 is at a high level, the FET 22
1 is controlled on and off. Therefore, the terminal 246 operates as a bit input terminal (for example, when applied to a D/A converter, etc.).

FIG. 6 shows another embodiment of the invention configured to obtain complementary outputs. When the level of the control terminal 346 is at a high level, the output 331 of the NOR gate 330 becomes a low level and the FET 321 is cut off. On the other hand, the NOR gate 335 to which the low level signal inverted by the inverter 325 is applied to the terminal 338 operates as an inverting amplifier, and the FET 325
is feedback biased and becomes an on state, so that the terminal 348 becomes an output state and the terminal 347 becomes an off state. On the other hand, when the level of the control terminal 346 is at a low level, the NOR gate 330 operates as an inverting amplifier, and the FET 321 is feedback biased and turned on. On the other hand, a high level signal inverted by inverter 325 is applied to terminal 338.
The output of gate 335 becomes low level and FET 32
2 is cut off, so that terminal 348 is in the off state and terminal 347 is in the output state, making complementary output operation possible with this embodiment. In this way, even in this embodiment, which enables complementary outputs, no external bias circuit is required, and the configuration uses simple logic gates, and the output impedance expected from the terminals in the on state is Compared to the conventional example, an improvement of more than one order of magnitude is easily possible.

As explained above, the current switch circuit of the present invention has a simple configuration suitable for monolithic integrated circuits, and has higher performance than conventional switches. This will greatly contribute to the development of D/A conversion circuits and the like.

[Brief explanation of drawings]

1A and 1B are diagrams showing a conventional current switch circuit and an equivalent circuit diagram of a current source, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a diagram showing another embodiment of the present invention. FIG. 4A is a circuit diagram showing the configuration of FIGS. 2 and 3 using a gate circuit, and FIG. 4B is a circuit diagram showing still another embodiment of the present invention using a gate circuit. The illustrated circuit diagrams, FIG. 5 and FIG. 6, are respectively circuit diagrams showing further embodiments of the present invention using gate circuits. 2...Current source, 3...External bias source, 20...
...Current switch of the present invention.

Claims (1)

[Scope of Claims] 1. A first and second potential terminal, a circuit node, a constant current source connected between the first potential terminal and the circuit node and generating a constant current, a current output terminal, and the circuit. a first field effect transistor connected between the node and the current output terminal; a gate connected between the first potential terminal and the gate of the first field effect transistor and connected to the circuit node; a second field effect transistor having a control signal input terminal; a third field effect transistor having a gate connected between the first potential terminal and the gate of the first field effect transistor and connected to the control signal input terminal; a field effect transistor, wherein when the control signal input terminal assumes a first voltage level, it becomes conductive, causing the first field effect transistor to be cut off; and when the control signal input terminal assumes a second voltage level. a third field effect transistor that is in a cutoff state when taking a level, and a gate connected between the second potential terminal and the gate of the first field effect transistor and connected to the circuit node; a fourth field effect transistor having a conductivity type opposite to that of the second field effect transistor, and when the control signal input terminal takes the second voltage level, the second field effect transistor 4. A current switch circuit characterized in that it functions as an inverting amplifier which takes the circuit node as an input and supplies an output to the gate of the first field effect transistor together with the fourth field effect transistor. 2 first and second potential terminals, a circuit node, a constant current source that is connected between the first potential terminal and the circuit node and generates a constant current, a current output terminal, the circuit node and the current output terminal a second field effect transistor having a gate connected between the first potential terminal and the gate of the first field effect transistor and connected to the circuit node; an effect transistor, a third field effect transistor having a control signal input terminal, a gate connected between the first potential terminal and the gate of the first field effect transistor and connected to the control signal input terminal; When the control signal input terminal assumes a first voltage level, the first field effect transistor becomes conductive and is cut off, and when the control signal input terminal assumes a second voltage level, the first field effect transistor is cut off. a fourth field effect transistor of depletion type connected between the second potential terminal and the gate of the first field effect transistor; When the terminal takes the second voltage level, the second
A current switch circuit characterized in that the field effect transistor functions together with the fourth field effect transistor as an inverting amplifier which receives the circuit node as an input and supplies an output to the gate of the first field effect transistor.