JPH0251259B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and particularly to the structure of a high impurity concentration region that serves as a channel stopper in a semiconductor device such as an insulated gate field effect semiconductor device. In integrated circuits using insulated gate field effect devices such as MOS devices, impurity diffusion regions are often formed as channel stoppers for electrical insulation between devices, which is especially essential in N-channel MOS integrated circuits. It has become a condition. This channel stopper is formed by diffusing an impurity having the same conductivity type as the substrate impurity. The higher the impurity concentration, the better the effect as a channel stopper, but if the impurity concentration is too high in the area where this impurity region overlaps the source or drain of the MOS transistor, the junction breakdown voltage will decrease, so the range of this impurity concentration is naturally limited. It's coming.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a channel stopper structure that allows the channel stopper to perform its original function without reducing the junction breakdown voltage.

The present invention is characterized by a thick insulating film provided on the main surface of a semiconductor substrate of one conductivity type, and a channel stopper of one conductivity type with a higher impurity concentration than the semiconductor substrate provided under the thick insulating film. Therefore, in a semiconductor device that performs isolation between element regions, the channel stopper of one conductivity type is provided in the element region and the first region in contact with the region of the opposite conductivity type is separated from the region of the opposite conductivity type. The semiconductor device has a second region provided in the semiconductor device, and the impurity concentration of the second region is higher than the impurity concentration of the first region.

In this way, since the portion of the channel stopper that contacts the region of the opposite conductivity type is the first region, a reduction in the junction breakdown voltage can be prevented. Furthermore, since the high concentration required for isolation between elements can be achieved in the second region, the original function of the channel stopper, which is insulation between elements, is not affected in any way. By using not only the second region but also the first region, isolation between elements can be more reliably achieved.

In particular, an N-channel insulated gate field effect transistor can be used as the element, and in this case, the regions of opposite conductivity type become N-type source and drain regions.

Next, embodiments of the present invention will be described.

First, as shown in Figure 1, the impurity concentration is 3×10 ¹⁵ /
A silicon oxide film 2 is deposited on a P-type silicon substrate 1 of ^cm3 .
500~2000Å and silicon nitride film 3 700~3000Å
Å is selectively provided, the silicon oxide film 2 and the silicon nitride film 3 are etched as masks, and P ⁺ boron is diffused at a relatively low concentration at 770°C to 800°C ^.
After forming a boron diffusion layer 10, P ⁺ boron oxidation is performed at a temperature of 900°C to 1140°C to grow a silicon oxide film 11 to a suitable thickness. This P ⁺ boron diffusion layer 10 becomes the first region of the channel stopper. Next, for example, a photoresist is provided so that only a part of the surface of the silicon oxide film 11 is exposed, and a part of the silicon oxide film 11 is removed.As shown in ^FIG . A P ⁺ layer 5 is formed within the P ⁺ layer 10 . This P ⁺ layer 5
becomes the second region of the channel stopper. Then, using the silicon nitride film 3 as a mask, a thick oxide film 6 partially buried in the semiconductor substrate is formed or not, and the substrate surface between the P ⁺ layers 10, that is, the element covered with the oxide film 2 in FIG. After removing the silicon oxide film 2 and silicon nitride film 3 from the region,
An N-type source 7, drain 8, thin gate insulating film, and gate electrode 9' of the MOS transistor are formed. Also, source and drain electrodes 9 are formed. As a result, as shown in FIG. 2, there is a P ⁺ channel stopper layer 10 with a not very high concentration in contact with the source 7 or drain 8, and a P + channel stopper layer 10 located within this layer 10 but not in contact with the source 7 or drain 8. A MOS integrated circuit having a high concentration P ⁺ channel stopper layer 5 between elements is constructed. here
Although the concentration of the P ⁺ layer 10 is determined in consideration of the junction breakdown voltage of the source 7 or the drain 8, the concentration of the P ⁺ layer 5 can be made high regardless of this.

Although the present invention has been described above for N channels, it is clear that similar effects can be obtained for P channels as well. In the embodiment of the present invention, a silicon nitride film is used as the oxidation-resistant film, but other materials such as alumina film, tantalum, molybdenum, etc. can also be used. Further, the channel stopper formed according to the present invention is not limited to diffusion, and may be formed by other means such as ion implantation.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views showing embodiments of the present invention. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, 3 is an oxidation-resistant film, 5 is an impurity diffusion region having the same conductivity type as the substrate, 6 is a thick silicon oxide film, 7 and 8 are source and drain regions, 9 ，
Reference numeral 9' indicates a source, drain electrode, and gate electrode made of a wiring aluminum layer, 10 an impurity diffusion region having the same conductivity as the substrate and having a lower concentration than 5, and 11 a silicon oxide film.

Claims (1)

[Claims] 1. An insulating film provided in a predetermined region of the main surface of a semiconductor substrate of one conductivity type, a high concentration impurity region of an opposite conductivity type provided in an element region other than the region where the insulating film is formed, and the opposite conductivity type. a first region of one conductivity type that is in contact with the high concentration impurity region, is provided under the insulating film, and has a higher impurity concentration than the semiconductor substrate;
A second region of one conductivity type, which is provided under the insulating film so as to be spaced apart from the high concentration impurity region of the opposite conductivity type and partially overlap with the first region, and has a higher impurity concentration than the first region. A semiconductor device characterized by having a region.