JPH0252458B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparison circuit, and more particularly to a frequency comparison circuit that compares a first signal whose frequency changes from moment to moment with a second signal which has a constant frequency, and outputs the height of the frequency. Regarding.

Conventionally, when detecting which frequency a signal that changes between two frequencies is operating over time, it is compared with a reference signal that has a constant frequency approximately halfway between the two frequencies. It is detected based on the comparison results. The circuit that has this purpose is a frequency comparison circuit, but when implementing this circuit in an integrated circuit, conventional circuits have the problem of having a large number of elements and occupying a large area, and because of the static operation, the through current between the power supplies is high. In many cases, there is a problem in that current consumption increases significantly as the frequency increases.

An example of a conventional frequency comparison circuit will be explained with reference to FIG.

The frequency comparison circuit shown in Fig. 1 has six non-OR gates (hereinafter abbreviated as NOR gates) R ₁ ,
R ₂ , R ₃ , R ₄ , R ₅ , R ₆ and two AND-non-OR gates (hereinafter abbreviated as ANOR gates)
AR ₁ , AR ₂ and NOR gates R ₁ , R ₂ , R ₅ ,
R ₆ has two inputs, NOR gates R ₃ , R ₄ and
ANOR gates AR ₁ and AR ₂ have three inputs. 1st
The input terminal I ₁ of is the first input on the AND side of the first input of NOR gates R ₁ and R ₃ and the ANOR gate AR ₁ .
connected to the input. The first inputs on the AND side of the NOR gates R ₂ , R ₄ and the ANOR gate AR ₂ are connected to the second input terminal I ₂ . The outputs of the NOR gates R ₁ , R ₂ are connected to the second inputs of the other NOR gate, and to the second inputs of the NOR gates R ₃ , R ₄ . The respective third inputs of NOR gates R ₃ and R ₄ are ANOR gates AR ₁ ,
Second input on AND side of AR ₂ and NOR gate
are connected to the first inputs of R ₅ and R ₆ , respectively, and
They are connected to the outputs of NOR gates R ₆ and R ₅ , respectively. Each output of NOR gate R ₃ and R ₄ is a NOR gate
They are connected to the second inputs of R ₅ and R ₆ , respectively.
Each output of the ANOR gates AR ₁ and AR ₂ is connected to a third input on the non-OR side of the other ANOR gate. The output of the ANOR gate AR ₁ is further connected to the output terminal O ₁ .

FIGS. 2 and 3 show examples of configurations of a three-input NOR gate (R ₃ , R ₄ ) and an ANOR gate (AR ₁ , AR ₂ ), respectively.

The 3-input NOR gate is a P-type insulated gate field effect transistor (hereinafter referred to as MOSFET) P ₁₀ ,
P ₂₀ , P ₃₀ and N-type MOSFETs N ₁₀ , N ₂₀ , N ₃₀ . The N-type MOSFETs N ₁₀ , N ₂₀ , and N ₃₀ are connected in parallel with each other between one end of the power supply V _SS and the output end O ₁₀ , and the P-type MOSFETs P ₁₀ , P ₂₀ , and P ₃₀ are connected to the other end of the power supply V _{DD .} and the output terminal _O10 are connected in series with each other. The gates of the P-type MOSFETs P ₁₀ , P ₂₀ , P ₃₀ are connected to the first, second, and third inputs I ₁₀ , I ₂₀ , and I _30, respectively, and the gates of the N-type MOSFETs N ₁₀ ,
It is connected to each gate of N ₂₀ and N ₃₀ , respectively.

Regarding the 2-input NOR gate (R ₁ , R ₂ , R ₅ , R ₆ ), in Fig. 2, for example, P-type MOSFET
Since this configuration excludes P ₃₀ and N-type MOSFET N ₃₀ , detailed explanation thereof will be omitted.

The ANOR gate in Figure 3 is a P-type MOSFET
P ₁₀₀ , P ₂₀₀ , P ₃₀₀ and N-type MOSFET N ₁₀₀ , N ₂₀₀ ,
Equipped with _N300 . N-type MOSFETs N ₁₀₀ and N ₂₀₀ have one end of the power supply V _SS and the output end common to Figure 2.
Connected in series with O ₁₀₀ . Power supply terminal V _SS
There is also an N-type MOSFET between and the output terminal _O100 .
N ₃₀₀ is connected. P-type MOSFET P ₁₀₀ ,
P ₂₀₀ are connected in parallel with each other, their common sources are connected to the other end of the power supply V _DD , and there is a P type connection between their common drains and the output terminal O ₁₀₀ .
MOSFET P ₃₀₀ is connected. P type
Each gate of MOSFET P ₁₀₀ , P ₂₀₀ , P ₃₀₀ is input terminal
connected to I ₁₀₀ , I ₂₀₀ , I ₃₀₀ respectively, and further connected to N
They are connected to the gates of type MOSFETs N ₁₀₀ , N ₂₀₀ , and N ₃₀₀ , respectively.

As is clear from the above explanation, the frequency comparison circuit shown in FIG. 1 is composed of 40 MOSFETs and is quite complex.

Next, the operation of the conventional example shown in FIG. 1 will be explained. Here, each of the first input terminals _I1 is supplied with an input signal that changes over time between two types of frequencies, and a reference signal having a constant frequency intermediate between the two frequencies of the input signal is supplied. Second input terminal
_I2 is supplied. The input and reference signals I ₁ , I ₂ are
Both pulse waves have positive pulses.

Taking as an example the process of detecting that the input signal has changed from higher to lower frequency than the reference signal, Figure 4 shows the first diagram in that case.
Signals of each part of the circuit shown in the figure are shown. The output terminal _O1 is initially at the V _SS level.

First, when the reference signal I ₂ reaches V _DD level, NOR
The output J ₂ of gate R ₂ goes to V _SS level and then
The output _J1 of NOR gate _R1 becomes _VDD level. Next, when the reference signal I ₂ goes to the V _SS level, the output J ₄ of the NOR gate R ₄ goes to the V _DD level, and then the output J ₆ of the NOR gate R ₆ goes to the V _SS level. In addition, the output J ₅ of NOR gate R ₅ becomes V _DD level, and further NOR
Output J ₄ of gate R ₄ becomes V _SS level. input signal
When I ₁ goes to V _DD level, the output J ₁ of NOR gate R ₁
goes to V _SS level and then the output of NOR gate R ₂
J ₂ becomes V _DD level. When the input signal I ₁ goes to V _SS level, the output J ₃ of NOR gate R ₃ goes to V _DD level, then the output J ₅ of NOR gate R ₅ goes to V SS level, and the output of NOR gate R ₆ goes to V _SS level. J ₆ goes to V _DD level, and furthermore, the output J ₃ of NOR gate R ₃ goes to V _SS level. In other words, when the input and reference signals I ₁ and I ₂ alternately repeat changes in V _SS and V _DD levels, NOR
The outputs J ₅ and J ₆ of the gates R ₅ and R ₆ only repeatedly invert their voltage levels. Now the reference signal I ₂ is V _SS
After changing the level of →V _DD →V _SS , the input signal I ₁
If there is a further change in V _SS → V _DD level before the level change in , the output J ₇ of ANOR gate AR ₂ will change to V _SS
Therefore, the output terminal O becomes the V _DD level. Therefore, it is detected that the frequency of the input signal supplied to the input terminal _I1 has become lower than the frequency of the reference signal input to the input terminal _I2 .

The conventional example shown in Fig. 1 is configured symmetrically with respect to inputs I ₁ and I ₂ , so similarly, the frequency of the signal input to input terminal I ₁ is the same as that of the signal input to input terminal I ₂ . It is also possible to detect when the frequency is higher than that.

However, since each logic gate used in FIG. 1 has the configuration shown in FIGS. 2 and 3, when the output of each logic gate changes, the power supply (V _DD −
Through current flows between V _SS ). This will be explained using FIG. 2.

First, assuming that the three inputs I ₁₀ , I ₂₀ , I ₃₀ are all at V _SS level, the P-type MOSFETs P ₁₀ , P ₂₀ ,
P ₃₀ are all conductive, and N-type MOSFETs N ₁₀ , N ₂₀ ,
All N ₃₀ are non-conducting. Then, the output
_O10 is the _VDD level. Here, when one of the three inputs, say I ₁₀ , changes to V _DD level, the N-type MOSFET N 10 becomes conductive and the P-type MOSFET N ₁₀ becomes conductive.
MOSFET P ₁₀ becomes non-conductive and the output O ₁₀ goes to the V _SS level. At this time, N-type MOSFET N ₁₀ and P
Both MOSFET P ₁₀ become conductive temporarily,
The larger this time, the more V _DD →P ₁₀ →P ₂₀ →P ₃₀ →
The through current in the N ₁₀ →V _SS path is large. When I ₁₀ changes to V _SS level again, the P-type MOSFET
_P10 becomes conductive, N-type MOSFET _N10 becomes non-conductive, and the output _O10 goes to the _VDD level. At this time, P
Both the type MOSFET P ₁₀ and the N type MOSFET N ₁₀ become conductive temporarily, and a through current flows in the same manner as described above. i.e. P type NOSFET P ₁₀ and N type
This means that as long as the conduction and non-conduction of MOSFET _N10 are not coincident in time, a through current will flow. In integrated circuits, P type and N type
MOSFET channel conductance (hereinafter abbreviated as β) and threshold voltage (hereinafter referred to as V _T
) vary independently due to manufacturing, so
It is difficult to make the conduction and non-conduction of the P-type and N-type MOSFETs coincide in time, and it is difficult to prevent the through current from flowing. Furthermore, β and V _T of the P-type and N-type MOSFETs have independent characteristics with respect to fluctuations in ambient temperature.

For these reasons, in conventional frequency comparison circuits, the number of MOSFETs is limited when implemented in integrated circuits.
The disadvantage is that there are 40 logic gates, which occupies a large area, and because it is difficult to prevent the through current from flowing in each logic gate, the current consumption, which is the sum of the through current and the charging/discharging current due to the output capacitance, increases. be. Especially when the frequency is high,
Since the MOSFET is manufactured with a large β and a small output capacitance, the proportion of through current in the current consumption increases, resulting in a noticeable increase in power consumption.

An object of the present invention is to provide a frequency comparison circuit that is configured with a small number of MOSFETs, has no through current, and is particularly effective when the frequency is high.

In the present invention, first, second, and third series circuits each including two first polarity transistors and two second polarity transistors are connected in parallel between power supply terminals, and a first input terminal one first in the first series circuit by a signal supplied to
and a second polarity transistor, controlling one second polarity transistor in the second series circuit and one first polarity transistor in the third series circuit, and controlling one of the first polarity transistors in the third series circuit by a signal supplied to the second input terminal. the other first and second in the series circuit of
polarity transistors, controlling one first polarity transistor in the second series circuit and one second polarity transistor in the third series circuit, the output of the first series circuit controlling the other first polarity transistor in the second series circuit; and controlling a second polarity transistor;
It is characterized in that the output of the second series circuit controls the other first and second polarity transistors in the third series circuit.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a circuit diagram showing an embodiment of the frequency comparison circuit according to the present invention. First, its configuration will be explained. The frequency comparison circuit shown in FIG. 5 consists of first, second, third, fourth, fifth, and sixth P-type MOSFETs.
P ₁₁ , P ₂₁ , P ₃₁ , P ₄₁ , P ₅₁ , P ₆₁ and the seventh, eighth,
9th, 10th, 11th, 12th N-type MOSFET N ₁₁ ,
It includes N ₂₁ , N ₃₁ , N ₄₁ , N ₅₁ , and N ₆₁ . P
Type MOSFET P ₁₁ , P ₄₁ and N type MOSFET
N ₁₁ , N ₄₁ , P type MOSFET P ₂₁ , P ₅₁ and N type
MOSFET N ₂₁ , N ₅₁ and P-type MOSFET
P ₃₁ , P ₆₁ and N-type MOSFETs N ₃₁ , N ₆₁ are each connected in series between power supply terminals V _DD and V _SS . The first input terminal _I11 is a P-type MOSFET
It is connected to each gate of P ₁₁ , P ₅₁ and N-type MOSFET N ₃₁ , N ₄₁ . The second input terminal I ₂₁ is
P-type MOSFET P ₃₁ , P ₄₁ and N-type MOSFET
Connected to each gate of N ₁₁ and N ₅₁ . P type
The gates of MOSFET P ₂₁ and N-type MOSFET N ₂₁ are connected to the connection point J ₁₁ of P-type and N-type MOSFETs P ₄₁ and N ₄₁ . P type and N type
The connection point J ₂₁ of MOSFET P ₅₁ and N ₅₁ is P type.
It is connected to each gate of MOSFET P ₆₁ and N-type MOSFET N ₆₁ , respectively. P type and N type
The connection point of MOSFETs P ₆₁ and N ₆₁ is connected to output terminal O ₁₁ .

Next, its operation will be explained. The first input terminal I ₁₁ is supplied with an input signal that varies over time between two frequencies;
A reference signal having a constant frequency intermediate between the two frequencies is supplied to _I21 . The input signal has positive pulses and the reference signal is a pulse wave with negative pulses.

It detects when the frequency of the input signal is lower or higher than the frequency of the reference signal, and changes the voltage level of the output terminal _O11 to the V _DD and V _SS levels, respectively. Let us take as an example the process of detecting a change from high to low. FIG. 6 shows the signals of each part in that case. In addition, in the initial state, the input terminals I ₁₁ and ₂₁ are at V _SS and V _DD levels, respectively, the connection points J ₁₁ and J ₂₁ are at V _SS and V _DD levels, respectively, and the output terminal O ₁₁ is held at the V _SS level by capacitance. are doing.

First, when the input terminal I ₂₁ reaches the V _SS level, the P type
MOSFET P ₃₁ , P ₄₁ and N-type MOSFET N ₁₁ ,
N ₅₁ becomes conductive and non-conductive, respectively, resulting in the connection point J ₁₁ being at the V _DD level. Furthermore, P type
MOSFET P ₂₁ and N-type MOSFET N ₂₁ become non-conductive and conductive, respectively. At this time, N-type MOSFET N ₅₁
is non-conducting before that, so the connection point J ₂₁
The capacitor holds the V _DD level without changing. Also, when the connection point J ₁₁ changes to the V _DD level, V _DD →
P ₁₁ →P ₄₁ →N ₄₁ →N ₁₁ →V _SS route has N type
Since MOSFET N ₄₁ remains non-conducting, no shoot-through current flows.

Next, when the input terminal ₂₁ becomes V _DD , the P type
MOSFET P ₃₁ , P ₄₁ and N-type MOSFET N ₁₁ ,
N ₅₁ becomes non-conductive and conductive, respectively, and at this time, since the connection point J ₁₁ is capacitively holding the V _DD level, the connection point J ₂₁ becomes the V _SS level. P-type MOSFET P ₆₁ ,
N-type MOSFET _N61 becomes conductive and non-conductive, respectively.
At this time, since the P-type MOSFET P ₃₁ has become non-conductive before that, the output terminal O ₁₁ remains unchanged and remains at V _SS
Hold the level to capacity. Also, when the connection point J ₂₁ changes to the V _SS level, V _DD →P ₂₁ →P ₅₁ →N ₅₁ →N ₂₁ →
Since the P-type MOSFET _P21 remains non-conductive in the path of D _SS , no through current flows.

When the input terminal _I11 reaches _VDD level, the P type
MOSFET P ₁₁ , P ₅₁ and N-type MOSFET N ₃₁ ,
N ₄₁ becomes non-conductive and conductive, respectively. As a result, the connection point _J11 goes to the V _SS level. Furthermore, P type
MOSFET P ₂₁ and N-type MOSFET N ₂₁ are each conductive.
It becomes non-conductive. At this time, since the P-type MOSFET _P51 has become non-conductive before that, the connection point _J21 does not change and maintains the capacitance at the V _SS level. Also,
When the connection point J ₁₁ changes to V _SS level, V _DD → P ₁₁ →
P ₄₁ →N ₄₁ →N ₁₁ →V _SS path has a P-type MOSFET
Since P ₄₁ remains non-conducting, no shoot-through current flows.

Next, when the input terminal _I11 reaches the V _SS level, the P type
MOSFET P ₁₁ , P ₅₁ and N-type MOSFET N ₃₁ ,
N ₄₁ becomes conductive and non-conductive, respectively, and the connection point J ₁₁
is capacitively holding the V _SS level, so the connection point J ₂₁
becomes V _DD level. As a result, the N-type MOSFET
P ₆₁ and N-type MOSFET N ₆₁ become non-conductive and conductive, respectively. Therefore, since the N-type MOSFET _N31 becomes non-conductive before that, the output terminal _O11 does not change and maintains the capacitance at the V _SS level. Also, connection point J ₂₁
When changes to V _DD level, V _DD →P ₂₁ →P ₅₁ →N ₅₁
→N ₂₁ → Since N-type MOSFET N ₂₁ remains non-conductive in the path of V _SS , no through current flows.

In this way, the input terminals I ₁₁ and ₂₁ alternately change the level of V _SS → V _DD → V _SS and V _DD → V _SS →
When the level change of V _DD is repeated, the connection points J ₁₁ and J ₂₁
simply repeats the inversion of the voltage level in response, and the output terminal _O11 remains unchanged. Input terminal ₂₁
After changing the level of V _DD → V _SS → V _DD , the input terminal I ₁₁
Before the level change occurs, the input terminal ₂₁
When the level changes from V _DD → V _SS , P type
MOSFET P ₂₁ becomes conductive. As a result, the output end
O ₁₁ becomes V _DD level. That is, it is detected that the frequency of the signal input to the input terminal _I11 has become lower than the frequency of the signal input to the input terminal ₂₁ . Also, when the output terminal O ₁₁ changes to the V _DD level,
V _DD →P ₃₁ →P ₆₁ →N ₆₁ →N ₃₁ →V _SS route has N type
Since MOSFETs N ₃₁ and N ₆₁ remain non-conducting,
No through current flows.

On the other hand, when the frequency of the signal input to the input terminal _I11 becomes higher than the frequency of the reference signal input to the input terminal ₂₁ , the output terminal _O11 becomes Changes from V _SS level to V _DD level. The detailed circuit operation will be omitted since it can be easily understood from the above. Furthermore, if the frequency of the signal to the input terminal I ₁₁ is equal to that of the reference signal, the output terminal O ₁₁ maintains its previous state.

As described above, the frequency comparison circuit according to the present invention has a smaller number of MOSFETs (12) than the conventional circuit, and can occupy a smaller area within the integrated circuit. Furthermore, changes in the connection points J _{11 and} J ₂₁ and the output terminal O ₁₁ due to changes in the signals input to the input terminals I ₁₁ and 21 occur from the capacitance retention state, so no through current flows between the power supplies. .

As described in detail above, according to the present invention, it is possible to obtain a frequency comparison circuit with a small number of configured MOSFETs and no through current, that is, low power consumption.

[Brief explanation of the drawing]

1, 2, 3, and 4 are logic circuit diagrams showing an example of a conventional frequency comparison circuit, a circuit diagram of a logic gate used in the logic circuit diagram, and an explanation of the operation of the logic circuit. Signal diagrams of each part for
FIG. 5 is a circuit diagram showing one embodiment of the present invention, and FIGS. 6 and 7 are signal diagrams for explaining the operation of FIG. 5, respectively. I ₁ , I ₂ ... input end, O ₁ ... output end, J ₁ , J ₂ , J ₃ , J ₄ ,
J ₅ , J ₆ , J ₇ ... Output of each logic gate, R ₁ , R ₂ , R ₃ ,
R ₄ , R ₅ , R ₆ …NOR gate, AR ₁ , AR ₂ …ANOR
Gate, I ₁₀ , I ₂₀ , I ₃₀ ... input, O ₁₀ ... output, V _DD ,
V _SS ...One end of the power supply, _P10 , _P20 , _P30 ...P type
MOSFET N ₁₀ , N ₂₀ , N ₃₀ …N type MOSFET,
I ₁₀₀ , I ₂₀₀ , I ₃₀₀ ... input, O ₁₀₀ ... output, V _DD , V _SS ...
One end of power supply, P ₁₀₀ , P ₂₀₀ , P ₃₀₀ ...P type MOSFET,
N ₁₀₀ , N ₂₀₀ , N ₃₀₀ ... N-type MOSFET, I ₁ , I ₂ ... Signal at input end, O ₁ ... Signal at output end, J ₁ , J ₂ , J ₃ ,
J ₄ , J ₅ , J ₆ , J ₇ ... Output signal of each logic gate, I ₁₁ ,
I ₂₁ ...Input end, O ₁₁ ...Output end, J ₁₁ , J ₂₁ ...Connection point,
V _DD , V _SS ...One end of the power supply, P ₁₁ , P ₂₁ , P ₃₁ , P ₄₁ ,
_P51 , _P61 ...P-type MOSFET, _N11 , _N21 , _N31 ,
N ₄₁ , N ₅₁ , N ₆₁ ...N-type MOSFET, I ₁₁ , ₂₁ ...Signal at the input end, O ₁₁ ...Signal at the output end, J ₁₁ , J ₂₁ ...Signal at the connection point, Broken line section...Voltage level capacitance Retention period.

Claims (1)

[Claims] 1 first, second, and third series circuits, each including two first-polarity transistors and two second-polarity transistors, are connected in parallel to each other, and a first input signal causes the one of the first and second polarity transistors in the first series circuit, one of the second polarity transistors in the second series circuit, and one of the first polarity transistors in the third series circuit; The other first and second polarity transistors in the first series circuit, the second
One first polarity transistor in the series circuit and one second polarity transistor in the third series circuit are controlled, and the other transistor in the second series circuit is controlled by the output of the first series circuit. 1. A comparator circuit characterized in that the first and second polarity transistors are controlled, and the other first and second polarity transistors in the third series circuit are controlled by the output of the second series circuit.