JPH0252887B2 - - Google Patents
Info
- Publication number
- JPH0252887B2 JPH0252887B2 JP57078552A JP7855282A JPH0252887B2 JP H0252887 B2 JPH0252887 B2 JP H0252887B2 JP 57078552 A JP57078552 A JP 57078552A JP 7855282 A JP7855282 A JP 7855282A JP H0252887 B2 JPH0252887 B2 JP H0252887B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- clock
- circuit
- level
- unipolar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/337—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Dc Digital Transmission (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は、ユニポーラ・バイポーラ変換回路
（以下、Ｕ・Ｂ変換回路と称す）に入力するデー
タ及びクロツクが共に断になつた時にＵ・Ｂ変換
回路内のトランスを保護する保護回路に係り、特
に、簡単な回路構成で実装スペースも小さく、消
費電力も少ないＵ・Ｂ変換回路の保護回路に関す
る。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention provides a method for converting U/B when both data and clock input to a unipolar/bipolar conversion circuit (hereinafter referred to as a U/B conversion circuit) are interrupted. The present invention relates to a protection circuit that protects a transformer in a conversion circuit, and particularly relates to a protection circuit for a U/B conversion circuit that has a simple circuit configuration, a small mounting space, and low power consumption.
(b) 技術の背景
デイジタル通信の分野において、伝送路上にデ
イジタル信号を送出する際、伝送すべきユニポー
ラ信号をバイポーラ信号に変換して送出する。(b) Background of the Technology In the field of digital communications, when transmitting digital signals onto a transmission path, unipolar signals to be transmitted are converted into bipolar signals and then transmitted.
第１図及び第２図を用いて、ユニポーラ信号を
バイポーラ信号に変換するＵ・Ｂ変換回路の一実
施例を説明する。 An embodiment of a U/B conversion circuit that converts a unipolar signal into a bipolar signal will be described with reference to FIGS. 1 and 2.
第１図は、Ｕ・Ｂ変換回路の一構成例を示す図
である。図において、１はJKタイプのフリツプ
フロツプ（以下FFと称す）、２及び３はナンド回
路、４及び５はノア回路、TR1及びTR2はトラン
ジスタ、D1及びD2はダイオード、Ｔはトランス、
Ｃはコンデンサ、Ｒは抵抗である。 FIG. 1 is a diagram showing an example of the configuration of a U/B conversion circuit. In the figure, 1 is a JK type flip-flop (hereinafter referred to as FF), 2 and 3 are NAND circuits, 4 and 5 are NOR circuits, TR 1 and TR 2 are transistors, D 1 and D 2 are diodes, T is a transformer,
C is a capacitor and R is a resistor.
第２図は、第１図の動作説明図であり、同図ａ
はクロツク、ｂはデータ、ｃはFF１のＱ出力、
ｄはFF１の出力、ｅはナンド回路２の出力、
ｆはナンド回路３の出力、ｇはトランスＴの出力
である。 FIG. 2 is an explanatory diagram of the operation in FIG.
is the clock, b is the data, c is the Q output of FF1,
d is the output of FF1, e is the output of NAND circuit 2,
f is the output of the NAND circuit 3, and g is the output of the transformer T.
第２図ａに示すクロツクがFF１のクロツク端
子に入力し、第２図ｂに示す如くのデータがFF
１のＪ端子及びＫ端子に入力したとする。この場
合、FF１のＱ出力及び出力はそれぞれ、第２
図ｃ及びｄに示す波形として出力される。ナンド
回路２では、データ、FF１のＱ出力及びクロク
を入力して、第２図ｅに示す波形を出力する。ま
たナンド回路３では、データ、FF１の出力及
びクロツクを入力して、第２図ｆに示す波形を出
力する。これらの出力は、それぞれノア回路４及
び５でそれぞれ、極性が反転させられる。そし
て、トランジスタTR1に“１”レベルのパルスが
入力したとき、＋5V−トランスＴ−トランジスタ
TR1−アースの系路で電流i1が流れることによ
り、トランスＴの出力はマイナス（−）極性の
“１”レベルとなる。また、トランジスタTR2に
“１”レベルのパルスが入力したとき、＋５−ト
ランスＴ−トランジスタTR2−アースの系路で電
流i2が流れることにより、トランスＴの出力はプ
ラス（＋）極性の“１”レベルとなる。 The clock shown in Figure 2a is input to the clock terminal of FF1, and the data shown in Figure 2b is input to the FF1 clock terminal.
Suppose that input is made to the J terminal and K terminal of No. 1. In this case, the Q output and output of FF1 are respectively
The waveforms shown in Figures c and d are output. The NAND circuit 2 inputs data, the Q output of the FF1, and the clock, and outputs the waveform shown in FIG. 2e. The NAND circuit 3 receives data, the output of the FF 1, and a clock, and outputs the waveform shown in FIG. 2(f). The polarities of these outputs are inverted by NOR circuits 4 and 5, respectively. Then, when a “1” level pulse is input to transistor TR 1 , +5V-transistor T-transistor
As the current i 1 flows in the TR 1 -ground path, the output of the transformer T becomes a "1" level with negative (-) polarity. Furthermore, when a “1” level pulse is input to transistor TR 2 , current i 2 flows in the path of +5 - transformer T - transistor TR 2 - ground, so that the output of transformer T has a positive (+) polarity. The level becomes “1”.
このように、Ｕ・Ｂ変換回路に入力するデータ
の“１”レベルが交互に、“＋１”、“−１”の
データとして出力される。 In this way, the "1" level of the data input to the U/B conversion circuit is alternately output as "+1" and "-1" data.
しかしながら、かかるＵ・Ｂ変換回路におい
て、データ及びクロツクが共に断になり、ナンド
ゲート３の出力が、“０”レベルに固定された場
合、トランジスタTR2が、オン状態が持続する。
このため、＋5V−トランスＴ−トランジスタTR2
−アースの系路で大電流が流れ、トランスＴの巻
線が焼きつくことになる。また、FF１のＱ出が
“１”レベル、出力が“０”レベルに固定され
た場合には、トランジスタTR1のオン状態が持続
する。このため、＋5V−トランスＴ−トランジス
タTR2−アースの系路で大電流が流れ、トランス
Ｔの巻線が焼きつくことになる。 However, in such a U/B conversion circuit, when both the data and the clock are cut off and the output of the NAND gate 3 is fixed at the "0" level, the transistor TR2 remains on.
Therefore, +5V - transformer T - transistor TR 2
- A large current will flow in the ground path, causing the transformer T windings to burn out. Furthermore, when the Q output of FF1 is fixed at the "1" level and the output is fixed at the "0" level, the transistor TR1 remains on. Therefore, a large current flows in the +5V-transistor T-transistor TR 2 -ground path, and the winding of the transformer T is burned out.
このため、データ及びクロツクが共に断になつ
た場合、トランスＴの巻線が焼きつくのを防止す
るために、Ｕ・Ｂ変換回路においては、保護回路
を設けている。 Therefore, in order to prevent the winding of the transformer T from being burned out if both the data and the clock are interrupted, a protection circuit is provided in the U/B conversion circuit.
(c) 従来技術と問題点
第３図及び第４図を用いて、従来の保護回路を
説明する。(c) Prior art and problems A conventional protection circuit will be explained using FIGS. 3 and 4.
第３図は、従来の保護回路を持つたＵ・Ｂ変換
回路のブロツク図である。図において、同一番号
を付加したものは同一の回路を示し、６は単安定
マルチバイブレータ（以下、単安定MBと称す）、
７は保護回路である。 FIG. 3 is a block diagram of a conventional U/B conversion circuit having a protection circuit. In the figure, the same numbers indicate the same circuits, 6 is a monostable multivibrator (hereinafter referred to as monostable MB),
7 is a protection circuit.
第４図は、第３図の動作説明図であり、同図ａ
はクロツク、ｂはデータ、ｃはFF１のＱ出力、
ｄはFF１の出力、ｅはナンド回路２の出力、
ｆはナンド回路３の出力、ｇはトランスＴの出
力、ｈは通常時の単安定MB６の出力、ｉはク
ロツク断時の単安定MB６の出力である。 FIG. 4 is an explanatory diagram of the operation in FIG.
is the clock, b is the data, c is the Q output of FF1,
d is the output of FF1, e is the output of NAND circuit 2,
f is the output of the NAND circuit 3, g is the output of the transformer T, h is the output of the monostable MB6 during normal operation, and i is the output of the monostable MB6 when the clock is cut off.
第４図ａに示すクロツクが入力している時単安
定MB６の出力は第２図ｈに示す如く常に
“０”レベルになるようにして、ナンド回路２，
３の出力パルスが其の侭トランジスタTR1，TR2
に送られるようになつている。 When the clock shown in FIG. 4a is input, the output of the monostable MB6 is always at the "0" level as shown in FIG. 2h, and the NAND circuit 2,
3 output pulses are output from the side transistors TR 1 and TR 2
It is now being sent to
又クロツクが断となり、“１”レベルに固定さ
れると、単安定MB６の出力第２図ｈに示す如
く常に“１”レベルになるようにして、ナンド回
路２，３の出力状態の如何にかかわらず、ノア回
路４，５の出力を“０”レベルとしトランジスタ
TR1，TR2は開の状態に保ち、後で説明する如く
トランジスタTR1，TR2及びトランスＴの焼損す
ることを保護しており、単安定MB６とコンデン
サＣ及び抵抗Ｒで保護回路７を形成している。 Also, when the clock is cut off and fixed at the "1" level, the output of the monostable MB6 is always kept at the "1" level as shown in Figure 2h, and the output status of the NAND circuits 2 and 3 is controlled. Regardless, the outputs of NOR circuits 4 and 5 are set to “0” level, and the transistor
TR 1 and TR 2 are kept open to protect the transistors TR 1 and TR 2 and the transformer T from being burnt out as will be explained later, and the protection circuit 7 is configured with the monostable MB6, capacitor C, and resistor R. is forming.
Ｕ・Ｂ変換回路の動作としては、第２図のｂに
示す如きユニポーラの信号が入力すると、FF１
のＱ出力はデータの立下り点で反転し第４図ｃの
如くになり、FF１の出力は、Ｑの出力を反転
したｄに示す如くになり、ナンド回路２の出力は
データとクロツクとFF１のＱ出力が共に“１”
レベルの時第４図ｅに示す如く“０”レベルとな
り、ナンド回路３の出力はデータとクロツク及び
FF１の出力が共に“１”レベルの時第４図ｆ
に示す如く“０”レベルとなる。これ等の出力を
ノア回路４，５を介してトランジスタTR1及び
TR1を開閉すると、トランジスタTR1が閉の時
は、ａの＋5Vの直流電源よりトランスＴの一次
側の巻線の中点より一方の巻線を通りトランジス
タTR2を通りアースに電流i1が流れる。 As for the operation of the U/B conversion circuit, when a unipolar signal as shown in Fig. 2b is input, FF1
The Q output of FF1 is inverted at the falling point of the data, as shown in Figure 4c, and the output of FF1 is as shown in d, which is the inverted output of Q, and the output of NAND circuit 2 is a combination of data, clock, and FF1. Both Q outputs are “1”
When the level is 0, as shown in Figure 4e, the output of the NAND circuit 3 is the data, clock and
When both FF1 outputs are at “1” level, Figure 4 f
It becomes "0" level as shown in FIG. These outputs are passed through NOR circuits 4 and 5 to transistors TR1 and
When TR 1 is opened and closed, when transistor TR 1 is closed, a current i 1 flows from the +5V DC power supply of a, passes from the midpoint of the primary winding of transformer T, passes through one winding, passes through transistor TR 2 , and goes to ground . flows.
又トランジスタTR2が閉の時はａの＋5Vの直
流電源よりトランスＴの一次側の巻線の中点より
他方の巻線を通りトランジスタTR2を通りアース
に電流i2が流れる。 When the transistor TR 2 is closed, a current i 2 flows from the +5V DC power supply a through the middle point of the primary winding of the transformer T, through the other winding, through the transistor TR 2 , and to the ground.
このことによりトランスＴの出力は第４図ｇに
示す如くになりバイポーラ符号に変換される。 As a result, the output of the transformer T becomes as shown in FIG. 4g and is converted into a bipolar code.
今クロツクが断で“１”レベルに固定され、其
の時データも断となり“１”レベルに固定され、
FF１のＱ又は出力が“１”レベルに固定され
ると、ナンド回路２又は３の出力は“０”レベル
に固定され、保護回路７がなければノア回路４又
は５の出力の１方が“１”レベルに固定され、電
流i1又はi2が流れ放しになりトランジスタTR1又
はTR2及びトランスＴを焼損することになるが、
これを保護回路７の出力がクロツク断の時“１”
レベルになるようにしてノア回路４，５の出力を
“０”レベルとして保護している。 Now the clock is broken and is fixed at the "1" level, and at that time the data is also broken and fixed at the "1" level.
When the Q or output of FF1 is fixed at "1" level, the output of NAND circuit 2 or 3 is fixed at "0" level, and if there is no protection circuit 7, one of the outputs of NOR circuit 4 or 5 will be "1" level, the current i 1 or i 2 is allowed to flow and burns out the transistor TR 1 or TR 2 and the transformer T.
This is set to “1” when the output of the protection circuit 7 is cut off.
The outputs of the NOR circuits 4 and 5 are protected as "0" level.
しかしこの保護回路７は、抵抗Ｒを介して単安
定MB６に電流を供給するため抵抗Ｒの値は大き
く出来ず、抵抗Ｒと共に時定数を持たせるコンデ
ンサＣの容量が大きくなり、プリント板等に実装
するスペースが大きくなり、又単安定MB６は回
路規模も大きく、単安定MB６は消費電力が大き
い欠点がある。 However, since this protection circuit 7 supplies current to the monostable MB6 via the resistor R, the value of the resistor R cannot be made large, and the capacitance of the capacitor C that provides a time constant becomes large together with the resistor R. The mounting space is large, the circuit scale of the monostable MB6 is also large, and the monostable MB6 has the drawbacks of high power consumption.
(d) 発明の目的
本発明の目的は上記の欠点をなくし、簡単な回
路で実装スペースも小さく又消費電力も少ない
Ｕ・Ｂ変換回路の保護回路の提供にある。(d) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a protection circuit for a U/B conversion circuit that is a simple circuit, requires less mounting space, and consumes less power.
(e) 発明の構成
本発明は上記の目的を達成するために、Ｕ・Ｂ
変換部のクロツク入力端子に基底線クランパ回路
を設け、其の出力を、クロツクパルスより時定数
の長い時定数回路と整流器により整流平滑し、ク
ロツクが通常の場合は時定数回路の出力を“１”
とし、断の場合は、“０”とし、この出力をイン
バータ・ゲートにより反転して保護回路としてい
ることを特徴とする。(e) Structure of the invention In order to achieve the above object, the present invention
A baseline clamper circuit is provided at the clock input terminal of the converter, and its output is rectified and smoothed by a time constant circuit with a longer time constant than the clock pulse and a rectifier.When the clock is normal, the output of the time constant circuit is set to "1".
When the output is off, it is set to "0", and this output is inverted by an inverter gate to form a protection circuit.
(f) 発明の実施例
以下本発明の１実施例につき第５図及び第６図
に従つて説明する。(f) Embodiment of the invention An embodiment of the invention will be described below with reference to FIGS. 5 and 6.
第５図は本発明の一実施例の保護回路を持つた
Ｕ・Ｂ変換回路のブロツク図、第４図は第５図の
保護回路７′のｂ，ｃ，ｄ，ｅ点の波形のタイム
チヤートでＡはクロツクが通常の場合Ｂはクロツ
ク断の場合を示す。 Fig. 5 is a block diagram of a U/B conversion circuit having a protection circuit according to an embodiment of the present invention, and Fig. 4 shows the waveform times at points b, c, d, and e of the protection circuit 7' in Fig. 5. In the chart, A shows the case where the clock is normal and B shows the case where the clock is disconnected.
図中第３図と同一機能のものは同一記号で示
す。７′は保護回路、R1，R2は抵抗、D3，D4は
ダイオード、C1，C2はコンデンサ、８はインバ
ータ・ゲートを示す。 Components in the figure that have the same functions as those in FIG. 3 are indicated by the same symbols. 7' is a protection circuit, R 1 and R 2 are resistors, D 3 and D 4 are diodes, C 1 and C 2 are capacitors, and 8 is an inverter gate.
動作としては第３図と同じであり、異なる点は
保護回路７′の回路の内容が異つている。 The operation is the same as that shown in FIG. 3, except that the contents of the protection circuit 7' are different.
保護回路７′について説明すると、クロツクが
通常の場合はｂ点では通常のクロツク波形であ
り、コンデンサC1、ダイオードD3で基底線クラ
ンパ回路が構成されており、Ｃ点の波形もクロツ
ク波形と同様である。ｄ点の波形は、クロツクパ
ルスより時定数の長い抵抗R2、コンデンサC2よ
りなる時定数回路とダイオードD4により整流平
滑化され“１”レベル連続となり、インバータ・
ゲート８の出力ｅ点では“０”レベル連続とな
る。クロツクが断となりｂ点が“１”レベル連続
となると、基底線クランパ回路出力のｃ点は
“０”レベル連続となり、従つてｄ点も“０”レ
ベル連続となり、インバータ・ゲート８の出力は
“１”レベル連続となり、第３図の場合で説明し
た保護回路７と同一の働きをする。この回路では
抵抗R2は大きく出来るので時定数を持たせるコ
ンデンサC2の大きさは小さく出来る。又この回
路は抵抗、コンデンサ、ダイオード各２個とイン
バータ・ゲート１個で構成されているので消費電
力も小さく、回路規模も小さく、又コンデンサ
C1，C2の容量も小さくLSI化も可能なのでプリン
ト板等へ実装する場合のスペースも小さくてよ
い。尚又インバータ・ゲート８が他のLSI化され
た物に余つているものがある場合は、其れを利用
すれば抵抗、コンデンサ、ダイオードはプリント
板の空き部分に実装することも出来るので、プリ
ント板に実装する場合特に保護回路の実装スペー
スを確保しなくても良い。 To explain the protection circuit 7', when the clock is normal, the clock waveform at point B is the normal clock waveform, the capacitor C 1 and the diode D 3 constitute a baseline clamper circuit, and the waveform at point C is also the same as the clock waveform. The same is true. The waveform at point d is rectified and smoothed by a time constant circuit consisting of a resistor R 2 and a capacitor C 2 whose time constant is longer than that of the clock pulse, and a diode D 4 , resulting in a continuous “1” level.
At the output point e of the gate 8, the "0" level continues. When the clock is cut off and point b remains at "1" level, point c of the base line clamper circuit output continues at "0" level, and therefore point d also remains at "0" level, and the output of inverter gate 8 becomes The "1" level is continuous, and it functions in the same way as the protection circuit 7 described in the case of FIG. In this circuit, the resistor R 2 can be made large, so the size of the capacitor C 2 that provides the time constant can be made small. In addition, this circuit consists of two resistors, two capacitors, two diodes, and one inverter gate, so the power consumption is low, the circuit size is small, and the capacitor
Since the capacitance of C 1 and C 2 is small and can be implemented as an LSI, the space required for mounting on a printed board etc. is also small. Furthermore, if you have an inverter gate 8 left over from another LSI, you can use it to mount the resistor, capacitor, and diode in the empty space on the printed board. When mounting on a board, there is no need to secure mounting space for the protection circuit.
(g) 発明の効果
以上詳細に説明せる如く、本発明によれば簡単
な回路で、実装スペースも小さく、又消費電力も
小さい保護回路が得られる効果がある。(g) Effects of the Invention As explained in detail above, the present invention has the effect of providing a protection circuit that is simple, requires a small mounting space, and consumes little power.
第１図はＵ・Ｂ変換回路の一構成例を示す図、
第２図は第１図の動作説明図、第３図は従来の保
護回路を持つたユニポーラ・バイポーラ変換回路
のブロツク図、第４図は第３図の各部の波形のタ
イムチヤート、第５図は本発明の実施例の保護回
路を持つたユニポーラ・バイポーラ変換部の回路
のブロツク図、第６図は第５図の保護回路７′の
ｂ，ｃ，ｄ，ｅ点の波形のタイムチヤートであ
る。
図中１はJKタイプFF、２，３はNAND回路、
４，５はNOR回路、６は単安定マルチバイブレ
ータ、７，７′は保護回路、TR1，TR2はトラン
ジスタ、D1〜D4はダイオード、Ｔはトランス、
Ｃ，C1，C2はコンデンサ、Ｒ，R1，R2は抵抗、
８はインバータ・ゲートを示す。
FIG. 1 is a diagram showing an example of the configuration of a U/B conversion circuit,
Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is a block diagram of a unipolar/bipolar conversion circuit with a conventional protection circuit, Fig. 4 is a time chart of waveforms of various parts in Fig. 3, Fig. 5 6 is a block diagram of a circuit of a unipolar-bipolar converter having a protection circuit according to an embodiment of the present invention, and FIG. 6 is a time chart of waveforms at points b, c, d, and e of the protection circuit 7' in FIG. be. In the figure, 1 is JK type FF, 2 and 3 are NAND circuits,
4 and 5 are NOR circuits, 6 is a monostable multivibrator, 7 and 7' are protection circuits, TR 1 and TR 2 are transistors, D 1 to D 4 are diodes, T is a transformer,
C, C 1 and C 2 are capacitors, R, R 1 and R 2 are resistors,
8 indicates an inverter gate.
Claims (1)
ロツクにしたがつて、該ユニポーラ信号をバイポ
ーラ信号に変換し、該ユニポーラ信号及び該クロ
ツク入力が断になつたとき、出力が正極性又は負
極性に固定されるユニポーラ・バイポーラ変換回
路で、該ユニポーラ信号及びクロツク入力が断に
なつたとき、該ユニポーラ・バイポーラ変換回路
の出力を“０”レベルに固定する保護回路におい
て、該ユニポーラ・バイポーラ変換回路のクロツ
クの入力端子から、第１の容量及び第１のダイオ
ードを介してインバータに接続し、かつ該第１の
容量の該クロツクの入力端子に接続される側に第
１の抵抗を設けて接地するとともに、該第１の容
量の他方に第２のダイオードを設けて接地し、該
第１のダイオードと該インバータ間に第２の抵
抗、第２の容量を設けてそれぞれ接地して構成
し、該インバータの出力により、該ユニポーラ信
号及びクロツク入力断時に該ユニポーラ・バイポ
ーラ変換回路の出力を“０”レベルに固定するこ
とを特徴とするユニポーラ・バイポーラ変換回路
の保護回路。1. When a unipolar signal and a clock are input, the unipolar signal is converted to a bipolar signal according to the clock, and when the unipolar signal and the clock input are disconnected, the output is fixed to positive or negative polarity. In a protection circuit that fixes the output of the unipolar to bipolar conversion circuit to "0" level when the unipolar signal and clock input are disconnected in the unipolar to bipolar conversion circuit, the clock input of the unipolar to bipolar conversion circuit is fixed. A first resistor is connected from the terminal to the inverter via a first capacitor and a first diode, and a first resistor is provided on the side of the first capacitor that is connected to the input terminal of the clock, and the first resistor is grounded. A second diode is provided on the other side of the first capacitor and grounded, and a second resistor and a second capacitor are provided between the first diode and the inverter and each grounded. A protection circuit for a unipolar/bipolar conversion circuit, wherein the output of the unipolar/bipolar conversion circuit is fixed at a "0" level when the unipolar signal and clock input are cut off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57078552A JPS58195315A (en) | 1982-05-11 | 1982-05-11 | Protection circuit for unipolar-bipolar conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57078552A JPS58195315A (en) | 1982-05-11 | 1982-05-11 | Protection circuit for unipolar-bipolar conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58195315A JPS58195315A (en) | 1983-11-14 |
| JPH0252887B2 true JPH0252887B2 (en) | 1990-11-15 |
Family
ID=13665077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57078552A Granted JPS58195315A (en) | 1982-05-11 | 1982-05-11 | Protection circuit for unipolar-bipolar conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58195315A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07118653B2 (en) * | 1987-11-20 | 1995-12-18 | 富士通株式会社 | Unipolar / bipolar conversion circuit |
-
1982
- 1982-05-11 JP JP57078552A patent/JPS58195315A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58195315A (en) | 1983-11-14 |
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