JPH025350B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sub-scanning line density determination circuit for facsimiles and similar devices that binarize and transmit image information.

Conventionally, in facsimile systems that binarize image signals and transmit them, depending on the image information density of the original image,
There is a method in which the line density of sub-scanning lines is appropriately switched for each original image and transmitted. This method has the disadvantage that when a single original image contains both complex and simple images, the line density cannot be switched midway.

In order to improve this drawback, the amount of information to be transmitted is determined for each scanning line or for each predetermined section of one scanning line. A method has been proposed in which the number of scanning lines is reduced for parts of the image. This method not only has the possibility of determining a simple image when a complex image is localized, but also when the same image continues in the sub-scanning line direction, if there are many changed pixels, the scanning line It has the disadvantage that it is transmitted in a dense manner and the transmission time is not shortened.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the prior art, and its purpose is to accurately detect the difference between the current transmission line and the next transmission line even when different pixels are localized. An object of the present invention is to provide a circuit that determines the scanning line density by determining the scanning line density.

The above object of the present invention is to provide two shift register circuits that continuously store two lines of image signals read and binarized for each run and output them using a transfer clock, and a transfer clock from each shift register circuit. A circuit that sequentially compares the image signals output by the circuits and detects and counts different image signals from the first bit, and after delaying each of the compared image signals by a predetermined number of transfer clocks, two shift register circuits that output again, and a circuit that sequentially compares the output from the first bit starting from the first bit using the same transfer clock as the circuit performing the above comparison, and detects and counts different image signals. , and a circuit that sequentially detects for each bit output by the transfer clock whether or not the difference between the two counted values has reached a specified value, and the correlation between the two lines is determined by the output of the detection means. This is achieved by determining the sub-scanning line density by determining the strength of the sub-scanning line.

The present invention will be explained below by way of examples with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, numerals 1, 2, and 3 are shift registers that can store pixels for one line.
4 and 5 can also store, for example, 40 pixels with a shift register. 6 is a counter whose output changes from a low level (hereinafter abbreviated as L) to a high level (hereinafter abbreviated as H) when counting the same number of image signal transfer clocks as the number of pixels stored in the shift registers 4 and 5; Similarly, the counter outputs one pulse at the end of each line, for example, every 256 image signal transfer clocks. 11 and 12 are on the counter
Counting is performed when the CLA input is H, and the count value becomes "0" when the preset input is H. 13 is a subtraction circuit which outputs the result obtained by subtracting the output of the counter 12 from the output of the counter 11. For example, 14 is 5
It is a constant generator that always outputs (00000101). 15 is a comparator which outputs H when (output of subtraction circuit 13) ≧ (output of constant generator 14). 17 and 18 are D flip-flops (hereinafter abbreviated as FF), 16 and 20 are OR
circuit, 20 is an inverter, 8 is an AND circuit, 9,
10 is an exclusive OR circuit.

Next, the operation of the circuit shown in FIG. 1 will be explained.

First, at the beginning of the line, counters 6, 11, 12, comparison circuit 15, FF1 are
7 is reset, counter 6 is L, counter 1 is reset.
1 and 12 are outputting "0", and the comparator circuit 15 and FF 17 are outputting L.

Next, when the original H and L signals obtained by scanning the original image are applied to the input terminal P, and their transfer clock is applied to the input terminal C, the corresponding pixels between the two lines are shifted. register circuit 1,
The two outputs are subjected to exclusive OR, and the different numbers of pixels are counted by the counter 11. When the image signal transfer clock reaches 40, the input of the counter 12 becomes H by the counter 6, and the counter 12 becomes capable of counting. From this point on, the outputs of shift registers 4 and 5 begin to output image signals delayed by 40 pixels from those of shift registers 1 and 2, respectively. That is, compared to the output of the counter 11, the output of the counter 12 represents the different number of pixels between two corresponding lines up to 40 pixels earlier. Subtractor 13
outputs the result of (value of counter 11) - (value of counter 12) for each transfer clock, that is, the number of different pixels for 40 pixels before that transfer clock, and comparator 15 outputs the result and the specified value. is constantly compared, and outputs H when it exceeds the specified value. If the specified value is exceeded even once, the FF 17 outputs an H signal and latches it until the end of one line. In other words, the different pixels between the two lines are monitored every transfer clock in a predetermined width of 40 pixels, so no matter where the different pixels between the two lines are located, the strength of the correlation between the two lines is This will allow us to accurately determine the

Next, the operation of the above embodiment will be explained using the time chart shown in FIG.

In FIG. 2, a is a waveform diagram of the image signal transfer pulse applied to the input terminal c, b is an output of the counter 6, and c is a waveform diagram of the output of the counter 7. If there is a section in which the number of different pixels exceeds the specified value between two lines, the output of the FF 17 becomes H when that section is determined, and is latched as is. The situation is shown in Figure 2d. The output of FF17 is latched to FF18 by the pulse of counter 7 at the end of one line, and as shown in FIG. The circuit 8 allows the next line to be loaded into the shift register 3. Also at this time, counters 6, 11, 12, comparator 15,
The FF 17 is reset and returns to its initial state.

Next, if the output of the comparator 15 is L for each line, that is, the next line is a line that is very similar to the current line, such that there are no pixels that are different from the current line by more than a specified value in any 40-pixel section. In some cases, when the previous line is a sending line and the output terminal O is H, the output of the FF 17 is L, and this output is the value of the counter 7 at the end of one line, as shown in A of Fig. 2 e'. The pulse causes FF18 to be latched as L. The output of the FF 18 outputs an L signal instructing deletion of the next line to the output terminal O until the end of the next line, and the AND circuit 8 disables loading the next line into the shift register 3. Also at this time, counters 6, 11, 12, comparator 15, FF
17 is reset and returns to the initial state, but FF18
The L output of is fed back to the FF 17 through the inverter 19, and at the next image signal transfer clock,
FF17 is latched as H, and as shown in B in Figure 2d, this causes the output of FF17 to be set to H and generates a signal instructing the transmission of the next line. The configuration is such that images that are changing gradually are not deleted one after another.

Since this circuit operates as described above, for transmission processing, it is only necessary to check the state of output terminal O at the end of one line scanning and control the scanning speed in accordance with the transmission processing speed only when O is H. It is sufficient to always send out the shift register 3 as the image signal.

As explained in detail above, according to the present invention, it is possible to monitor and determine whether the next line is very similar to the current sending line using a constant width and pixel shift. In an image with two lines, both lines are not sent because there are many changed pixels, and even if a large difference is localized in any way, it will not be mistakenly determined as a deleted line. Therefore, any image can be clearly transmitted with a high scanning line density if it differs from the transmission line by more than a specified value, or with a sparse scanning line density if it is very similar to the transmission line. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a scanning line density determining circuit according to the present invention, and FIG. 2 is a time chart showing waveforms of various parts of the circuit shown in FIG.
Note that the symbols used in the drawings indicate the following. 1, 2, 3, 4, 5...shift register, 6,
7, 11, 12...Counter, 8...AND circuit,
9, 10... Exclusive OR circuit, 13... Subtraction circuit, 14... Constant generator, 15... Comparison circuit, 16, 20... OR circuit, 17, 18...
FF circuit, 19...Negation circuit.

Claims (1)

[Claims] Two shift register circuits that continuously store two lines of image signals that are read and binarized for each line and output them using a transfer clock, and output signals from each shift register circuit using a transfer clock. A circuit that sequentially compares image signals and detects and counts different image signals starting from the first bit, and a circuit that delays each of the two compared image signals by a predetermined number of transfer clocks and then outputs them again. Similarly, the first shift register circuit and its output are transferred to the first shift register circuit using the same transfer clock as the circuit performing the above comparison.
A circuit that sequentially compares the bits and detects and counts different image signals, and a circuit that sequentially compares each bit outputted by a transfer clock to determine whether the difference between the two counts has reached a specified value. 1. An automatic line density determination circuit comprising: a detection circuit, and determines a sub-scanning line density by determining the strength of correlation between two lines based on the output of the detection means.