JPH0253795B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention detects a pattern displayed on a CRT screen and changes it to another pattern, changing the color or changing a straight line to a dotted line. This invention relates to a display control device that can change graphics.

[Conventional technology]

Many personal computers use color CRTs for their displays and display color graphics using the digital RGB system. Since it is digital RGB, the types of colors that can be displayed are R, G, B, RG, GB,
There are 7 colors: RB, RGB. By adding brightness information I to R, G, and B, brightness and darkness of these seven colors can be obtained, and further by using a method called tile painting, intermediate colors can be obtained.

In Tile Paint, for example, 8 on the display
In terms of memory, it is 8 bits (this is RGBI).
There are 8 bits for each, so the total is 32.
The upper 4 bits and lower 4 bits of the 8 bits are each expressed in hexadecimal numbers, and are therefore 00 to FF, blue B is 55, red R is
Assuming that AA, green G is 00, and brightness I is 00, Fig. 2 c
, blue is displayed every other bit, red is also displayed every other bit and is different from blue, and green is not displayed, and their brightness is at a level of 00 (this refers to a certain brightness level, It does not mean complete darkness). The reason why B and R are as shown is that 55=01010101 and AA=10101010. When B and R are displayed in such a tile pattern, they appear to be a neutral purple color to the human eye. Other neutral colors can be created using a similar method.

When graphic display is handled using the 8-bit (multi-bit) method, solid lines, dotted lines, chain lines, etc. can be easily displayed. That is, if R is 80 and B=G=I=00, then 80=10000000, so a point is displayed,
By arranging a plurality of such 8-bit units, a dotted line R is obtained. If R = 88, B = G = I = 00, it will still be a red dotted line, but it will be a fine dotted line with a pitch. R=
When 9C=10011100, a red chain line is obtained, and other chain lines can be obtained using the same method.

[Problem that the invention seeks to solve]

To display characters and figures (herein simply referred to as figures) on a CRT display, the dot patterns are stored in VRAM (Video Random Access Memory, in the case of color, there are four in total for R, G, B, and I). Write it in advance, read it out, and display it on the CRT screen. Pattern change requests such as changing the color of a figure or changing its shape (changing a solid line to a dotted line, etc.) occur, but conventionally these change requests have been processed by software. That is, the program
The data was read from VRAM and rewritten to the required color and shape data for the shape part that needed to be changed, but this method was slow in processing speed.
It puts a heavy burden on the CPU, and it is not easy to change only a specified area on the screen.

Therefore, it is an object of the present invention to provide a display control device that can quickly change patterns, reduce the load on the CPU, and easily change patterns only in designated areas.

[Means for solving problems]

The present invention provides a display control device that is provided with a video random access memory for three primary colors R, G, and B, and an address generator that generates an access address for the memory, and in which the memory can be accessed in units of a plurality of bits. Compare the read output of the memory and the output of the comparison pattern register with the register that stores the comparison pattern in bit units and the register that stores the changed pattern, and if they match, change the data stored in the memory at the address. A control circuit for rewriting the output data of the rear pattern register is provided, and the address generation section is configured to generate each address in a region between the specified start and end coordinates of the display screen in a television scan manner. Next, the configuration will be explained with reference to the examples.
The action will be explained in detail.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and 10 is
There are a total of 4 VRAMs for R, G, B, and I. 12
is a latch circuit, and in this example, since VRAM is read out in 8-bit units, it consists of 8-bit registers for each of R, G, B, and I. 14 is not shown
A register 16 is into which a comparison pattern is written by the CPU (Central Processing Unit), and a register 16 is into which a pattern after change is written.These registers each have a capacity of 8 bits for R, G, B, and I. 18 is VRAM10
This is an address generation unit that generates an access address and mask data MD. 20 is a pattern detection circuit that compares the output pattern of the latch circuit 12 and the output pattern of the register 14, and if the two match, it goes to, for example, H (high) level, and if they do not match, it goes to L in this example.
(low) level select output. 22 is an output data selection circuit, 24 is an output control circuit, and the selection circuit 22 adds mask data MD, which will be described later, to the selected output of the detection circuit 20. Output control circuit 24 is connected to terminal 1
The output of the latch circuit 12 is connected to A~4A, and the output of the latch circuit 12 is connected to terminals 1B~
4B receives the output of the register 16, and the terminal SEL receives the above selection signal, and according to the selection signal, the terminal 1
Input data of A to 4A or input data of terminals 1B to 4B is applied to output terminals 1Y to 4Y. Although not shown in the drawing, the address generation unit 18 contains the start coordinates (X ₀ , Y ₀ ) and end coordinates (X ₁ , Y ₁ ) of the processing target area.
There are registers that are written to by the CPU.

To explain the operation, the CPU (not shown) writes the start coordinates (X ₀ , Y ₀ ), end coordinates (X ₁ , Y ₁ ), comparison (change target) pattern, and post-change pattern to the register according to operator input data. , starts the address generator. When the starting end coordinates and ending end coordinates are given, the processing target area is determined as shown with diagonal lines in FIG.
8 sequentially generates addresses in this range in a television scan manner. In Figure 2a, 30 indicates the CRT screen or the storage area of VRAM (both RGBI).
In this example, the processing target area 32 is the upper left corner, but of course this can be any part within the area 30 depending on the designation of the coordinates (X ₀ , Y ₀ ) and (X ₁ , Y ₁ ).
The address generation section has a preset and output end changeable X address counter that has a counting capacity equal to the number of bits in the horizontal direction, and counts the output pulses of the counter, and has a counting capacity equal to the number of horizontal scanning lines of one screen. and output terminal changeable Y address counters, preset X ₀ , Y ₀ to these counters, change the output terminals to X ₁ , Y ₁ , and thus (X ₀ , Y ₀ ) to (X ₁ , Y ₁ ) Output each address in the intervening rectangular area in a television scan style.

Upon receiving such addresses, the VRMA 10 sends each address (X ₀ , Y ₀ ), (X ₁ , Y ₀ ), (X ₂ , Y ₀ ),
...(X ₁ , Y ₁ ) is sequentially read out, taken into the latch circuit 12, and compared with the 8-bit pattern in the register 14 in the detection circuit 20. Currently, the processing target area of VRAM has a second
As shown in Figure b, if a short red straight line is written in the figures F ₁ , F ₂ , F ₃ in this example, the data read at the above access address will be all read until the access comes to figure F ₁ . It is 0. In the register 14, R= shows a red straight line as a comparison pattern.
FF, G=B=I=00 is written, register 1
6 shows G= a straight line as a change pattern.
Assuming that FF, R=B=I=00 is written, that is, an instruction is given to change the red line to the green line, the pattern detection circuit 20 will detect a mismatch in this example until the access comes to figure _F1 . In this case, an L level selection output is generated, which means that the output control circuit 24 transfers the data of terminals 1A to 4A, that is, the VRAM read data, to terminals 1Y to 4A.
Make it output to 4Y. This output data is
The data is returned to the VRAM 10 and written to the read address. Therefore, the data stored in the VRAM 10 remains unchanged.

When the access enters the figure _F1 , the output data of the latch circuit 12 and the output data of the register 14 match, so the pattern detection circuit 22 sets the selection output level to H in this example, which is caused by the output control circuit 24 input data is output to terminals 1Y to 4Y. This output data is VRAM1
It is written to the read address of 0, and thus the short red straight line _F1 is changed to the short green straight line (8
(in bits). When the access address passes figure _F1 , the comparison result returns to a mismatch, and the VRAM storage data remains unchanged. Access address is shape F ₂
When it comes to VRAM1, the comparison results match again and VRAM1
The corresponding data of 0 is changed from red to green. The same applies below.

Since only the area to be processed is read from the VRAM 10, even if figures _F5 and _F6 exist outside the area, the figure data will not be changed. Furthermore, even if there is another figure, such as a short green straight line, within the processing target area, this does not match the comparison pattern in the register 14, so the data of the figure will not be changed. Further, if a blue dotted line, chain line, etc. is used as the changed pattern to be registered in the register 16, the figure _F1 is changed to the blue dotted line, chain line, etc.

Coordinates (X ₀ , Y ₀ ) that specify the area to be processed,
Since (X ₁ , Y ₁ ) is in units of bits or dots, if 8 bits are processed, there is a risk that the end portion will be a fraction. For example, if there is a figure _F4 in Figure 2b, and the processing target area is specified as (X ₀ , Y ₀ ), (X ₁ ', Y ₁ ), processing 8 bits from the edge will result in the shape of this figure. Although the latter half is outside the range, it is changed.
In other words, if it is 8-bit processing, in this case the X termination is
Even if it is set to X′, data up to X ₁ will be read and written,
It turns out that even X ₁ was scanned. The mask data MD output by the address generator 18 is designed to deal with this problem, and since the portion of the 8 bits that goes outside the specified area can be easily calculated by the address generator, that portion is masked. For example, if 0 is left as is (the changed pattern is adopted), 1 is masked (no change is made and VRAM read data is adopted), and the protruding portion is the last 3 bits, the mask data MD becomes 00000111. This mask data MD enters the output control circuit 24 through the selection circuit 22, and when the data at the terminals 1B to 4B is adopted, that is, when the data is changed, the data at the terminals 1B to 4B is the upper one in the above example. Up to 5 bits are adopted, and the remaining lower 3 bits are adopted from terminals 1A to 4A, and these are output to terminals 1Y to 4Y.

In Figure 1, WRCK is a timing signal,
When the VRAM read data is taken into the latch circuit 12 and can be compared by the detection circuit 20, the data in the register 14 is output to the detection circuit 20, and the data in the register 16 is output to the output control circuit 24. VLATCH is also a timing signal and VRAM
It becomes a clock that causes the latch circuit 12 to take in the read data. VRAMB is also a timing signal, and instructs the address generator 18 to increment the address when output data from terminals 1Y to 4Y is written to VRAM. In addition, in this first figure
Although the VRAM read/write control circuit is not shown, it is naturally provided. The depth of each VRAM is 8 bits in the preferred embodiment, so the width of the address space is 1/8 the number of dots on the display screen.

〔Effect of the invention〕

As is clear from the above explanation, the present invention
It can detect a specified pattern on the display screen and quickly change it to a different pattern with less CPU load. In other words, the work done by the CPU, or in other words, the work done by software, begins with the registers.
All you have to do is write the end point coordinates, comparison pattern, and post-change pattern and instruct the address generator to start.The hardware shown in FIG. 1 then automatically reads the VRAM, compares the patterns, and changes the corresponding pattern. Compared to the sequential processing performed by software, this processing by hardware can improve the processing speed by about an order of magnitude. To change a pattern, simply write the changed pattern into a register and replace the corresponding part with it, so changing colors, changing solid lines/dotted lines, etc. can be done very easily and quickly. Further, the processing target area can be easily specified by simply inputting the start and end coordinates. In personal computers, a multi-window system in which a CRT screen is divided into a plurality of sections is becoming popular, and the present invention is extremely effective when applied to such a system.

If a plurality of comparison pattern registers 14 and post-change pattern registers 16 are provided, and the pattern detection circuit 20 compares the outputs of the plurality of comparison pattern registers with the VRAM read data,
Various figures in the processing target area can be changed simultaneously with other specified figures.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an operation explanatory diagram. In the drawing, 10 is a VRAM, 18 is an address generation section, 14 is a comparison pattern register, 16 is a changed pattern register, and 20 and 24 are control circuits.

Claims (1)

[Scope of Claims] 1. A display control device comprising a video random access memory for the three primary colors R, G, and B, and an address generation section that generates an access address for the memory, the memory being accessible in units of multiple bits. , Compare the readout output of the memory and the output of the comparison pattern register with the register storing the comparison pattern in units of multiple bits and the register storing the changed pattern, and if they match, the storage of the address in the memory is performed. and a control circuit that rewrites the data to the output data of the pattern register after the data has been changed, and the address generating section is configured to generate each address in the area between the specified start and end coordinates of the display screen in a television scanning manner. A display control device characterized by: