JPH0253988B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise removal circuit for removing noise mixed in a pulse signal of a predetermined period.

Generally, there is a possibility that noise from the transmission path may be mixed into the synchronization signal transmitted from the sending facsimile to the receiving facsimile. Therefore, among the noise mixed in the received synchronization signal, noise below a certain voltage level is removed by the limiter, but noise above a certain voltage level is not removed. Conventionally, the noise has not been completely removed, resulting in errors in the detection of the received synchronization signal, which in turn leads to synchronization of the rotation of the drums of the facsimile machines on the sending and receiving sides. This caused the inconvenience that the original image on the sending side and the received image were misaligned.

The present invention has been made based on the above-mentioned circumstances, and its object is to provide a noise removal circuit that completely removes noise mixed in pulse signals sent at predetermined synchronization.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 shows a circuit diagram of main parts when the present invention is applied to a facsimile machine. Reference numeral 1 in FIG. 1 is a limiter amplifier provided in a facsimile on the receiving side, and a synchronization signal containing a noise signal transmitted from the facsimile on the transmitting side is input to this limiter amplifier 1.
When this synchronization signal is input to limiter amplifier 1,
Noise signals below a certain voltage level are removed, and noise signals above a certain voltage level are adjusted to a certain level, then amplified to a certain voltage and output to the waveform shaping circuit 2. The waveform shaping circuit 2 shapes the waveform of the amplified synchronizing signal by removing waveform distortion, and outputs the shaped synchronizing signal to the synchronizing differentiation circuit 3. The synchronous differentiation circuit 3 shapes the input synchronous signal into a rectangular signal and sends it to the AND circuit 4.
Output via . The synchronization signal output from the AND circuit 4 is used to synchronize the receiving operation.

Furthermore, the output of the synchronous differentiator 3 is input as a clock signal to the pulse number detection circuit 5 and also to one side of the AND circuit 6. The pulse number detection circuit 5 has four output terminals Q ₁ , Q ₂ , Q ₃ , Q ₄
It is composed of a four-stage shift register with a "1" level signal VD at its input terminal D.
is always entered. Further, the output of the AND circuit 6 is input to the reset terminal of the counter 8 after being slightly delayed by the delay circuit 7. A clock signal having a cycle much shorter than the cycle of the synchronization signal is input to the clock input terminal of the counter 8. The count value of the counter 8 is always outputted to the comparison circuit 9, and furthermore, the count value of the counter ₈ is outputted to the comparison circuit 9.
The count value is set in the latch circuit 10. The comparator circuit 9 constantly compares the counted value of the counter 8 and the counted value of the latch circuit 10, and outputs binary signals "1" and "0" of coincidence and mismatch to the input terminal D of the flip-flop circuit 11. ing. The pulse signal from the synchronous differentiator circuit 3 is input to the clock input terminal CP of this flip-flop circuit 11, and the signal "1" input to the input terminal D is input to the clock input terminal CP.
In response to "0", a signal "1" is output to the set output terminal Q or the reset output terminal. The signal at the set output terminal Q is input to the one shot circuit 12, the inverter circuit 13, the OR circuit 14, and the AND circuit 4. The output signal of the one-shot circuit 12 is sent to the reset terminal R of the shift register 15.
is input to. A "1" level signal VD is always input to the input terminal D of the shift register 15. Further, the signal of the synchronous differentiating circuit 3 is transmitted to the delay circuit 1.
6 to one side of the AND circuit 17, and the other side of the AND circuit 17 receives the output signal from the reset output terminal of the flip-flop circuit 11. This AND circuit 17 is input to the clock input terminal CP of the shift register 15. This shift register 15 is composed of n stages, and the signals from the output terminals Qn of the n stages are inputted to the reset terminal R of the pulse number detection circuit 5 via the OR circuit 18. Further, the output signal of the output terminal Q ₃ of the pulse number detection circuit 5 is input to the AND circuit 19, the output signal of the output terminal Q ₄ is input to the AND circuit 19 via the inverter circuit 20, and further this AND circuit The output signal of the inverter circuit 13 is input to 19. The output signal of this AND circuit 19 is input to the OR circuit 18. Further, the output signal of the inverter circuit 20 is inputted to the other of the AND circuits 6 via the OR circuit 14.

Next, the operation of this invention will be explained. Now, the synchronization signal transmitted from the transmitting facsimile passes through the limiter amplifier 1, the waveform shaping circuit 2, and the synchronization differentiator circuit 3 in order, and is converted into a rectangular synchronization signal containing the noise signal N as shown in FIG. 2A. It is input to circuit 6. At this time, the pulse number detection circuit 5 is cleared, and the signal at its output terminal Q ₄ is inverted by the inverter circuit 20 to become "1" and is input to the AND circuit 6. Therefore, the synchronization signal is transmitted to the AND circuit 6 and the delay circuit 7.
is input to the counter 8 via the counter 8 to reset the counter. Further, the synchronization signal is also input to the pulse number detection circuit 5, and a state is reached in which a signal "1" is outputted to the output terminal _Q1 . Next, when the second synchronization signal is output from the synchronization differentiator 3, a "1" signal is output to the output terminals Q ₁ and Q ₂ of the pulse number detection circuit 5, and the latch circuit 10 outputs the count of the counter 8. After the numerical value is stored, the count value of the counter 8 is reset. The first and second synchronizing signals are also input to the flip-flop circuit 11, but since the output of the comparator circuit 9 is "0" in the initial state, the flip-flop circuit 11 remains in the reset state. , therefore, no synchronizing signal is derived from the AND circuit 4. Next, assuming that the third synchronization signal is input with exactly equal pulse intervals,
At this point, the output of the comparator circuit 9 is "1",
The flip-flop circuit 11 is set by this signal. Therefore, a set output signal is outputted to the AND circuit 4 as shown in FIG. 2B, and a synchronization signal is derived as shown in FIG. 2C. If the third signal is noise and has a different interval from the previous two synchronization signals, the flip-flop 1
1 cannot be obtained, so the pulse number detection circuit 5 is reset by the signal from the AND circuit 19, and the above-described operation is repeated from the beginning.

After the periods of the three synchronization signals mentioned above completely match, even if the noise signal N is input, the set output signal from the flip-flop circuit 11 is not output from the OR circuit 1.
4 is not input to the AND circuit 6, and therefore the counter 8 is not reset. This counter 8 is reset only when a synchronizing signal is output from the synchronous differentiating circuit 3 at the time when the matching signal "1" is being output from the comparing circuit 9. Only this synchronizing signal is sent out from the AND circuit 4.

Further, the shift register 15 stores the number of mismatches, and when the number of mismatches reaches a predetermined value n, the pulse number detection circuit 5 is reset to restart the above-described detection operation. This circuit sets the interval in the latch circuit 10 even if three or more noises with exactly the same period arrive during a detection operation, but it is possible that many such noises come with the same period. As a result, when the number of mismatches in the shift register 15 reaches n, the latch circuit 1
This is for resetting the count value of 0.

As explained above, according to the present invention, a pulse signal is detected, a count value corresponding to the interval of the pulse signal is automatically set in the storage means, and thereafter, a pulse signal is generated at an interval equal to the interval relative to the count value. Since only the pulse signal is derived, there is an advantage that noise mixed in the pulse signal can be completely removed and only the necessary pulse signal can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention;
Figure 2 is a time chart. 5... Pulse number detection circuit, 15... Shift register, 7, 16... Delay circuit.

Claims (1)

[Claims] 1. A counter that is counted by a clock signal and is connected to a transmission line that transmits a pulse signal with a longer period than the clock signal and that is reset each time the pulse signal is input; a storage means for storing a counted value, and each time a pulse signal is detected on the transmission line, a detection operation is performed between the counted value of the counter and the counted value in the storage means, and when the two do not match; a detection circuit that outputs a mismatch signal to the counter; a first gate circuit that cuts off input of a pulse signal for resetting the counter when the mismatch signal is introduced; and a second gate circuit for prohibiting transmission of the pulse signal.