JPH0255814B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a cache store method in an information processing apparatus having a cache memory, and particularly to a store method in the cache memory when a cache miss occurs when a store swap method is adopted. Conventionally, information processing devices equipped with a cache memory store frequently used portions of information in the main memory in the cache memory in blocks to speed up processing. If it is detected that the information is not registered in the cache, there is a method in which the information is stored only in the main memory without being registered in the cache. This conventional method has the disadvantage that new data is not registered in the cache, resulting in a cache miss when the stored data is subsequently referenced, reducing the cache hit rate. Also known is a memory swap method (see Information Processing Vol. 1.21 No. 4pp336) in which a block is stored only in the cache and the main memory is updated only when the block is deleted from the cache.
In this case, when a cache miss is detected at the time of a store request, a block containing the store address is read out from the main memory to the cache and then stored in the block of the cache. This requires a block transfer from the main memory to the cache, which has the disadvantage that access to the cache is severely restricted during that time. Particularly, when store requests are made consecutively, the performance deteriorates significantly. The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
A device with a large capacity cache (for example, about 1/10 of the main memory capacity), which can be used satisfactorily even when a large amount of data is to be stored continuously (for example, a move long instruction). To provide a cache store method that reduces the required time by minimizing transfer from a main storage device when a mishit occurs and storing to a cache. Note that since this method is based on a memory swap method, the cache rate does not decrease. The present invention provides a system that, when a cache mishit occurs in a plurality of information processing apparatuses each having a cache memory for holding a portion of data in a shared main storage device in block units, an information processing apparatus among the plurality of information processing apparatuses In the cache store method, in which data at consecutive addresses in the shared main storage device is transferred and stored in the cache memory of It is characterized by omitting the transfer of all or part of the intermediate block data sandwiched between the blocks. Next, the present invention will be explained in detail with reference to the drawings. The figure is a block diagram showing one embodiment of the present invention. That is, it has interfaces 1 to 4 with a store request source (for example, an arithmetic control unit, etc.) and interfaces 5 to 9 with a main storage device. A request code is input from the store requester through the interface 1, and at the same time, a store start address is input into the interface 2. Also interface 3
request code 1 with the location of the write byte
One word (8 bytes) of data is input per write data buffer 70 and stored in the write data buffer 70. The request code input from the interface 1 is held in the request code register 30 via the buffer register 20. In this embodiment, in order to minimize the number of transfers from the main memory, the request code includes a cache store flag bit CSF indicating that even a cache miss will cause a write to the cache memory, and a series of cache store flag bits CSF. It includes a store start flag bit SSF indicating the start of a store operation and a store end flag bit SEF indicating the end of the store. Further, the start address (logical address) input from the interface 2 is held in the request address register 21 and then converted into a physical address by the address conversion buffer 22 and held in the request address register 31. The transfer count determination circuit 40 determines the store start flag bit SSF of the request code register 30 and the word address within the block of the request address register 31 (in this embodiment, the block size of the cache is 32 bytes, so the lower 5 of the address)
The number of transfers is determined by referring to the upper two bits. When transferring 8 bytes at a time, the relationship between the intra-block word address and the number of transfers is as shown in Table 1.

[Table] The number of transfers is given to the block transfer control 41 and held. On the other hand, the block transfer control 41
The cache store flag bit CSF and the store start flag SSF are both “1”, and
The comparator circuit 51 compares the output of the cache directory 50 and the output of the request address register 31, detects a mishit, and sets the control line 503 to "1".
When set to , a block transfer is requested to the main storage device via the interface 7. At this time, the block transfer address is sent from the request address register 31 to the main memory via interfaces 8 and 9. Data read from main memory (8 bytes each from the beginning of the block)
is input to the selection circuit 71 via the interface 6. Further, the reply signal is inputted to the block transfer control 41 via the interface 5. The block transfer control 41 counts the number of reply signals, compares it with the number of transfers given from the transfer count determination circuit 40, and reports the presence or absence of one sheet to the cache memory write control 80. The cache memory write control 80 controls the selection circuit 71 to write the reply data (8 bytes) from the interface 6 to the cache memory 60 until the number of reply signals matches the number of transfer instructions. . When the number of reply signals matches the number of transfer directions, that is, at the time of final transfer, the data in the write data buffer 70 and the reply data from the main storage device are transferred to the write byte position designation 70-1. The selection circuit 71 is controlled to write into the cache memory 60 in correspondence with each instruction bit. The selection of data to be written into the cache memory by the selection circuit 71 is as shown in Table 2.

[Table] In other words, one word (8 bytes) from the beginning of the block including the store start address is transferred from the main memory and written to the cache memory 60, and at the final transfer, the data is transferred in response to the write byte position specification. Transfer data or data from the write data buffer 70 is written as shown in Table 2. Next, the request code in which the cache store flag bit CSF of the request code from the request source is "1" and the other flag bits are "0" (the above-mentioned request code in which the store start flag bit SSF is "1") is ), the request code is stored in register 30 and the request address is set in request address register 31. At this time, the block transfer control 41 does not issue a transfer request even if there is a cache miss. Then, the memory write control 80 is notified through the control line 403 that the selection circuit 71 selects the write data from the write data buffer 70 and writes it into the cache memory 60. Therefore, for requests other than the first and last (in the middle) of a series of store operations, the same operation is performed whether the request is a cache miss or a cache hit. Finally, when the last request code of the series of consecutive store requests is set in the request code register 30, the cache store flag bit CSF of the request code is "1", and the store end flag bit SEF is set to "1". Since it is “1”, the transfer count determination circuit 40 determines that the request address register 31
The number of transfers is determined by referring to the word address within the block (upper 2 bits of the lower 5 bits) according to Table 3 below.

[Table] The number of transfers is given to the transfer control 41 and held, but if the cache store flag bit CSF and the store end flag bit SEF of the request code register 30 are both "1", and the cache directory 50 The output of the request address register 31 becomes valid only when a mishit is detected by the comparison/determination circuit 51. The transfer control 41 determines the validity, and when it is valid,
A transfer request is issued to the main storage device via the interface 7. At this time, the requested address is sent from the requested address register 31 to the main storage device via the interfaces 8 and 9. From the main memory, the words (8 bytes) in the block containing the address are sent as reply data to the selection circuit 71 via the interface 6, and are transferred word by word one after another. Further, the reply signal is input to the transfer control 41 via the interface 5. The transfer control 41 compares the number of transfer instructions held and the number of reply signals. If it is the first reply signal, it is reported to the cache memory write control 80, and the cache memory write control 80
controls the selection circuit 71 to select the data W in the write data buffer 70 holding the write data from the request source according to the write byte position designation 70-1 and write it into the cache memory 60; Transfer data M from the main storage device is selected and written into the section. Write byte position specification (8 bits)
The relationship between and the output (8 bytes) of the selection circuit 71 is shown in Table 4 below.

【table】

Claims (1)

[Claims] 1. When a cache mishit occurs in a plurality of information processing apparatuses each having a cache memory for holding a portion of data in a shared main memory in units of blocks, the cache of one of the plurality of information processing apparatuses is In the cache store method, which transfers and stores data at consecutive addresses in the shared main storage device to memory, two blocks of data including the start address and end address of the store request are transferred, and the block data sandwiched between these two blocks of data is transferred. A cache storage method characterized by omitting the transfer of all or part of intermediate block data.