JPH0255979B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission system that ensures the reliability of transmitted data in a data transmission device such as a data way. In general, the reliability of transmitted data in data transmission equipment is required to be extremely high. Therefore, error control methods such as the CRC (Cyclic Redundancy Check) method, which is resistant to noise, are adopted. I try to ensure sex.

FIG. 1 is a block diagram showing such a conventional data transmission device and an example of its connection configuration, and FIG. 2 is a configuration diagram showing an example of a transmission data frame.

In FIG. 1, i, j, and k indicate data transmission equipment, which respectively include a controller 1 that determines transmission frames, starts transmission/reception operations, and performs termination control; a data memory 2 that stores transmission frames; , a data bus 3, transmission sections 4-1 and 4-2, etc., which perform transmission control and reception control based on instructions from the controller 1. Note that 5 is a transmission path. Furthermore, since data is transmitted bidirectionally, each of the transmitting sections 4-1 and 4-2 has a transmitting section and a receiving section. In FIG. 2, F is a flag, A is an address field, C is a command field, I is a data field, and FCS is a frame check code field such as a cyclic redundancy check (CRC).

The transmission units 4-1 and 4-2 are further configured as follows.

FIG. 3 is a block diagram showing the detailed configuration of the transmission section. Note that this figure shows the case where data is transmitted from, for example, data transmission device i to j in FIG. , only the receiving section R is shown. In the same figure, T1 is a transmission control section;
2 is a transmission buffer register, T3 is a parallel-to-serial converter, T4 is a CRC generator, T5 is a transmission driver, T6 is a switch, and T7 is a flag generator.
is formed. On the other hand, R1 is a reception control section, R2 is a reception buffer register, R3 is a serial-to-parallel converter, R4 is a CRC checker, and R5 is a reception receiver, and these form the reception section R of the data transmission device j. be done.

The data transmission operation from data transmission device i to j will be explained based on FIGS. 1 to 3.

In FIG. 1, controller 1 of transmission device i
When it learns of the existence of a transmission frame addressed to transmission device j, it issues an activation command to transmission section 4-2 or transmission control section T1 in transmission section T via data bus 3.
The transmission control unit T1 sequentially takes out data from a designated area of the data memory 2 and sets it in the shift register T3 via the buffer register T2.
The shift register T3 shifts data bit by bit under the control of the transmission control section T1, converts the parallel data into serial data, and sends it to the transmission line 5 via the switch T6 and the driver T5. The order of sending data is F, A, C, I, as shown in Figure 2.
FCS,F, where F is from flag generator T7, A,
C and I are from shift register T3, and FCS is
CRC generator T4 to switch T6 respectively
The transmission control section T1 performs gate control to send out the signal.

On the other hand, the data from the transmission path 5 is received by the receiver R5, and the reception control unit R1 detects the flag F.
converts the serial data into parallel data in the shift register R3, and sequentially stores the data in the area of the data memory previously instructed by the controller 1 of the data transmission device j via the buffer register R2. Then, after detecting the last flag F of the transmission frame, the reception control unit R1 performs error tests such as checking the frame size and CRC, and if this is correct, it informs the controller 1 of the existence of the received frame. Inform. Thereafter, the controller 1 requests the transmission control unit T1 to send a response frame. Upon receiving a response frame from data transmission device j, the reception control unit of port (data transmission device) i identifies the transmitted response frame and transmits it to controller 1. The controller 1 confirms this and ends the normal transmission operation of the transmission frame. In addition, CRC generator T4, check R
Regarding the operation of 4, for example, the JIS standard (JISC6363
-1978).

In the transmission device configured as described above, noise in the transmission line,
Regarding malfunctions of transmission circuits such as drivers and receivers, missed errors are suppressed to an extremely small level by CRC checks and the like, so there is no problem at all in practice. However, the above-described CRC check is completely powerless against malfunctions of buffer registers, shift registers for serial/parallel conversion, etc. on both the transmitting and receiving sides. Therefore, as a countermeasure against malfunctions of these buffer registers and shift registers, a parity check in byte or word units can be considered, but as the circuit becomes bulky and the transmission circuit becomes high-speed, the probability of malfunction increases and the error detection ability increases. There was a problem in that the value decreased. In other words, from the perspective of transferring data from one data memory to another, the transmission operation is "OK" (no errors), but the contents of the data memory itself are incorrect. The problem is that there are cases where there is a problem, and this cannot be checked using the method described above.

The present invention aims to eliminate the above-mentioned drawbacks by ensuring not only data reliability in a transmission system but also data reliability at the content level of a data memory.

In summary, the present invention consists in installing an error control circuit such as a CRC in a data memory section in order to ensure reliability of data at the data memory level.

FIG. 4 is a block diagram showing an embodiment of the present invention. In the figure, 21 is a control circuit for the data memory 2, 22 is a memory element, 23 is a memory read gate, 24 is a data receiver of the memory, and 25 is a memory element.
CRC generator, 26 is a CRC data transmission gate, 27 is a CRC checker, 28 is a read gate of the CRC checker, G1 to G3 are gate signals,
WE is a control signal. FIG. 5 is a block diagram showing a transmission frame according to the present invention. As is clear from the figure, the difference from Figure 2 is that the data section I is divided into a pure data section D and frame check information IFCS (inner frame check sequence) up to A, C, and D. be.

The data transmission operation between data transmission devices i and j will be explained based on FIGS. 1, 4, and 5.

The controller 1 of the transmission device i in FIG. 1 sets the CRC generator 25 to the base (initial) state via the memory control section 21 prior to starting transmission to the transmission section 4-2. The transmission control section T1 of the transmission section 4-2 sequentially takes out the data of the memory element 22 in the order of A, C, and D through the memory read gate 23 via the memory control section 21. The CRC generator 25 takes in data word by word each time the memory read gate 23 operates, and performs a CRC operation. The CRC generator 25 is composed of an arithmetic circuit using a serial arithmetic method, etc., exactly the same as the transmitter T shown in FIG. 3, but it is different from the conventional example shown in FIG. The feature is that data is imported in parallel for comparison. When the transmission control unit T1 of the transmission unit 4-1, 4-2 reads the data length of the transmission frame and finishes reading the data part D, the transmission control unit T1 of the transmission unit 4-1, 4-2
1, sends a command to read the contents of the CRC generator 25 and performs an inner frame check sequence.
Reads the IFCS, performs parallel to direct conversion, and sends it to the transmission line. The operation of sending out FCS and F is exactly the same as in the conventional example.

Next, the operation on the receiving side will be explained. The controller 1 of the transmission device j in FIG.
The CRC checker 27 is set to the base (initial) state. The reception control unit R1 of the transmission unit 4-1 sequentially stores data A, C, and D in the order of data A, C, and D via the memory control unit 21 and the receiver 24. CRC checker 27 is memory element 22
Each time the data storage signal WE is activated, the data is taken in word by word and a CRC calculation is performed.
The CRC checker 27 is composed of an arithmetic circuit of the same serial arithmetic type as that of the receiving section R. The receiver controller 1 includes a receiver controller R1.
In response to a signal indicating the existence of a transmission frame, the contents of the CRC checker 27 are read out via the memory control unit 21 and read out through the read gate 28, and after confirming that the contents are at a predetermined value, the response frame is sent to the transmission device. Send to i.

Furthermore, internal frame check sequence IFCS
is constructed using CRC, but it can also be constructed using SUM, the cumulative sum of data.
The operation of the checker 27 in this case is as follows:
Instead of taking the sum when receiving the IFCS, either hold it as is and check the match using hardware, or controller 1 can read out both the cumulative sum up to the IFCS and the IFCS and check the match. By doing so, data reliability at the data memory level can be ensured.

As described above, according to the present invention, a frame check sequence generator and a checker are installed in the data memory, and when transmitting a frame, a frame check sequence is generated based on the data in the data memory. When receiving a frame, the frame check is executed using the data itself stored in the data memory, so the reliability of data at the data memory level can be ensured, and therefore it is industrially easy to use. It can be said that its utility value is extremely high. That is, it is possible to detect not only malfunctions of buffer registers and shift registers for both transmission and reception, but also data errors due to transfer errors on the data bus 3 shown in FIG. 1 and malfunctions of the receiver and driver of the data memory 2. Furthermore, when malfunctions due to noise in the transmission system are small and data error detection by the transmission system itself is unnecessary, error control at the data memory level according to the present invention is sufficient, making it possible to reduce hardware. . In addition,
When performing CRC code generation and checking using a serial calculation method, the operating speed is required to be equal to or higher than the operating speed of the transmission system, so there is a concern that data errors will increase if high-speed operation is performed. However, by using a synchronous clock, extremely stable operation can be achieved compared to a clock with a large amount of jitter in the transmission system. In addition, compared to the case where a parity bit generation and check circuit is provided in the buffer register and shift register of the transmission section, the amount of metal is only slightly increased in the case of the CRC method, and compared to the case of providing a parity bit generation and check circuit in the buffer register and shift register of the transmission section. In this case, it can be made smaller than the CRC method, so
Increased costs are not a problem.

Note that the present invention is applicable not only to the serial transmission transmission device described above, but also to parallel transmission transmission devices, and is not limited to data transmission devices, but can also be applied to transfer data from one storage device to another storage device. The present invention is applicable to devices having various data exchange functions for transferring data to other devices.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional transmission system, Fig. 2 is a block diagram showing an example of a transmission data frame, Fig. 3 is a block diagram showing details of the transmission section in Fig. 1, and Fig. 4 is a block diagram showing the present invention. FIG. 5 is a block diagram showing a transmission data frame according to the present invention. Description of symbols 1...Controller, 2...Data memory, 3...Data bus, 4-1, 4-2...Transmission unit,
5... Transmission line, 21... Memory control circuit, 22... Memory element, 23, 26, 28... Gate, 24, R5
...Receiver, 25, T4...CRC generator,
27, R4...CRC checker, T1...reception control unit, T2...transmission buffer register, T3...parallel-
Series converter, T5...driver, T6...switcher, T
7...Flag generator, R1...Reception control unit, R2...Reception buffer register, R3...Serial-parallel converter,
F...flag, A...address, C...command, D...
Data, IFCS...internal frame check sequence, FCS...frame check sequence, G1~
G3...Gate signal, WE...Control signal.

Claims (1)

[Scope of Claims] 1. A data memory, a transmitting means for configuring data read from the memory into a frame with a check code for detecting a transmission error and transmitting the frame, a frame receiving means, and a check code in the received frame. and a means for writing the data in the frame into the memory after confirming that there are no transmission errors, and a plurality of data transmission devices that perform error control at the transmission path level are coupled by a transmission path. In a data transmission system that performs data transmission using a data transmission system, the data memory of each data transmission device includes a memory element, a check code generator, and a check code checker, and when outputting data, the data read from the memory element is A check code generated from the check code generator is added to the input data, and when data is input, the check code added to the input data is checked by the check code checker before being stored in the memory. A data transmission system characterized in that error control is performed even at the memory content level by writing to an element.