JPH0258821B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is a method for transmitting or storing digital data by randomizing it, that is, a scrambling method (or descrambling method).
The present invention relates to a code conversion device. There are various purposes for scrambling, but one is that even if the data is stolen on the transmission or storage medium, the information remains confidential because the original information is randomized. There is a point to gain.

Conventionally, a widely known method for such scrambling is to place a scrambler using a so-called feedback shift register on the transmitting side and a descrambler using a so-called feed forward shift register on the receiving side. It is being In this system, the way the feedback or feedforward is connected is used as a key for decoding the transmitted information data.

For convenience of explanation, an example of a conventional method is shown in FIG.

In FIG. 1, 51 is a transmitting point, 52 is a scrambler, 53 is a transmission or storage medium, 54 is a descrambler, 55 is a receiving point 56, 56' is a four-stage shift register, 57, 57' are bits. The pattern converters 58, 58' are modulo-2 adder circuits. The feedback function f _i that defines the bit pattern converters 57 and 57' is based on a predetermined 16-bit code pattern f _i =(f _i
(0), f _i (1), ..., f _i (15). That is, considering the 4-bit pattern in the shift register as a binary number, if the number is a, then
The bit pattern converters 57, 57' convert bit f _i
Output (a). In FIG. 1, data flows in the direction of the arrow.

As can be easily seen from Figure 1, in the conventional scrambling method, a scrambled data stream that is streamed onto a transmission or storage medium and a data stream that is fed into a shift register of a scrambler are separated. Because they are the same, it is easy to estimate the feedback function f _i from the scrambled data string, and in order to maintain the confidentiality of information, when using the conventional method described above, it is necessary to make it easy to decipher to some extent. I had to prepare myself.

An object of the present invention is to eliminate the drawbacks of the conventional scrambling method described above, and to make it difficult to easily determine the correspondence between a scrambled data string and data held in a shift register in a scrambler. Therefore, we propose a code conversion device as a scrambler or descrambler that reduces the risk of being decoded.

According to the present invention, the transmitting side includes an encoding device for scrambling a transmission digit string, and the receiving side includes a decoding device for decoding a received digit string and restoring the transmission digit string. In the conversion device, the encoding device is composed of a plurality of cascade-connected code conversion blocks, and each code conversion block converts a part of the output of the subsequent code conversion block into
However, the regroup code conversion block uses one or more shift registers that take part of its own output as an input bit string, and converts the bit patterns stored in the one or more shift registers into predetermined bit patterns. Accordingly, a bit pattern converter converts the bit pattern into a conversion bit corresponding to the bit pattern, and a predetermined combination modulo 2 for the conversion bit and one or more input bits to the code conversion block. and a combinatorial addition circuit that performs addition in the code conversion block; However, the code conversion block at the first stage uses one or more shift registers that take part of its own input as an input bit string, and converts the bit patterns stored in the one or more shift registers into the respective predetermined code patterns. Accordingly, a bit pattern converter converts the bit pattern into corresponding conversion bits, and converts the bit pattern into a conversion bit corresponding to the bit pattern, and converts the conversion bits and one or more input bits to the code conversion block into 2 in each predetermined combination. A code conversion device is obtained, which is characterized by comprising a combinatorial addition circuit that performs modulo addition. In the present invention, each data is considered to be represented as a digit consisting of one or more bits.

The present invention will be explained in detail with reference to the drawings.

Figures 2, 3, 4, 5, and 7 are
FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 2, reference numeral 1 indicates a combinational circuit consisting of modulo-2 adder circuits 114, 15, 16, and reference numeral 2 indicates shift registers 3, 4, 5.
The bit pattern stored in the bit pattern is converted into three conversion bits c _t , corresponding to the bit pattern according to predetermined code patterns f ₁ , f ₂ , f ₃ .
A bit pattern converter that converts d _t and e _t is shown.
Note that the conversion bits c _t , d _t , and e _t are as follows at time t:
These are the bits output from the bit pattern converter 2, and are output via lines 8, 9, . . . 10, respectively.

Now, at time t, the input information bit a _t inputted to the combinational circuit 1 from the input line 6 is added to the conversion bit e _t in the modulo-2 addition circuit 14 in the combinational circuit. is converted into an addition result b _t which is sent via line 7 onto a transmission or storage medium and at the same time is sent via line 11 to shift register 3.

In this embodiment, the bit pattern converter 2 is composed of three bit pattern converters corresponding to each of the shift registers 3, 4, and 5. The bit patterns that are displayed are changed according to predetermined code patterns f ₁ , f ₂ , and f ₃ , respectively.
The bits are converted into the conversion bits c _t , d _t , and e _t corresponding to the respective bit patterns. As is conventional, the bit pattern converter can be easily realized using a read-only memory or a random access memory. Now, the conversion bit c _t ,
d _t and e _t are input to the combinational circuit 2, but the conversion bits c _t and d _t are input to the 2 in the combinational circuit 1, respectively.
The addition circuits 15 and 16 modulo the output bit b _t and the addition results f _t and g _t are
These become input bits to the shift registers 4 and 5, respectively.

As explained above, in the embodiment shown in FIG. 2, the column of sending bits _bt does not appear directly in the shift registers 4 and 5, but the information bits are extracted only from the column of _bt .
Estimating the sequence of a _t is based on the code patterns f ₁ , f ₂
and is difficult unless you know f ₃ . Therefore, if predetermined code patterns f ₁ , f ₂ , f ₃ are used as decryption keys, the code conversion device shown in FIG. 2 can be used for information secrecy.

FIG. 3 is a diagram showing a code conversion device on the receiving side that converts the data _string scrambled by the code conversion device of FIG. This is an example. In FIG. 3, the same numbers as in FIG. 2 indicate blocks or circuits having the same functions.

Therefore, if the string of bits b _t output from the code converter of FIG. 2 is inputted from the input line 20 in _{FIG .} , e _t are output, and the combinational circuit 1
It is clear that the data is input to Therefore, in the modulo-2 addition circuit 14 in the combinational circuit 1, the bits b _t and e _t are added. However, as explained in FIG. 2, since a _t ○+e _t =b _t , b _t ○+e _{t =} at, and the input information bit _at is restored and output from line 21.

Therefore, FIG. 3 is certainly a descrambler when the code conversion device of FIG. 2 is used as a scrambler.

FIG. 4 shows another embodiment of the invention. In Figure 4, reference numbers 1', 2', 3', 4', 5', 6',
7', 8' are 1, 2, 3, 4, in Figure 2
Indicates that it has the same role function as 5, 6, 7, and 8.

First, the reference number 1' is the adder circuit 1 modulo 2.
8 and 19, the reference numeral 2' converts the bit patterns stored in the shift registers 3', 4', 5' into predetermined code patterns f ₁ ', f ₂ '. Accordingly, a bit pattern converter is shown which converts the bit pattern into two conversion bits c _t ', d _t ' corresponding to the bit pattern. Note that the conversion bits c _t ' and d _t ' are bits output from the bit pattern converter 2' at time t, and are output via lines 8'17, respectively.

Now, at time t, the information bit a _t ' inputted to the combinational circuit 1' from the input line 6' is added to the conversion bit d by modulo-2 adder circuits 18 and 19 in the combinational circuit. It is converted into an addition result b _t ' by being added with _t ′ and c _t ′, and is sent to the transmission or storage medium via line 7 ′, and at the same time is sent to the shift register 3 ′ via line 11 ′. will also be sent.

In this embodiment, the bit pattern converter 2' is composed of two bit pattern converters corresponding to a register 3' and registers 4' and 5', respectively. The bit patterns stored in bit patterns 4' and 5' respectively correspond to the bit patterns c _t ' and f 2 ' according to predetermined code patterns f ₁ ' and f ₂ ', respectively.
It is converted to d _t ′. Furthermore, the conversion bit c _t ' is input to the shift registers 3' and 4'.

Now, the conversion bits c _t ' and d _t are sent to the combinational circuit 1', and as mentioned above, the conversion bits c t ' and d t are respectively sent to the modulo-2 addition circuit 18 in the combinational circuit 1'.
and 19, and a _t ′○+c _t ′○+d _t ′=b _t ′ is output from the combinational circuit.

In the example of FIG. 4, the sequence of transmitted bits b _t ' is also
It is difficult to estimate the sequence of information bits at _' from the sequence of transmitted bits b _t ', which do not appear directly in shift registers 4 and 5, unless the code patterns f ₁ ' and f ₂ ' are known. Therefore, the predetermined code patterns f ₁ ′ and f ₂ ′ are used as keys for decoding.
If used as a code converter, the code converter shown in FIG. 4 can be used for information secrecy. FIG _. 5 is a diagram showing a code conversion device on the receiving side that converts the data string scrambled by the code conversion device of FIG. This is a block diagram showing one embodiment. Components having the same numbers as in FIG. 4 are blocks or circuits having the same functions.

Therefore, in FIG. 5, from the input line 30,
When the string of bits _{b t} output from the code _converter shown in FIG. That is clear.

Therefore, the input bit b _t ' passes through the modulo-2 adder circuits 19 and 18 in the combinational circuit 1', and then becomes b _t '
○+c _t ○+d _t ' and is outputted via line 31. However, as explained in Figure 4, a _t ′○+d _t ′○+
Since c _t ′=b _t ′, b _t ′○+c _t ′○+d _t ′=a _t ′.

Therefore, the information bit a _t ' is reliably restored, and the circuit shown in FIG. 5 serves as a descrambler when the code converter shown in FIG. 4 is used as a scrambler.

Next, FIG. 6 shows still another embodiment of the present invention. Reference numbers 1″, 2″, 3″, 4″, 5″, 6″,
7″, 8″, 9″, 10″, 11″, 12″, 13″,
6, 7 are reference numbers 1, 2,
3, 4, 5, 6, 7, 8, 9, 10, 11, 1
Indicates that it has the same role function as 2 and 13.

First, the reference numeral 1'' is an adder circuit 22 modulo 2,
23, 24, 25, 26, 27 and 28, the reference numeral 2'' converts the bit patterns stored in the shift registers 3'', 4'' and 5'' into a predetermined code pattern f. ₁ '', f ₂ '', f ₃ '' into three conversion bits c _t '', d _t '' and e _t '' corresponding to the bit pattern. The conversion bit
c _t ″, d _t ″ and e _t ″ are lines 8″, 9″, 1 respectively
0'' to the combinational circuit 1'.

Now, at time t, the information bit a, which is one of the information digits (a _t ″, a _t ) inputted from the input line 6 to the combinational circuit 1'
is added to the conversion bit e _t ″ in the adder circuit 22 modulo 2 in the combination circuit, and the bit b _t
It is sent via line 7 onto a transmission or storage medium. The bit b _t is also supplied to the adder circuits 24 and 27 at the same time.

Furthermore, another information bit a'' is the combinational circuit 1''.
Addition circuits 23, 24, 26, 2 modulo 2 of
At step 8, the conversion bit e _t '', the sending bit b _t '', and the conversion bits d _t '' and c _t '' are added together to form a bit b _t '', which is transmitted via line 7''. The bits b _t on a transmission or storage medium
Sent with The bit b _t '' also serves as an input bit to the shift register 3'' at the same time.

Note that in the modulo-2 addition circuit 27, the conversion bit c _t '' and the sending bit b _t are added together, and the addition result f _t '' is input to the shift register 4'', and In the adder circuit 25 modulo 2, the conversion bit d _t '' and the sending bit b _t are added together, and the addition result is
g _t '' is an input to the shift register 5''.

In the example shown in FIG. 6, the set of transmitted bits, that is, the column of digits (b _t ″, b _t ), does not appear directly in shift registers 4 ″ and 5 _{″ ;} ), the information digits (a _t ″, a _t
) is the code pattern f ₁ ″,
It is difficult unless you know f ₂ ″ and f ₃ ″. Therefore, if predetermined code patterns f ₁ '', f ₂ '' and f ₃ '' are used as decryption keys, the code conversion device shown in FIG. 6 can be used for information secrecy.

The code conversion device shown in Fig. 6 converts the scrambled data string into the original information digits (a _t ″, a _t ).
FIG. 7 is a diagram showing a code conversion device on the receiving side that converts the data into a sequence of . Components having the same numbers as in FIG. 6 are blocks or circuits having the same functions.

Therefore, in FIG.
1, if the digits (b _t '', b _t ) output from the code conversion device of FIG.
It is clear that c _t ″, d _t ″ and e _t ″ are outputted and fed into the combinational circuit 1″.

Therefore, in the adder circuit 22 modulo 2 in the combinational circuit 1'', the input bit b _t and the conversion bit
e _t ″ are added together, and the addition result b _t ○+e _t ″ is outputted via line 43.

However, as explained in the code conversion device of FIG. 6, since a _t ○+e _t ″=b _t , b _t ○+e _t ″=a _t
Thus, the information bit at _' ' is certainly restored.

Furthermore, the input bit b _t ″ passes through the modulo-2 addition circuits 28, 26, 24, and 23 in the combinational circuit 1″, and then becomes b _t ″○+c _t ″○+d _t ″○+b _t 〇e _t ″
is output via line 42. However, as explained in Figure 6, a _t ″○＋e _t ″○＋b _t ○＋d _t ″○＋
c _t ″=
Since b _t ″, b _t ″○+c _t ″○+d _t ″○+b _t ○+e _t ″=a _t ″, and the information bit a _t ″ has certainly been restored.

Therefore, the code conversion device shown in FIG. 7 functions as a descrambler when the device shown in FIG. 6 is used as a scrambler.

The configurations shown in FIGS. 2 to 7 can also be interpreted as follows. In FIG. 2, 121,
122 and 123 are the first, second and third code conversion blocks, respectively, and the lines are 124 and 125.
are connected in cascade. Further, the first code conversion block 121 inputs the output of the second code conversion block 122 at the subsequent stage to the internal register 5 via the line 13, and
22 inputs the output of the third code conversion block 123 at the subsequent stage to the internal register 4 via line 12, and inputs the output from the third code conversion block 123 at the final stage.
inputs its output to the internal register 3 via line 11. Also, the first, second, third
In each code conversion block 121, 122, 123, register 5, register 4, register 3
a bit pattern converter _f3 , which converts each bit pattern stored in the bit pattern into each conversion bit corresponding to each stored bit pattern according to a predetermined bit pattern;
f ₂ and f ₁ respectively, and the respective conversion bits are supplied via lines 10, 9, and 8, respectively, and lines 6, 124, and 1, respectively.
It has circuits 14, 16, and 15 for performing modulo-2 addition with input bits from 25, respectively. The output of circuit 14 is sent via line 124 to a second transcoding block 122, and the output of circuit 16 is sent via line 1.
3 to a first transcoding block 121, and the output of circuit 15 is fed via line 12 to a second transcoding block 122.

In FIG. 3, 131, 132, and 133 are first, second, and third code conversion blocks, respectively, and the third code conversion block 133, which is cascade-connected by lines 134 and 135, is the second code conversion block in the previous stage. The output of the conversion block 132 is input to the internal register 5 via line 136, and the second code conversion block 132 inputs the output of the first code conversion block in the preceding stage to the internal register via line 137. The code conversion block 131 at the first stage inputs the input to the internal register 3 via the line 11. or,
First, second, and third code conversion blocks 131, 1
At 32 and 133, each bit pattern stored in register 3, register 4, and register 5, respectively, is converted into each conversion bit corresponding to each stored bit pattern according to a predetermined bit pattern. bit pattern converters f ₁ , f ₂ , f ₃ respectively, each converting bit supplied via lines 8, 9, 10, respectively, and input bits from lines 20, 134, 135, respectively. It has circuits 15, 16, and 14 that respectively perform addition modulo . The output of circuit 15 is fed via line 137 to a second transcoding block, and the output of circuit 16 is fed via line 136 to a third transcoding block.
The output of 4 is connected via line 21 to the output of the decoding device.

In FIG. 4, 141 and 142 are the first and second code conversion blocks, respectively, and the line 14
They are cascaded through 3. Furthermore, the first code conversion block 141 inputs the output of the second code conversion block 142 at the subsequent stage to the internal registers 4' and 5' via line 44, and inputs the output from the second code conversion block 142 at the final stage to the internal registers 4' and 5'. inputs its output to the internal register 3' via line 11'. Moreover, the first and second code conversion blocks 1
41 and 142, registers 4' and 5', respectively.
Bit pattern converters f 2 ′, f ₁ that convert each bit pattern stored in the register 3 ′ into conversion bits corresponding to each stored bit pattern according to a _{predetermined} bit pattern. circuits 18 and 19, respectively, which perform modulo-2 addition of the respective conversion bits supplied via lines 17 and 8', respectively, and the input bits from lines 145 and 143, respectively; have The output of circuit 18 is sent via line 143 to the second transcoding block, the output of circuit 19 is provided via line 7' to the output of the encoding device, and at the same time as an input to itself via line 11'. and is supplied to the internal register 3'.

In FIG. 5, 151 and 152 are first and second code conversion blocks, respectively, and line 15
They are cascaded through 3. Furthermore, the second code conversion block 152 inputs the output of the first code conversion block 151 in the previous stage to internal registers 4' and 5' via line 154, inputs to itself via line 11' to internal register 3'. Further, in the first and second code conversion blocks 151 and 152, registers 3 and 3 are respectively stored.
A bit pattern converter f 1 ', which converts each bit pattern stored in the registers 4' and ₅ '' into conversion bits corresponding to the stored bit pattern, respectively, according to a predetermined bit pattern. circuits ₁₈ and 19 each having a modulo-two addition of each conversion bit supplied via line 8' and line 17 and input bits from line 30 and line 153, respectively; The output of circuit 19 is connected via line 31 to the output s of the encoding device.

In FIG. 6, 161, 162, and 163 are first, second, and third code conversion blocks, respectively, and lines 164, 165, 166, and 167 are connected in cascade. Furthermore, the first code conversion block 161 is connected to the second code conversion block 1 at the subsequent stage.
The output of 62 is input to the internal register 5'' via line 13'', and the second code conversion block 162 inputs the output of the third code conversion block 163 at the subsequent stage to the internal register via line 12''. 4'' and the third code conversion block 1 at the final stage.
63 inputs its own output via line 11'' to internal register 3''. Also, the first
Second and third code conversion blocks 161 and 16
In No. 2,163, each bit pattern stored in register 5'', register 4'', and register 3'' is converted into each conversion bit corresponding to each stored bit pattern according to a predetermined bit pattern. bit pattern converters f ₃ ″, f ₂ ″, f ₁ ″, respectively, for converting bit pattern converters f 3 ″, f 2 ″, f 1 ″, respectively, with the respective conversion bits supplied via lines 10 ″, 9 ″, 8 ″, respectively, and lines 6, 6, respectively.
6″, 6 lines 164 and 165, line 166
Combinational circuits 22, 23 and 24, 2 which perform addition modulo 2 of input bits from 167 and 167, respectively.
5 and 26, 27 and 28. circuit 22,2
The output of the combinational circuit consisting of 3 and 24 is on line 16.
4 and 165 to the second code conversion block 16
2, part of the output of the combinational circuit consisting of circuits 25 and 26 is routed to the first transcoding block via line 13'', and part of the output of the combinational circuit consisting of circuits 27 and 28 is routed to line 12''. and are respectively supplied to the second code conversion block.

In FIG. 7, 171, 172, and 173 are first, second, and third code conversion blocks, respectively, and the third code conversion block 173, which is cascade-connected by lines 174, 175, 176, and 177, is the previous stage code conversion block. The second transcoding block 172 of
The output of
2 is the output of the first code conversion block,
The code conversion block 171 at the first stage inputs the input to the internal register 4'' via the line 12'', and inputs the input to the internal register 3'' via the line 11. 1st, 2nd, 3rd
Each of the code conversion blocks 171, 172, and 173 converts each bit turn stored in register 3'', register 4'', and register 5'' into each stored bit pattern according to a predetermined bit pattern. A bit pattern converter f ₁ that converts into each conversion bit corresponding to
f ₂ and f ₃ respectively, and the lines 8″ and 8″ respectively.
9'', 10'' and lines 40, 41, 174 and 175, 1, respectively.
Combinational circuits 28, 27, and 25 that perform modulo-2 addition of the input bits from 76 and 177, respectively.
and 26, 22, 23 and 24. The output of the combinational circuit consisting of circuits 28 and 27 is sent to the second transcoder block via lines 12, 174 and 175, and the output of the combinational circuit consisting of circuits 25 and 26 is sent to the second transcoding block via lines 13'', 176 and 177. 2 and 3, respectively, and are supplied to circuits 23 and 2, respectively.
The output of the combinational circuit consisting of 4 is on lines 42 and 43
The signal is output from the decoding device via the .

As described in detail above, according to the present invention, a code conversion device and an inverse conversion device thereof are constructed in which it is difficult to easily estimate the original information data string from the data string on the transmission or storage medium. can do.

In the embodiment, the number of shift registers is limited to three for convenience of explanation, but it is clear that a configuration using a plurality of shift registers is possible. It is clear that it can be complicated.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a scrambler and a descrambler according to the conventional scrambling method, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6,
FIG. 7 is a block diagram showing a specific embodiment of the present invention. In the figure, 51 is a transmission point, 52 is a scrambler, 53 is a transmission or storage medium, 54 is a descrambler, 55 is a reception point, 3, 4, 5, 3',
4', 5', 3'', 4'', 5'', 56, 56' are shift registers, 2, 2', 2'', 57, 57' are bit pattern converters, 58, 58', 14, 15, 1
6, 18, 19, 22, 23, 24, 25, 2
6, 27, 28 are addition circuits modulo 2, 6, 2
0, 6', 30, 6'', 6, 40, 41 are input lines, 7, 21, 7', 31, 7'', 7, 42,
43 is an output line, 1, 1', 1'' is a combinational circuit of adder circuits modulo 2, 8, 9, 10, 11, 1
2, 13, 8', 11', 17, 8'', 9'', 10'',
11″, 12″, 13″ are lines through which data flows within the code converter, 121 to 123, 131 to 13
3,141,142,151,152,161～
163, 171-173 are code conversion blocks.

Claims (1)

[Scope of Claims] 1. The transmitting side has an encoding device that scrambles a digit string for transmission, and the receiving side has a signaling device that scrambles the received digit string and restores the digit string for transmission. In the decoding/converting device, the encoding device is composed of a plurality of cascade-connected code conversion blocks, and each code conversion block transmits a part of the output of the subsequent code conversion block, except for a part of the output of the code conversion block in the final stage. uses one or more shift registers whose input bit string is a part of its own output, and converts the bit patterns stored in the one or more shift registers into the bit patterns according to predetermined bit patterns. a bit pattern converter for converting into corresponding conversion bits; and a combinational addition circuit for performing addition modulo 2 in predetermined combinations of the conversion bits and one or more input bits to the code conversion block. and the decoding device is composed of a plurality of cascade-connected code conversion blocks, and further, each code conversion block receives a part of the output of the previous code conversion block, but the first code conversion block One or more shift registers whose input bit string is a part of its own input, and bit patterns stored in the one or more shift registers according to the respective predetermined code patterns. a bit pattern converter for converting into corresponding conversion bits; and a combinatorial addition for performing addition modulo 2 in the respective predetermined combinations on the conversion bits and one or more input bits to the code conversion block. A code conversion device comprising a circuit.