JPH026027B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an IC tester that tests the logic functions, AC characteristics, or DC characteristics of logic circuit systems such as ICs (integrated circuits) and IC boards, and in particular, The present invention relates to a logic circuit testing device that sets the temporal change state of a strobe signal every time a strobe signal is input, and compares and determines it with an expected pattern.

Conventionally, the detection system of this type of IC tester is
There are two methods for time measurement: an analog method that uses a sampling oscilloscope and a single-shot time measurement device, and a digital method that uses a latch circuit to detect the output signal of the IC under test. Analog methods that use sampling or single shots can only measure one logic path between pins from the input to output of the IC under test, but strobe methods measure many logic paths between several pins. It has been widely used since it can measure paths simultaneously.

The conventional strobe method is a method in which the state of the output signal of the IC under test is determined at predetermined time intervals using a strobe signal that is generated only once within the system lock cycle. This is shown in block diagram form in Figure 1a. A conventional strobe-type tester receives an input signal line 102 driven by an input drive circuit 101, executes a logical operation, and then outputs the result to an output signal line 103. A level comparator 20 to which the output signal line 103 of the measurement IC 10 and the reference voltage level input signal line 201 are connected, and the output signal line 20 of this level comparator 20
2 is connected to the strobe signal line 301, and the output signal line 302 of this latch circuit 30 and the reference logic signal line 401 are connected to the inputs, and the logic comparison of the two input signals from these is performed. It consists of a pattern comparator 40 that transmits the results to the test machine control system from an output signal line 402.

The conventional strobe type tester shown in FIG. 1a operates according to the timing diagram shown in FIG. 1b. Since the operation of the test machine is synchronized with the slow system clock 104, the input drive circuit 1
When the input signal 102 driven by 01 changes immediately after the rising edge of the clock pulse, the IC under test
10, the output signal 103 changes after a change in the input signal 102 by the delay time of the internal logic. In FIG. 1b, IC output signal 103 falls during the first clock period of single clock 104 and rises during the second clock period. The level comparator 20 is an IC under test.
10 output signal 103 is received, and a voltage level test is performed using a reference input signal 201 of a predefined voltage level. The latch circuit 30 is a single D-type flip-flop and is connected to the level comparator 20.
The logic 1 or 0 state of the output signal 202 of the strobe signal 301 latches at the moment the strobe signal 301 rises, as shown in FIG. 1b. In Figure 1b,
At the first rise time of the strobe signal 301, the IC output signal 103 is at a low level, so a low level signal is latched into the latch circuit 30, so that the output signal 302 of the latch circuit 30 is latched.
falls with a delay of the delay time of the latch circuit. Also, at the second rise time of the strobe signal 301, the IC output signal 103 is at a high level, so a high level signal is latched in the latch circuit 30, so that the output signal of the latch circuit 30 is delayed by the delay of the latch circuit. I'm standing up an hour late. The pattern comparator 40 receives the output signal 302 of the latch circuit 30 and outputs the output signal 302.
A functional test of the IC under test is performed by comparing the state of logic 1 or 0 with the state of a reference logic input signal 401 having a predefined expected pattern, and the result is outputted to the test machine as an output signal 402. control system.

However, the conventional IC tester described above can detect the temporal change state of the output signal of the IC under test only in the operating cycle of the system. Therefore, the conventional strobe method is not suitable for testing IC output signals whose temporal states change significantly. For example, when the switching delay time of each pin varies depending on the IC output, such as in a random logic IC, or when the IC If there is a hazard where the output signal temporarily transitions to another level, or if the IC
When the output signal is a chopper signal that changes in a pulsed manner, there is a drawback that it is impossible to perform an accurate inspection.

The present invention can simultaneously test many logic paths with different delay times from the input to the output of the IC under test in parallel, and by adding a high-speed buffer register driven by a high-speed strobe signal to the measurement system. at a speed several to several tens of times faster than the operating cycle of the machine.
To provide a logic circuit tester capable of performing a correct test even when the output signal of an IC under test changes rapidly by detecting the temporal change state of the IC output signal by capturing it in the register as it is in its waveform. With the goal.

The present invention is characterized by a tester for testing an output signal of a logic circuit under test that receives an input signal transmitted from a tester, executes a logical operation, and outputs a result, the tester comprising: a comparator connected to an output signal line and a reference voltage level input signal line for comparing the voltage level of the output signal of the logic circuit under test with a predetermined voltage level of the reference input signal; a high-speed buffer shift register that stores the digital signal from the comparator every time a strobe signal faster than the operating cycle of the test machine is inputted to determine the temporal change state of the output signal of the tester; and the high-speed buffer shift register. To provide a logic circuit tester comprising a pattern comparator for comparing whether the output of the tester matches an expected pattern of a predefined reference input logic signal in a slow operation cycle of the tester. It is.

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 2a, the detection system in the logic circuit tester of the present invention includes the input drive circuit 1
The output signal line 103 of the IC under test 10 and the reference voltage level input are connected to the IC under test 10, which receives an input signal 102 driven by 01 and executes a logical operation, and then outputs the result to the output signal line 103. a level comparator that receives a signal line 201; a high-speed buffer shift register 50 that inputs the output signal line 202 of the level comparator 20 at an input terminal 501 through a buffer circuit 502 and also inputs a high-speed strobe signal line 504; A selection circuit 60 selectively inputs the output signal line 503 of the buffer register 50 and the output signal line of the level comparator, and a selection circuit 60 connected to the output signal line 601 of the selection circuit 60 and also a comparison pattern input logic signal line 401. a pattern comparator 4 that inputs the input signals and transmits the results of logical comparison of the two input signals to the test machine control system from an output signal line 402;
Consists of 0.

In the tester of the present invention, a high-speed buffer resistor 50 is provided in the output detection system of the IC under test 10.
The temporal change state of the output signal of the IC is sampled at a specified time interval at high speed and stored in the high-speed buffer register 50. From then on, the pattern comparator 40 performs the sample processing in the low-speed tester operation cycle.
Refer to the status of the IC output signal Input logic signal line 401
The function is compared with the expected pattern to determine the function. The present invention uses a high-speed buffer shift register 5 to detect the time-varying state of the output signal of the IC under test, which can only be detected in the operating cycle of the test machine in the conventional strobe-based detection system.
By adding 0 to the detection system, the temporal change state of the IC output signal is stored in the register 50 as a 1 or 0 digital signal at a high speed several to several tens of times faster than the operating cycle of the test machine, and the N-bit strobe The analog output of the IC is digitized and outputted from the register 50 by shifting according to the signal, so that temporal changes in the IC output signal can be detected at high speed.

The embodiment of the tester of the invention shown in FIG. 2a operates according to the timing diagram shown in FIG. 2b. The detection system uses a slow system clock 104.
Therefore, when the input signal 102 of the IC driven by the input drive circuit 101 changes, the output signal 103 changes from the change in the input signal 102 to the internal logic delay time according to the internal logic of the IC under test 10. changes with a delay. In FIG. 2b, as an example of the IC output signal 103, an IC output signal indicated by A changes in level with a relatively short delay time interval in response to a change in the IC input signal 102, and an IC output signal indicated by A changes in level with a relatively long delay time interval. The IC output signal indicated by B and the chopper output signal indicated by C whose waveform changes in a pulse-like manner are shown. The level comparator 20 receives the output signal 103 of the IC under test 10 and receives a predefined reference voltage level input signal 2.
01 and perform a voltage level check. The high-speed buffer shift register 50 is an N-bit shift register, and outputs the output signal 1 of the IC under test 10.
03 consecutive N bit states at high speed time interval T
This circuit takes in the detection strobe signal 504 N times (times) of rising edges. For example, as shown in FIG. 2b, signal 504 is a fast detection strobe signal indicating the rise time.

The output signal 103 of the IC under test 10 is as shown in A.
If the IC input signal 102 changes after a time Ta, the detection strobe signal 504 captures the state after the change in the IC output signal 103 of A with the strobe at point a, and the high-speed buffer shift register 5
0 to the most input side register 5031. Second
The A signal of the signal 5031 in FIG. b is a waveform indicating a state change of the register 5031 corresponding to the output signal A of the IC 10 under test. In addition, the IC under test10
The output signal 103 of is the IC input signal 10 like B.
2, the detection strobe signal 504 captures the state of the B IC output signal 103 after the change with the strobe at point b and sends it to the most input side register 5031 of the high-speed buffer shift register 50. take in. Signal 50 in Figure 2b
The B signal 31 is a waveform indicating a change in the state of the register 5031 corresponding to the output signal A of the IC 10 under test. Furthermore, the output signal 1 of the IC under test 10
03 rises after T _C1 from a change in the IC input signal 102, and after a short time T _C2 rises from a change in the IC input signal 102.
If it is a tipping signal that falls later,
The detection strobe signal 504 is generated by capturing the rising change of the IC output signal 103 at the C1 point with a strobe at _{the C1} point, and catching the falling change at the C2 _point strobe at the C2 point. Incorporate into. The C signal 5031 in FIG. 2b has a waveform indicating the state change of the flip-flop 5031 at this time.

Since the high-speed buffer register 50 is an N-bit shift register, the contents of the most input flip-flop 5031, that is, the state of the signal 5031 in FIG.
After N bits of 04 are input, that is, they are shifted by N bits and output 50 of the high-speed buffer register 50.
Appears in 3. Therefore, the high speed buffer register 50
The waveform of the output signal 503 is the same as that of the signal 5031 in FIG. 2b, although it is delayed in time. Then, the selection circuit 60 selects the output signal 503 of the high-speed buffer register 50 and outputs it to the output signal line 60.
The state is output to 1. pattern comparator 40
is the output signal 50 of the high-speed buffer register 50 whose waveform is the same as the signal 5031 in FIG. 2b.
3 and the test machine side, for example, compare it with a reference input logic signal 401 of a predefined expected pattern sent through an input signal line 401 from a test pattern storage memory controlled by a CPU, and output the resulting output signal 402. Send to test machine control system.

Note that when it is not necessary to use the high-speed buffer register 50 to capture the temporal change state of the IC output signal 103 at high speed, the selection circuit 60 uses the direct output signal 202 of the level comparator 20 as in the conventional case.
Select 2. Therefore, the input pattern of the IC under test 10 requires bits of a control signal to be input to the selection circuit 60 that discriminates between the conventional normal system operation pattern and the time extension function operation pattern of the high-speed buffer register 50 according to the present invention. ,
The operation of the high speed buffer register 50 is started by activating this control signal bit to, for example, logic 1.

As explained above, since the detection system of the present invention shown in FIG. 2a is attached to all output pins of the IC under test, it is possible to simultaneously detect and judge the switching characteristics of the output signals of all output pins. It is also effective for systems where the switching delay between pins varies, such as random logic where the delay from input to output is undefined. For example, in an arithmetic circuit, depending on whether it is addition or subtraction,
Even if the delay of the output signal differs due to different logical paths within the IC, sampling is performed using multiple strobe signals during one system clock cycle, so the position of change in signal level can be detected accurately. Also, the output signal of the IC under test is 1
If you temporarily transition to another level and become a hazard,
Even if the output signal becomes a chopper signal, sampling with a high-speed strobe allows the phenomenon waveform to be taken into the high-speed buffer register as it is, so that the presence or absence of the phenomenon or the duration of the phenomenon can be detected.

[Brief explanation of drawings]

Fig. 1a is a block diagram of a conventional logic circuit tester, Fig. 1b is a timing chart of the tester of Fig. 1a, and Fig. 2a is an embodiment of the logic circuit tester according to the present invention. The block diagram, FIG. 2b, is a timing diagram for the embodiment described above. 10... IC to be measured, 101... Input drive circuit,
20... Level comparator, 201... Voltage level input signal line, 40... Pattern comparator, 401... Reference input signal line, 50... Buffer shift register, 502
...Batsuhua, 60...Selection circuit.

Claims (1)

[Scope of Claims] 1. A tester that tests an output signal of a logic circuit under test that receives an input signal transmitted from a tester, executes a logical operation, and outputs a result, comprising: a comparator connected to a signal line and a reference voltage level input signal line to compare a voltage level of an output signal of the logic circuit under test with a predetermined voltage level of the reference input signal; A high-speed buffer shift register that stores the digital signal from the comparator every time a strobe signal faster than the operating cycle of the test machine is input to detect the temporal change state of the signal, and an output of the high-speed buffer shift register. 1. A logic circuit tester comprising: a pattern comparator for comparing whether or not the signal matches an expected pattern of a predefined reference input logic signal in a slow operation cycle of the tester. 2. Compare the voltage level of the output signal of the logic circuit under test connected to the output signal line and voltage level reference input signal line of the logic circuit under test with the voltage level of the reference input signal specified in advance, and compare the output with the voltage level of the reference input signal. 2. The logic circuit tester according to claim 1, further comprising a level comparator for inputting to a high-speed buffer shift register.