JPH0261060B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention makes it possible to digitally process signals in real time, especially for signals that require a wide frequency band, such as video signals.

As shown in Figure 1, the block diagram of high-speed image processing using a video signal is to convert the synchronously separated video signal A5 into n-bit parallel digital data (high-speed comparator method) using the A-D converter A1, and convert it into 1-bit parallel digital data. Image processing is performed by one or more digital correlator group A2 per image, and it is again converted into an analog signal A6 using a DA converter A3, and a synchronization signal is added thereto and output to a monitor. The code generator A4 has two codes for convolution with digital correlators.
Supply a value series. Clock A7 drives the AD converter and digital correlator group from 0 to 20 MHz.

In FIG. 2, when one digital correlator is connected for each bit, the 7-bit output of the digital correlator is given a certain weight. 2 ⁰ for the output bit of the digital correlator connected to the least significant digit (LSD)
times, for the output of the digital correlator of the next bit
2 ^1x , and the digital correlator B2 of the most significant digit (MSD) B1 is a full adder group B3 to multiply by 2 ^n-1.
The output B4 of the full adder group becomes 2×n bits.

Inside the digital correlator, as shown in Figure 3, there is a data register C1 and a clock A that drives it.Every 64 bits of the data register are input to one side of a 2-input exclusive NOR C2, and the other is input to the reference latch C4 which stores the binary series of 0 or 1 in the reference register C5. The output of the exclusive NOR enters an AND circuit C3, which determines whether to perform multiplication depending on the state of the mask register C6. Also, the same signal is used for clocks B and M for driving the reference register and mask register. Digital summer C7, which uses the same clock as clock A that drives the data register, integrates the result of the exclusive NOR and outputs a 7-bit parallel digital signal C8.

FIG. 4 is a diagram showing in detail the method of connecting the digital correlator and the full adder group described in FIG. 2. The output of the digital correlator following the least significant digit is 2
Wire directly to the input full adder (with carry) D2, and the output of the digital correlator of the next digit will be connected upward by 1.
Bit shift and connect to 2-input full adder (with carry). This output and the output of the digital correlator D1, which is weighted 4 times, are wired to a 2-input full adder (with carry) by shifting the output of the digital correlator upwards by 2 bits, and connecting it to the output of the next 2-input full adder and the lower order. The two bits are supplied to a DA converter through latch D3 and converted into an analog signal.

FIG. 5 shows an example of convolution using a digital correlator. In general, V1(t) and
The correlation (cross-correlation) of V2(t) is calculated from the mathematical formula R12(r)=1/T ₀ ∫ ^T0/2 _T0/2 V1(t)V2(t+r)d
Represented by t. However, T ₀ : Period of the function Also, the convolution of V1(t) and V2(t) is shown as C(r)=∫ ^∞ _-∞ V1(t)V2(t-r)dt. It can also be expressed as follows.

C(r)=∫ ^∞ _-∞ V(t)h(r-t)dt However, h(t): indicates the impulse response of the transmitting system.

To calculate the correlation and convolution digitally, the correlation is expressed as R(n)= _∞ 〓 ^K=-∞ V1(K)V2(n+k). Also, convolution becomes y(n)= _∞ 〓 ^K=-∞ V(K)h(n-K), and correlation and convolution are the same except for the sign of K. In fact, Figure 5
is an example of convolution using a digital correlator. If the following data is input to the reference register E1, where the filter coefficients of the FIR digital filter are input, and the mask register E2, which specifies the filter order, as shown in the figure below. It is the same as the FIR digital filter expression E3. This frequency response A(ω) is H(ω)=A(ω)e ^-j 〓 ^t0 H(ω)=e ^-j 〓 ^(t0-2 〓 ⁾ +e ^-j 〓 ^(t0- 〓 ⁾ +e ^-j 〓 ^t0 +e ^-j 〓 ^(t0+ 〓 ⁾ −e ^-j 〓 ^(t0+2 〓 ⁾ = (4SIN ² ωτ−4SIN ² ωτ／2+1)e ^-j 〓 ^t0 ∴A(ω)＝4SIN ² ωτ−4SIN ² ωτ /2+1. This response represents a low pass filter with enhanced high frequencies. τ is the delay time. Furthermore, when all 1s are input to the reference register E4 and mask register E5, the FR digital filter expression E6 shown in the figure below is obtained. This frequency response A(ω) becomes H(ω)=(4COS ² ωτ +4COS ₂ ωτ/2+1)e ^-j 〓 ^t0 ∴A(ω)=4COS ² ωτ+4COS ² ωτ/2+5. This shows the characteristics of a smooth low-pass filter with reduced high frequencies.

FIG. 6 shows the input relationship of rectangular waves, and FIG. 7 shows waveforms that are subjected to real-time convolution. This results in an output waveform G1 of a low-pass filter with good response in the high frequency region. If the number of bits in the mask register is allowed to range from 3 to 8, all the bits in the reference register representing the system transfer characteristics will be 1. This impulse response becomes an output waveform G2 in which the high frequency region is lowered. If the conventional convolution operation for 1 bit is performed in the same way by all bits of digital correlators, n-bit signal processing (digital hard convolver) will result.

FIG. 8 shows a high-resolution and high-precision signal processing method. Analog signal H1 is input to two AD converters. A-D converter 1H2 uses clock 1H4
The A/D converter 2H3 converts the signal into digital data using the clock 2H5, which is delayed by half a cycle from the clock 1, and performs signal processing using a group of digital correlators. By connecting the digital correlator groups 1 and 2 with the full adder group H6, the resolution and accuracy are doubled.

[Brief explanation of the drawing]

Fig. 1 is a configuration explanatory diagram showing a high-speed image processing device using a video signal, Fig. 2 is a diagram showing a digital correlator group using one digital correlator for each bit, and Fig. 3 is a diagram showing a digital correlator group. Figure 4 shows how the digital correlators are connected to the full adder in order to give a certain weight to their output. Figure 5 shows an example of convolution using the digital correlators. Figure 6 is a diagram showing the rectangular wave used as an input to perform convolution, Figure 7 is a diagram of the output waveform showing each impulse response, and Figure 8 is a diagram showing high resolution and high precision. The figure which shows the signal processing device of.

Claims (1)

[Claims] 1 The N-bit digital signal obtained by A/D converting the analog signal is input into N data shift registers in parallel, and the FIR set in the reference latch is input based on the data set in the mask register. The resolution (resolving power) and A signal processing device characterized by improved accuracy.