JPH0261143B2 - - Google Patents
Info
- Publication number
- JPH0261143B2 JPH0261143B2 JP56027702A JP2770281A JPH0261143B2 JP H0261143 B2 JPH0261143 B2 JP H0261143B2 JP 56027702 A JP56027702 A JP 56027702A JP 2770281 A JP2770281 A JP 2770281A JP H0261143 B2 JPH0261143 B2 JP H0261143B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- junction
- plating
- bump
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
Landscapes
- Electrodes Of Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に関し、特に
例えば低いツエナー電圧を有する多数のツエナー
ダイオードを形成した半導体ウエーハの各ツエナ
ーダイオードにバンプ電極を形成する方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming bump electrodes on each Zener diode of a semiconductor wafer on which a large number of Zener diodes having a low Zener voltage are formed.
ツエナーダイオードは、一般に第1図に示す素
子構造を有する。図において、1はN型領域で、
このN型領域1内にP型領域2が選択的に形成さ
れている。3はPN接合。4は酸化膜等の絶縁
膜。5はアノード電極で、金蒸着膜6とその上の
銀のバンプ7で形成されている。8はカソード電
極で、金蒸着膜9と、その上の銀のメツキ膜10
で形成されている。 A Zener diode generally has an element structure shown in FIG. In the figure, 1 is an N-type region,
A P type region 2 is selectively formed within this N type region 1. 3 is PN junction. 4 is an insulating film such as an oxide film. Reference numeral 5 denotes an anode electrode, which is formed of a gold vapor-deposited film 6 and silver bumps 7 thereon. 8 is a cathode electrode, which has a gold vapor deposited film 9 and a silver plating film 10 thereon.
It is formed of.
この種のツエナーダイオードは次のようにして
製造されている。まず、N型の半導体ウエーハ
(以下単にウエーハという)1を用意し、両主面
に熱酸化膜等の絶縁膜4を形成し、一主面の絶縁
膜4のみに多数の窓孔を穿設して、この窓孔から
P型不純物を選択拡散してP型領域2を形成す
る。次にP型領域2上の絶縁膜4に再び窓孔を穿
設し、この窓孔から露出したP型領域2上および
裏面のN型領域1上に金蒸着膜6,9を形成す
る。続いて裏面の金蒸着膜9上に銀メツキ膜10
を形成してウエーハ100を得る。こののち、第
2図に示すように、銀電極板11とウエーハ10
0とを所定間隔でメツキ液中に浸漬して対向配置
し、銀電極板11とウエーハ100間にPN接合
3に順方向となる電圧を印加して、すなわち直流
メツキ電源12の正極を銀電極板11に接続する
とともに、負極をウエーハ100のカソード電極
8に接続して、表面の金蒸着膜6上に銀のバンプ
7をメツキ形成してアノード電極5を形成する。
こののち、各ツエナーダイオード素子間を切断分
離すれば、第1図のようなツエナーダイオードが
得られる。 This type of Zener diode is manufactured as follows. First, an N-type semiconductor wafer (hereinafter simply referred to as wafer) 1 is prepared, an insulating film 4 such as a thermal oxide film is formed on both main surfaces, and a large number of windows are drilled in the insulating film 4 on only one main surface. Then, P-type impurities are selectively diffused through this window hole to form P-type region 2. Next, a window hole is made again in the insulating film 4 on the P-type region 2, and gold vapor deposited films 6, 9 are formed on the P-type region 2 exposed through the window hole and on the N-type region 1 on the back surface. Next, a silver plating film 10 is applied on the gold vapor deposited film 9 on the back side.
is formed to obtain the wafer 100. After this, as shown in FIG. 2, the silver electrode plate 11 and the wafer 10 are
0 are immersed in a plating solution at a predetermined interval and placed facing each other, and a forward voltage is applied to the PN junction 3 between the silver electrode plate 11 and the wafer 100, that is, the positive electrode of the DC plating power source 12 is connected to the silver electrode. The negative electrode is connected to the plate 11 and the cathode electrode 8 of the wafer 100, and silver bumps 7 are plated on the gold vapor deposited film 6 on the surface to form the anode electrode 5.
Thereafter, by cutting and separating each Zener diode element, a Zener diode as shown in FIG. 1 is obtained.
ところで、上記第2図のバンプ7の形成工程に
おいて、もしすべてのPN接合3が正常であれ
ば、各バンプ7は略同等の高さに形成できるが、
一部のPN接合3aが短絡を起していると、この
不良素子部分にメツキ電流が集中して流れ、バン
プ7aが異常成長する。このため、周辺の正常な
素子のメツキ電流が減少して、正規のメツキ時間
ではバンプ7の高さが不足するようになり、所定
の高さのバンプ7を形成するためには、メツキ時
間が長くなる。また、異常なバンプ7aが形成さ
れると、特性チエツク時に探針がこの異常バンプ
7aに引掛つて特性チエツク装置を傷めたり、さ
らには各素子に切断分離することが困難になると
いつた問題点があつた。 By the way, in the step of forming the bumps 7 shown in FIG. 2 above, if all the PN junctions 3 are normal, each bump 7 can be formed to approximately the same height.
If some of the PN junctions 3a are short-circuited, the plating current will concentrate and flow in this defective element portion, causing abnormal growth of the bumps 7a. For this reason, the plating current of the surrounding normal elements decreases, and the height of the bump 7 becomes insufficient in the normal plating time. become longer. Furthermore, if an abnormal bump 7a is formed, there are problems such as the probe getting caught on the abnormal bump 7a during a characteristic check, damaging the characteristic checking device, and furthermore, making it difficult to cut and separate each element. It was hot.
上記欠点を解決するために各種の方法が提案さ
れた。まず、第1の方法は、金蒸着膜6,9を形
成した段階で特性チエツクを行なつて、不良素子
の金蒸着膜6a上に絶縁膜を被着形成するもので
ある。この方法は特性チエツク工程および絶縁膜
の形成工程が必要で煩雑である。第2の方法は、
ツエナーダイオードの電圧対電流特性を利用する
ものである。すなわち、ツエナーダイオードは、
第3図に示すように、順方向の電圧に対しては低
いスレツシホールド電圧VSで導通するが、逆方
向の電圧に対してはツエナー電圧VZ1で導通し、
VS<VZ1である。そこで、バンプ7の形成に際し
て、第3図および第4図Aに示すように、前記ス
レツシホールド電圧VSよりも大きい順方向電圧
V1を印加するのであるが、いきなりこのように
すると万一不良PN接合3aがあつた場合、前述
のとおり異常バンプ7aが形成される。このた
め、第2の方法は、第4図Bに示すように、まず
ツエナー電圧VZ1よりも低い電圧V2を印加して、
不良PN接合3a部分のみに逆電流を流して、不
良素子の金蒸着膜6aのみを電解作用によつて選
択的に溶解除去し、次いで、順方向電圧V1を印
加して良品PN接合3を有する良品素子上のみに
バンプ7を形成する方法である。第3の方法は、
第4図Cに示すように、時間T1だけ順方向電圧
V1でメツキし、時間T2だけ逆電圧V2を印加し
て不良素子上のバンプ7aを溶解除去することを
繰返す方法である。これら第2、第3の方法は非
常に巧みな方法で、ツエナー電圧VZが比較的大
きい場合は非常に優れた方法であるが、ツエナー
電圧VZが数ボルト程度になると、良品素子上の
金蒸着膜6やバンプ7も溶解されるという問題点
がある。すなわち、低いツエナー電圧VZ2(2〜
6V程度)のツエナーダイオードは、N型領域1
およびP型領域2の不純物濃度を高くして製造す
るので、ウエーハ100の比抵抗が小さくなるこ
と、およびそれによつて絶縁膜4の直下部分に反
転層(チヤンネル)が形成されやすいことによつ
て、第5図に示すような電圧対電流特性となる。
このため、ツエナー電圧VZ2よりも小さい逆電圧
V3を印加しても、リーク電流I0が流れるので、第
2の方法では、不良PN接合3a上の金蒸着膜6
aのみならず、正常なPN接合3上の金蒸着膜6
も溶解除去されてしまいやすいし、第3の方法で
は異常バンプ7aのみならず正常バンプ7も一部
溶解されるので、所定の高さのバンプ7を形成す
るためには、メツキ時間が著しく長くなるという
欠点があり、採用できないという問題点があつ
た。 Various methods have been proposed to solve the above drawbacks. First, the first method is to perform a characteristic check after forming the gold vapor deposited films 6 and 9, and then deposit an insulating film on the gold vapor deposited film 6a of the defective element. This method is complicated because it requires a characteristic check step and an insulating film formation step. The second method is
This utilizes the voltage versus current characteristics of a Zener diode. In other words, the Zener diode is
As shown in Fig. 3, it conducts at a low threshold voltage V S with respect to a forward voltage, but conducts at a Zener voltage V Z1 with respect to a reverse voltage.
V S <V Z1 . Therefore, when forming the bump 7, as shown in FIGS. 3 and 4A, a forward voltage higher than the threshold voltage V S is applied.
V 1 is applied, but if this is done suddenly, if a defective PN junction 3a occurs, an abnormal bump 7a will be formed as described above. Therefore, the second method, as shown in FIG. 4B, is to first apply a voltage V 2 lower than the Zener voltage V Z1 ,
A reverse current is applied only to the defective PN junction 3a to selectively dissolve and remove only the gold vapor deposited film 6a of the defective element by electrolytic action, and then a forward voltage V1 is applied to remove the good PN junction 3. In this method, bumps 7 are formed only on non-defective devices that have the same characteristics. The third method is
As shown in FIG. 4C, the forward voltage is increased for time T1.
This is a method of repeating plating with V 1 and applying a reverse voltage V 2 for a time T 2 to dissolve and remove the bumps 7a on the defective elements. These second and third methods are very clever methods and are very good when the Zener voltage V Z is relatively large, but when the Zener voltage V Z becomes about several volts, the There is a problem that the gold vapor deposited film 6 and the bumps 7 are also dissolved. That is, the low Zener voltage V Z2 (2~
6V) Zener diode is in the N-type region 1
Since the P-type region 2 is manufactured with a high impurity concentration, the specific resistance of the wafer 100 is reduced, and an inversion layer (channel) is easily formed directly under the insulating film 4. , the voltage vs. current characteristics are as shown in FIG.
For this reason, the reverse voltage smaller than the Zener voltage V Z2
Even if V 3 is applied, leakage current I 0 flows, so in the second method, the gold vapor deposited film 6 on the defective PN junction 3a is
In addition to a, the gold vapor deposited film 6 on the normal PN junction 3
Also, in the third method, not only the abnormal bump 7a but also a part of the normal bump 7 is dissolved, so in order to form the bump 7 of a predetermined height, the plating time is extremely long. There was a problem that it could not be adopted.
それゆえ、この発明の主たる目的は、ツエナー
電圧の低い多数のツエナーダイオード素子を形成
したウエーハの各素子上に良好なバンプをメツキ
形成する方法を提供することである。 Therefore, the main object of the present invention is to provide a method for plating good bumps on each element of a wafer on which a large number of Zener diode elements with low Zener voltage are formed.
この発明を要約すると、最初所定の順方向電圧
でバンプを形成したのち、ツエナー電圧等の逆方
向破壊電圧よりも低い逆電圧を印加して異常バン
プを溶解するようにしたことを特徴とする。 In summary, the present invention is characterized in that after a bump is first formed with a predetermined forward voltage, a reverse voltage lower than the reverse breakdown voltage, such as a Zener voltage, is applied to dissolve the abnormal bump.
この発明の上述の目的およびその他の目的と特
徴は、図面を参照して行なう以下の詳細な説明か
ら一層明らかとなろう。 The above objects and other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.
第6図はこの発明によるメツキ時間と印加電圧
の関係を示す図であり、第7図はメツキ時の状態
を示す図である。図において、第2図および第4
図と同一部分は同一参照符号を示す。第7図にお
いて、13は切換スイツチで、銀電極板11に接
続された共通端子14a、ウエーハ100のカソ
ード電極8に接続された共通端子14bと、電圧
V1の直流メツキ電源12の正極に接続された切
換端子15a、負極に接続された切換端子15b
と、電圧V3の直流電解電源16の正極に接続さ
れた切換端子17a、負極に接続された切換端子
17bとを有する。 FIG. 6 is a diagram showing the relationship between plating time and applied voltage according to the present invention, and FIG. 7 is a diagram showing the state during plating. In the figure, Figures 2 and 4
Parts that are the same as those in the figures have the same reference numerals. In FIG. 7, 13 is a changeover switch, which has a common terminal 14a connected to the silver electrode plate 11, a common terminal 14b connected to the cathode electrode 8 of the wafer 100, and a voltage
Switching terminal 15a connected to the positive pole of the V 1 DC plating power supply 12, switching terminal 15b connected to the negative pole
, a switching terminal 17a connected to the positive electrode of the DC electrolytic power supply 16 of voltage V3 , and a switching terminal 17b connected to the negative electrode.
まず、第7図に示すように、切換スイツチ13
を切換端子15a,15b側に投入すると、銀電
極板11が直流メツキ電源12の正極に、ウエー
ハ100のカソード電極8が負極に接続されるの
で、ウエーハ100のPN接合3にはスレツシホ
ールド電圧VSよりも大きい順方向電圧V1が印加
されて表面の金蒸着膜6上にバンプ7が形成され
る。こゝで、もしPN接合3に一部不良PN接合
3aが含まれていると、この不良PN接合3aを
含む素子に電流が集中して流れて、異常バンプ7
aが形成されることは先に述べたとおりである。 First, as shown in FIG.
When applied to the switching terminals 15a and 15b, the silver electrode plate 11 is connected to the positive electrode of the DC plating power supply 12, and the cathode electrode 8 of the wafer 100 is connected to the negative electrode, so that a threshold voltage is applied to the PN junction 3 of the wafer 100. A forward voltage V 1 larger than V S is applied, and bumps 7 are formed on the gold vapor deposited film 6 on the surface. Here, if the PN junction 3 includes a part of the defective PN junction 3a, the current will concentrate on the element including the defective PN junction 3a, and the abnormal bump 7
As mentioned above, a is formed.
次に、切換スイツチ13を切換端子17a,1
7b側に投入する。すると、ウエーハ100のカ
ソード電極8が直流電解電源16の正極に、銀電
極板11が負極に接続されるので、ウエーハ10
0のPN接合3にはツエナー電圧VZ2よりも低い
逆電圧V3が印加される。しかるに、ツエナー電
圧VZ2が低いと、第5図に示すように、正常な
PN接合3にもリーク電流I0が流れるが、不良PN
接合3aにはより大きい電流が流れる。この結
果、正常なPN接合3の素子のバンプ7も電解作
用で若干溶解されるが、不良PN接合3aの素子
の異常バンプ7aの溶解はより顕著である。この
ようにして、異常バンプ7aが特性チエツク装置
を傷めないような高さに達した時点で切換スイツ
チ13を中性状態に戻して電解作用を中止する。
こののち、各素子間を切断分離すれば、第1図の
ようなツエナーダイオードが得られる。 Next, the changeover switch 13 is connected to the changeover terminals 17a, 1
Insert it into the 7b side. Then, the cathode electrode 8 of the wafer 100 is connected to the positive electrode of the DC electrolytic power source 16, and the silver electrode plate 11 is connected to the negative electrode, so that the wafer 10
A reverse voltage V 3 lower than the Zener voltage V Z2 is applied to the PN junction 3 of 0. However, if the Zener voltage V Z2 is low, as shown in Figure 5, the normal
Leakage current I 0 also flows through PN junction 3, but the defective PN
A larger current flows through junction 3a. As a result, the bumps 7 of the element with the normal PN junction 3 are also slightly dissolved by the electrolytic action, but the abnormal bumps 7a of the element with the defective PN junction 3a are more significantly dissolved. In this way, when the abnormal bump 7a reaches a height that will not damage the characteristic check device, the changeover switch 13 is returned to the neutral state and the electrolytic action is stopped.
Thereafter, by cutting and separating each element, a Zener diode as shown in FIG. 1 is obtained.
なお、上記実施例はN型領域1内にP型領域2
を選択拡散で形成する場合について説明したが、
N型領域1上にP型不純物をドープしたP型多結
晶領域を形成してもよい。P型領域内または上に
N型領域を選択拡散するかN型多結晶領域を形成
してもよい。また、温度補償型ツエナーダイオー
ドのように、両主面にバンプを有するものにも適
用できる。 Note that in the above embodiment, a P-type region 2 is provided within an N-type region 1.
We explained the case where is formed by selective diffusion, but
A P-type polycrystalline region doped with a P-type impurity may be formed on the N-type region 1. An N-type region may be selectively diffused in or on the P-type region, or an N-type polycrystalline region may be formed. Furthermore, the present invention can also be applied to devices having bumps on both principal surfaces, such as a temperature-compensated Zener diode.
さらに、バンプ7を形成する場合、銀電極板1
1とウエーハ100をメツキ液中に浸漬して対向
配置する場合のみならず、噴流式メツキを採用し
てもよい。 Furthermore, when forming the bumps 7, the silver electrode plate 1
In addition to the case where the wafer 1 and the wafer 100 are immersed in a plating liquid and placed facing each other, jet plating may be adopted.
この発明は以上のように、PN接合を有する多
数の半導体素子を形成した半導体ウエーハの各半
導体素子上にバンプ電極をメツキ形成する方法に
おいて、最初に、前記PN接合に順方向の電圧を
印加して各半導体素子上にバンプ電極を形成した
のち、前記PN接合に逆方向破壊電圧よりも小さ
い逆電圧を印加して異常バンプ電極を溶解するも
のであるから、低いツエナー電圧を有するツエナ
ーダイオードにおいても、短時間でかつ良好なバ
ンプ電極が形成できるという効果を奏する。 As described above, the present invention provides a method for plating bump electrodes on each semiconductor element of a semiconductor wafer on which a large number of semiconductor elements having PN junctions are formed, in which a forward voltage is first applied to the PN junction. After forming bump electrodes on each semiconductor element, a reverse voltage smaller than the reverse breakdown voltage is applied to the PN junction to dissolve the abnormal bump electrodes. Therefore, even in a Zener diode with a low Zener voltage, This has the effect that a good bump electrode can be formed in a short time.
第1図はこの発明の背景となるツエナーダイオ
ードの一例の断面図、第2図は第1図のダイオー
ドの従来の製造方法を説明するための概略構成断
面図、第3図はツエナー電圧が比較的大きい場合
の電圧対電流特性図、第4図Aないし第4図Cは
従来の異なるメツキ方法の電圧印加特性図、第5
図はツエナー電圧が比較的小さい場合の電圧対電
流特性図、第6図はこの発明による製造方法を説
明する電圧印加特性図、第7図はこの発明の一実
施例方法を説明するための概略構成断面図であ
る。
3……(良品)PN接合、3a……(不良)
PN接合、5……アノード電極、7……バンプ、
8……カソード電極、11……銀電極板、12…
…直流メツキ電源、13……切換スイツチ、16
……直流電解電源、100……半導体ウエーハ、
V1……順方向電圧、VZ2……逆方向破壊電圧、V3
……逆方向電圧。
Fig. 1 is a cross-sectional view of an example of a Zener diode which is the background of this invention, Fig. 2 is a schematic cross-sectional view for explaining the conventional manufacturing method of the diode shown in Fig. 1, and Fig. 3 is a comparison of Zener voltages. Figures 4A to 4C are voltage vs. current characteristic diagrams when the target is large;
The figure is a voltage vs. current characteristic diagram when the Zener voltage is relatively small, FIG. 6 is a voltage application characteristic diagram illustrating the manufacturing method according to the present invention, and FIG. 7 is a schematic diagram illustrating one embodiment of the method of the present invention. It is a configuration sectional view. 3... (good product) PN junction, 3a... (defective)
PN junction, 5... anode electrode, 7... bump,
8... Cathode electrode, 11... Silver electrode plate, 12...
...DC plating power supply, 13...Selector switch, 16
...DC electrolytic power supply, 100...semiconductor wafer,
V 1 ...Forward voltage, V Z2 ...Reverse breakdown voltage, V 3
...Reverse voltage.
Claims (1)
た半導体ウエーハの各半導体素子にバンプ電極を
メツキ形成する方法において、 最初前記PN接合に所定の順方向の電圧を印加
して各半導体素子にバンプ電極を形成したのち、
前記PN接合に逆方向電圧を印加して異常バンプ
電極を溶解することを特徴とする半導体装置の製
造方法。[Claims] 1. In a method of plating bump electrodes on each semiconductor element of a semiconductor wafer on which a large number of semiconductor elements having PN junctions are formed, a predetermined forward voltage is first applied to the PN junctions, and each After forming bump electrodes on the semiconductor element,
A method of manufacturing a semiconductor device, comprising applying a reverse voltage to the PN junction to dissolve the abnormal bump electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56027702A JPS57141940A (en) | 1981-02-26 | 1981-02-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56027702A JPS57141940A (en) | 1981-02-26 | 1981-02-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57141940A JPS57141940A (en) | 1982-09-02 |
| JPH0261143B2 true JPH0261143B2 (en) | 1990-12-19 |
Family
ID=12228309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56027702A Granted JPS57141940A (en) | 1981-02-26 | 1981-02-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57141940A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100705371B1 (en) | 1999-07-26 | 2007-04-11 | 동경 엘렉트론 주식회사 | Plating treatment method, plating treatment device and plating treatment system |
-
1981
- 1981-02-26 JP JP56027702A patent/JPS57141940A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57141940A (en) | 1982-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2590284B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0473306B2 (en) | ||
| JPH0216591B2 (en) | ||
| US4350990A (en) | Electrode for lead-salt diodes | |
| US5254869A (en) | Aluminum alloy/silicon chromium sandwich schottky diode | |
| US2992471A (en) | Formation of p-n junctions in p-type semiconductors | |
| EP0297325A2 (en) | Gate turn-off thyristor and manufacturing method thereof | |
| US6633071B1 (en) | Contact on a P-type region | |
| US5831291A (en) | Insulated gate bipolar transistors | |
| US6838744B2 (en) | Semiconductor device and manufacturing method thereof | |
| US4223327A (en) | Nickel-palladium Schottky junction in a cavity | |
| JPH0261143B2 (en) | ||
| JPH0291974A (en) | Semiconductor device | |
| US4551744A (en) | High switching speed semiconductor device containing graded killer impurity | |
| JP2934606B2 (en) | Semiconductor device | |
| EP0186567B1 (en) | Diac with coplanar electrodes | |
| US2980594A (en) | Methods of making semi-conductor devices | |
| JPH0291975A (en) | Semiconductor device | |
| US3284680A (en) | Semiconductor switch | |
| JPH02114675A (en) | Semiconductor light emitting device and its manufacturing method | |
| JPH02260529A (en) | Manufacture of plating electrode | |
| JP2581890B2 (en) | Semiconductor device | |
| KR100482845B1 (en) | Silicon carbide back-to-back Schottky barrier diode structure | |
| JPH02246160A (en) | Semiconductor device | |
| JPH0832049A (en) | Semiconductor device |