JPH0261192B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal recording and reproducing device, and in particular to a sampling method obtained by sampling an input composite video signal at a frequency slightly higher than the upper limit frequency of its required frequency band. Video signal recording and reproduction in which a signal is recorded on a recording medium, and during reproduction, a reproduced video signal is obtained by chronologically synthesizing two types of reproduced sampled signals having a time difference of one field from each other at each sampling point. Regarding equipment.

Conventional technology In general, helical scanning VTRs use
A rotating head records a video signal on a running magnetic tape, and the already recorded video signal is reproduced by the rotating head. The above video signal has a wide band with an upper limit frequency of about 4.2 MHz, for example. In order to frequency-modulate this wide band video signal, record it on a magnetic tape, and play it back, the relative speed between the head and tape must be set at a predetermined level. It is well known that it is necessary to use a high-performance head with high sensitivity in a high frequency range as well as to increase the speed above the specified value.

However, in the case of home-use VCRs, the relative speed between the tape and the head has to be much lower than the above prescribed value due to demands for lower prices, smaller devices, and lighter weights. The recording and reproducing band becomes narrower than the original band of the video signal, which poses a problem in reproducing higher quality video signals.

Therefore, the present applicant previously proposed in Japanese Patent Application No. 107379/1983 to sample and record the input video signal at a frequency slightly higher than the upper limit frequency of the required frequency band of the input video signal, and when playing back, the above sampling frequency is used. approximately equal to
We also proposed a video signal recording and reproducing device that alternately samples signals with a phase difference of 180° from each other. According to this proposed device, even if the recording/reproducing device has a narrow recording/reproducing band, it is possible to obtain a reproduced video signal with a wider band.

Problems to be Solved by the Invention However, in the device proposed above, the reproduction system delays the reproduced sampled signal by one field using a field memory, and the reproduced sampled signal delayed by one field is Since the configuration was such that the reproduced sampled signal that is currently being reproduced before the field is synthesized (resampled) alternately in time series for each sampling point, the image The edges in the horizontal direction sometimes became jagged. This is especially true when the field memory is specified with an absolute address for the line, that is, the lower address of the memory address specifies the address based on the number of samples per line, and the upper address corresponds one-to-one with the line. If you let
Whisker-like jagged edges appear on the horizontal edges of rectangular images that have a different brightness than the background, or images that have no vertical correlation, such as diagonal lines. For example, Figure 14A
As shown in the figure, the third and fourth lines of the odd field
Each pixel data of L ₃ and L ₄ is black, all the pixel data of the other lines of the odd field are white, and as shown in Figure B, each pixel data of the 266th line L266 of the even field is black. , all the pixel data of the other lines of the even field are white, and therefore, as shown in FIG. When writing and reading are performed in one-to-one correspondence with the lines, when reproducing the black pixel data of the third line _L3 in an odd field, the 266th line one field before
It is added and synthesized alternately with the black pixel data of the line L266, and when reproducing the black pixel data of the fourth line _L4 of an odd field, the black pixel data of the previous field is
267 Since the white pixel data of line L267 is added alternately, when the fourth line _L3 is reproduced, the first
As shown in FIG. 5A, white and black pixel data appear alternately. Similarly, when reproducing the 267th line L267 of an even field, the black pixel data of the 4th line _L4 , which is one field before, is added and synthesized alternately for each sample point, so as shown in FIG. 15B, white and Black pixel data appears alternately. As a result, the reproduced image appears to have jagged edges in the horizontal direction on the 3rd, 4th, 266th, and 267th lines, as shown in FIG. 15C.

In addition, the pixel data of six lines from the top of the first, second, and third fields are shown in FIG. 16A,
In the case of video signals of diagonally shaded images as shown in B and C, pixel data sequences as shown in FIG. , when each pixel data of the third field is synthesized alternately in time series, the first
A pixel data string as shown in Figure 7B is obtained, and as a result, the reproduced image has the first eight pixels from the top of the screen.
As shown in Figure 8, the pattern appears as a large step-like pattern instead of a diagonal line.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a video signal recording and reproducing device that solves the above problems by changing the memory write address or read address by a fixed value once every two fields. do.

Means for Solving the Problems FIG. 1 is a block diagram showing the configuration of the apparatus of the present invention. In the figure, a composite video signal (particularly a luminance signal) input to an input terminal 1 is supplied to a first signal generating means 2 and a sampling means 3, respectively. 1st
The signal generating means 2 generates a signal having a sampling frequency f _S related to the horizontal scanning frequency f _H of the input composite video signal, and whose phase differs by 180° for each field of the input composite video signal. . The sampling means 3 samples the input composite video signal using the output signal of the first signal generating means 2.

The sampled signal extracted from the sampling means 3 is
It is recorded on a recording medium by the recording means 4 and reproduced by the reproducing means 5. Recording means 4 and reproduction means 5
is a conventionally known configuration. The signal reproduced by the reproduction means 5 (reproduction signal) is supplied to the addressing means 8 and the second signal generation means 11, respectively, and is also supplied to the AD converter 6, where it is analog-to-digital converted and converted into a pixel. After being converted into data, the data is supplied to a memory circuit 7 having a storage capacity for one field and to reproduction sampling signal generation means 9, which will be described later. Furthermore, the reproduction signal is transmitted to the addressing means 8.
Here, a write address and a read address are alternately generated and supplied to the memory circuit 7, and the relationship between the upper address of one of the read address and write address in the odd field and the line is determined from the even field. Compared to the relationship between the upper address and the line of one of the read addresses and write addresses, which are the same as above, these are generated relatively by one address.

The pixel data read out after being delayed by one field by the memory circuit 7 is supplied to the reproduced sampling signal generating means 9. The reproduced sampling signal generating means 9 simultaneously generates and outputs first and second reproduced sampling signals having a relative time difference of one field. Further, the second signal generating means 11 converts the reproduced signal into a signal having the same frequency as the output signal of the first signal generating means 2.
f _S and a signal whose phase differs by 180° for each field of the reproduced signal is generated. Resampling means 1
0 is supplied with the output signal of the second signal generating means 11 as a switching signal, and the first and second reproduced sampling signals from the reproduced sampling signal generating means 9 are alternately outputted to the output terminal 12 every half period. Selectively output to. As a result, the output terminal 12 is effectively 2f _S
A reproduced composite video signal resampled at the frequency is extracted.

Effect The sampling frequency of the reproduced composite video signal is essentially
2f _S , it is possible to obtain a wideband reproduced video signal.

In addition, according to the present invention, the addressing means 8 makes the upper address corresponding to the line of the write address or read address in the odd field different from that in the even field by one address, so that the vertical correlation Since the jaggedness of the horizontal edges of the neutral image is reduced to one line, which is half of that of the conventional image, the jaggedness becomes almost invisible visually.

For example, in an odd field, as shown in FIG. 2A, the two adjacent third and fourth lines L ₃ and L ₄ are all composed of black pixel data, and the remaining lines L ₁ ,
Each pixel data of L ₂ , L ₅ to L263 is an image in which all are white, and as shown in FIG.
Assuming that each pixel data of L267 to L525 are all white images, the reproduced image is the 14th pixel data.
The image will look like the one shown in Figure C. In this image, there is no vertical correlation between lines L265 and _L3 , and there is no vertical correlation between lines _L4 and L267.
For pixel data of such an image, the addressing means 8 assigns A 1 , A 2 , A 2 , A ₁ , A ₂ , …，A263
In the even field, the upper address of the write address is A 2 , A ₃ , A 3 , A ₃ ,
..., A263, A ₁ , the address of the line plus one address (for example, line L26
4 is the top line in an even field,
Adding ₁ to the original address A1 results in _A2 . ), and the read address is generated by associating the upper address with the line in one-to-one correspondence through all fields.

As a result, during the sampling signal reproduction period of line L266, line _L266 is
video signal and the line one field before this
The video signals of L _{3 and} 3 are selectively output to the output terminal 12 alternately, but since the pixel data of both lines are both black, as shown in FIG. It becomes an image. During the sampling signal reproduction period of the next line L267, the upper address of the read address of the memory circuit 7 is _A4 ,
From memory circuit 7, the address is one field before.
The black pixel data of line _L4 written in _A4 is read out. On the other hand, since line L267 is white pixel data, during the reproduction period of line L267, the white image of line L267 is alternately displayed every period 1/(2f _S ) as shown by L ₄ +L267 in FIG. 3A. and a black image of line _L4 appear.

Also, during the sampling signal reproduction period of each line L265 and L268, the upper address of the read address of the memory circuit is A ₂ and A ₅ , and the pixel data of lines L ₂ and L ₅ is read from the memory circuit 7. As a result, a white image appears as shown in FIG. 3A.

On the other hand, during the reproduction period of the sampled signal of line _L3 in the odd field, the upper address of the read address of the memory circuit 7 is set to _A3 , and the pixel data of line _L3 is black as shown in FIG. 2A. On the other hand, since the pixel data of line L265 (conventionally, this was L266) one field before read from address _A3 is white as shown in FIG _. is the third
As shown by L265+ _L3 in Figure B, the black image of line _L3 and the line L26 are alternately displayed every 1/2f _S.
5 white image appears. Furthermore, during the period of reproducing the sampling signal of line _L4 , the upper address of the read address of the memory circuit 7 is set to _A4 , and the black of line L266 written one field ago from the memory circuit 7 to the address _A4 . The pixel data of L266+ _L4 is read out in Figure 3B.
As shown, a horizontal black line appears on the playback screen. During the reproduction period of the next sampled signal of line _L5 , the upper address of the read address of the memory circuit 7 is set to _A5 , so the memory circuit 7 reads the line L267 that was written one field ago to the address _A5 . White pixel data is read out. Therefore, during this reproduction period, the images of lines L ₅ and L267 appear alternately every 1/2f _S , but
Since both images of lines L ₅ and L267 are white, a single horizontal white line appears on the playback screen as shown by L267+L ₅ in FIG. 3B.

Therefore, the final reproduced image consists of lines L ₂ to _{L 5} ,
As shown in Figure 4, near L265 to L268,
A black rectangle with a width of two lines has one line above and below the other, creating an image in which white and black are alternately repeated, that is, whisker-like jagged edges. However, compared to the conventional one shown in FIG. 15C, the width of this jagged line is only one line, which is half the width of the conventional one, and it is hardly noticeable visually.

In addition, as shown in Fig. 5 A, B, Fig. 2 A, B
For the video signal (especially the luminance signal) of the same image as the image shown in , the upper address of the write address corresponds one-to-one to the line in both odd and even fields, while the upper address of the read address is For odd fields, lines L ₁ , L ₂ ,...
L263 has a one-to-one correspondence with lines A ₁ , A ₂ , ..., A263, and in even fields, lines L264, L265, ..., L524, L52
5, A ₂ , A ₃ , . . . , A263, A ₁ and the relationship between the read address of the odd field and the line is increased by one address, the same result as in the case of FIG. 2 is obtained. That is, during the reproduction period of the sampling signal of the line L265 of the even field, the memory circuit 7
The upper address of the read address is A ₃ ,
Since the black pixel data of line _L3 is written to address _A3 , _L3 +L265 is shown in FIG. 6A.
As shown, the white image of line L265 and the line
The black images of _L3 appear alternately. Also,
During the reproducing period of each sampled signal on lines L266 and L267, the upper addresses of the readout address of the memory circuit 7 become A ₄ and A ₅ , and the pixel data on lines L ₄ and L ₅ are read out, as shown in FIG. 6A. An image like this will be played.

On the other hand, the upper addresses of the read addresses of the memory circuit 7 during the reproduction period of the sampling signals of the lines L ₂ , L ₃ , and L ₄ of the odd field are A ₂ , A ₃ , and A ₄ as shown in FIG. 5A. be. This address A ₂ , A ₃ ,
Since the pixel data of the 2nd, 3rd, and 4th lines L265, L266, and L267 from the top of the even field are written in _A4 , the lines _L2 , _L3 ,
The reproduced image during each sampling signal reproduction period of _L4 is as shown in FIG. 6B. Therefore, the final reproduced image will be the same as that shown in FIG.

Further, only the upper address of the write address may be reduced by one address during even field reproduction than in the case of odd field reproduction, and furthermore, only the upper address of the read address may be reduced by one address. In the former case, see Figure 6 A and B.
In the latter case, the same reproduced images as in FIGS. 3A and 3B are obtained.

In addition, six lines L ₁ to _{L 6} (L264 to L269) from the top of the first, second, and third fields, respectively.
In the case of a video signal of an image in which the pixel data shows diagonal lines as shown in FIGS. 7A, B, and C, only the upper address of the write address is increased by one address when playing an even field compared to when playing an odd field. Then, when the second field is reproduced, an image as shown in FIG. 8A is obtained, and when the third field is reproduced, an image as shown in FIG. 8B is obtained. Therefore, the reproduced image for one frame is shown in FIG. Thus, the jagged edges on the whiskers are less noticeable than those in the conventional image shown in FIG. below,
The present invention will be described in more detail along with examples.

Embodiment FIG. 10 shows a circuit diagram of an embodiment of the device of the present invention. In the figure, the same components as in FIG. 1 are designated by the same reference numerals. First, to explain the operation during recording, a composite video signal (for example, a luminance signal) input to input terminal 1 is supplied to synchronization signal separation circuit 15 through switch circuit 14 connected to terminal R, where horizontal After the synchronization signal and vertical synchronization signal are separated, the horizontal synchronization signal is supplied to a phase locked loop (PLL) 16 and a timing generator 17, respectively, and the vertical synchronization signal is supplied to the timing generator 17. PLL1
6 is phase-synchronized with the horizontal synchronizing signal, and generates and outputs a sampling pulse having a sampling frequency f _S that is a natural number multiple of the horizontal scanning frequency f _H and satisfies the following equation.

f _S ≒ f _L + f _U …(1) (However, in equation (1), f _L is a constant frequency of about 0.5MHz to 1 MHz, and f _U is the upper limit frequency of the required frequency band of the reproduced luminance signal) This sampling pulse is While the signal is supplied to the timing generator 17, it is also supplied to the terminal 18a of the switch circuit 18, and the phase is inverted by the inverter 19 (with a 180° phase difference) and then supplied to the terminal 18b of the switch circuit 18. In the switch circuit 18, a well-known head switching pulse, which is a symmetrical square wave with a two-field period, generated by a recording/reproducing device 23, which will be described later, is branched and applied as a switching pulse from an output terminal 25, and is switched every field. Connected.

As a result, the switch circuit 18 has a frequency f _S whose phase is varied by 180 degrees for each field.
The sampling pulses are selectively outputted and supplied to the terminal 20a of the switch circuit 20. switch circuit 2
0 terminal 20b is applied with DC voltage +Vc. On the other hand, during recording, the timing generator 17 takes a first logical value in phase synchronization with the horizontal blanking period and vertical blanking period of the input composite video signal, and takes a second logical value in other periods. A pulse is generated and outputted to the switch circuit 20 as a switching pulse. As a result, the switch circuit 20 switches the input DC voltage Vcc of the terminal 20b to the switch circuit 2 during both the horizontal and vertical blanking periods.
1 and continues to keep it on. On the other hand, during a period other than the blanking period (video period), the input sampling pulse at the terminal 20a is selectively output to the switch circuit 21.

As a result, the switch circuit 21 alternately turns on and off every half _cycle of the sampling pulse during the video period of the input composite video signal, and applies the input composite video signal to the hold capacitor 22 during the on period. Therefore, hold capacitor 2
2, the sampled signal obtained by sampling the video period signal at the sampling frequency _fS is taken out and connected to the recorded video signal input terminal of the recording/reproducing device 23 (existing VTR
is supplied to the input terminal (input terminal) 24 of the luminance signal recording system. Furthermore, since the switch circuit 21 is continuously on during the blanking period, at least the synchronization signal of the input composite video signal is supplied to the recording video signal input terminal 24 without being sampled.

Here, as is clear from equation (1) above, the sampling frequency f _S is a frequency f _L higher than the upper limit frequency f _U of the required frequency band of the reproduced composite video signal, but this frequency f _L is lower than upper limit frequency f _U
The frequency is approximately 0.5MHz to 1MHz. Therefore, due to the above sampling, the folded frequency spectrum is mixed into the frequency range from the upper limit frequency f _U to the frequency f _L , but there is no folded frequency spectrum at all in the frequency range from O to f _L. It is transmitted as is without being interfered with by other signals. The above frequency f _L is selected to be approximately 0.5 MHz to 1 MHz, which is a frequency that can ensure the minimum necessary vertical resolution.

The recording and reproducing device 23 comprises a recording means 4 and a reproducing means 5, and is an existing narrowband VTR with a horizontal resolution of, for example, about 240 lines, and the above-mentioned sampled signal is recorded on a magnetic tape via a well-known recording system. It is recorded and then played back.

Next, the operation during playback will be explained. The reproduced sampled signal is taken out from the reproduced video signal output terminal 26 and supplied to the synchronizing signal separation circuit 15 through the switch circuit 14 which is switched and connected to the terminal P side, and is also supplied to the memory device 27 through the AD converter 6. supplied to The horizontal synchronization signal in the reproduced sampling signal is PLL16, timing generator 1
7, and generates a sampling pulse having a frequency f _S that is a natural number multiple of the horizontal scanning frequency f _H and satisfies the above equation (1) in the same manner as during recording. Further, the timing generator 17 to which both horizontal and vertical synchronization signals are supplied generates pulses of different logic values during the blanking period and the video period of the reproduced sampling signal. Further, the timing generator 17 generates a pulse with a frequency twice as high as the frequency f _S and a pulse with a vertical scanning period, respectively, and applies write/read control pulses to the input terminals 28 ₁ and 28 ₂ of the memory device 27, respectively. , output as a load pulse. That is, the circuit sections from the switch circuits 14 to 20 are circuits that share the first signal generating means 2 and the second signal generating means 11, respectively. Also,
A part of the timing generator 17 and the memory device 27 constitute the memory circuit 7 and the addressing means 8.

The memory device 27 is composed of a random access memory (RAM) that constitutes the memory circuit 7 and an address specifying means 8 such as an address counter. When specifying an address in such a manner that there is one address less between the field and the even field, a configuration as shown in FIG. 11 is used. In the figure, the same components as those in FIG. 10 are denoted by the same reference numerals, and the explanation thereof will be omitted. The pulse of the frequency 2f _S inputted to the terminal ₂₈₁ is sent to the inverter 65.
is supplied to the RAM 66 as a write/read control pulse R/W. Further, to the address counter 67, a pulse from the terminal ₂₈₂ is applied as a load pulse, and a sampling pulse is applied from the switch circuit 20 through the terminal ₂₈₄ as a clock pulse. As a result, the address counter 67 generates, for example, a 16-bit address signal, and supplies the upper 8 bits of the address signal (upper address) to the adder 68 and the selector 69, while the lower 8 bits of the address signal (lower address) is supplied to the RAM 66. The upper address of the address signal changes corresponding to the line, and the lower address changes corresponding to the pixel position (number of samples) in one line.

The adder 68 is a circuit that adds a constant -1 to the upper address (that is, subtracts 1), and supplies the obtained upper address to the selector 69. The selector 69 is supplied with the head switching pulse taken out from the terminal 25 through the terminal ₂₈₃ , and the output signal of the AND circuit 70 which takes the logical product with the clock pulse from the terminal ₂₈₄ is applied as a select signal, for example. The output signal of the address counter 67 and the adder 6 only when playing an odd field.
The output signal of the address counter 67 is alternately switched and outputted every 1/2f _S , and only the output signal of the address counter 67 is output during even field playback.
is applied as the upper address. This results in
The upper address of the RAM 66 is one address smaller when writing than when reading when odd-numbered fields are reproduced, and the same value when writing and reading when reading even-numbered fields. That is, the write/read control pulses supplied from the inverter 65 to the RAM 66 have a period of 1/2f _S for both odd and even fields, as shown by W/R in FIGS. 12A and B.
This is a symmetrical square wave with a high level indicating a read period and a low level indicating a write period, while the lowest bit of the upper address output from the selector 69 to the RAM 66 is as shown in FIG. 12A when an odd field is reproduced. It changes with a period of 1/f _S , as shown by LSB, and changes with a period of 2/f _S , as shown by LSB in Figure B, during even field reproduction.

On the other hand, the pixel data read out from the RAM 66 is supplied to a latch 71, where it is latched at the rising edge of a latch pulse from a gate circuit 72, for example. The gate circuit 72 outputs a high level signal only when the clock pulse from the terminal ₂₈₄ is low level and the pulse from the terminal ₂₈₁ is high level. Therefore, the latch pulse is
When playing any even numbered field, Figure 12 A,
As shown by the latch ck in B, this is a pulse train with a period of 1/f _S that rises within the high level period of the write/read control pulse. Therefore, the pixel data read out from the RAM 66 after being delayed by one field is applied to the terminal 29b of the switch circuit 29 after being latched by the latch 71 every cycle 1/ _fs .

Returning to FIG. 10 again, the switch circuit 29 is applied with the sampling pulse of the sampling frequency f _S taken out from the switch circuit 20 as a switching pulse, and is applied to the terminal 29a every half period 1/2f _S. The incoming output signal of the AD converter 6 and the 1-field delayed signal from the memory device 27 coming into the terminal 29b are selectively outputted alternately. As a result, the switch circuit 29 inserts each pixel data of the previous field into each intermediate position of each pixel data (sample point) of the field currently being reproduced. In other words, considering field correlation,
A pixel data string with substantially a sampling frequency of 2f _S is taken out and supplied to the DA converter 30 . A resampled signal that is converted into an analog signal by the DA converter 30 and sampled at a sampling frequency of 2f _S is taken out, and is connected to a capacitor 35 and a resistor 36.
Here, the high frequency components above the frequency f _L are separated and then supplied to a mixing circuit 33 through a buffer amplifier 37 and a switch circuit 31 .

On the other hand, the output pulse of the timing generator 17 is applied to the switch circuit 31, which is turned off during the blanking period and turned on during the video period, and is applied to the switch circuit 40 through the inverter 32.

Further, the reproduced signal taken out from the reproduced video signal output terminal 26 of the recording/reproducing device 23 is supplied to the terminal 40a of the switch circuit 40, while the resistor 38
and a capacitor 39, where only the low frequency components below the frequency f _L are separated and then supplied to the terminal 40b of the switch circuit 40. The switch circuit 40 is controlled by the output pulse of the inverter 32, and is switched to the terminal 40b during the video period, and to the terminal 40a during the horizontal and vertical blanking periods. The output signal of the switch circuit 40 is output from the delay circuit 3.
4 to the mixing circuit 33. . As a result, the video period is transmitted from the mixer circuit 33 to the output terminal 41 between the resampled signal of the high frequency component above the frequency f _L and the low frequency component for which there is no folded frequency spectrum due to sampling below the frequency f _L. A mixed signal is extracted, and a synchronization signal, etc., which is not sampled or resampled during both horizontal and vertical blanking periods, is extracted.

In this embodiment, only the high frequency components are resampled, so the AD converter 6 and the DA converter 30
The number of bits is the AD converter 27 and DA converter 30 required when resampling the entire band.
It was confirmed that 5 bits, which is about half of the number of bits (8 bits), is sufficient. In addition, in the memory device 27
The storage capacity of the RAM is only 5/8 of the storage capacity when resampling is performed for the entire band.

Incidentally, when an existing helical scanning type VTR is used as the recording/reproducing device 23, terminals are provided as shown in FIG. In the same figure,
Components that are the same as those in FIG. 10 are designated by the same reference numerals, and their explanations will be omitted. Figure 13 shows an existing VTR.
A luminance signal obtained by separating the composite color video signal inputted to the recorded video signal input terminal 80 of the VTR by the Y/C separation circuit 42 is inputted to the input terminal 1. In addition, the luminance signal input to the input terminal 24 is sent to the pre-emphasis and clip circuit 43, clamp circuit 44, FM modulator 45, and high-pass filter 46 inside the VTR.
are supplied to the adder circuit 47, where Y/
The carrier color signal separated by the C separation circuit 42 is frequency-division multiplexed with, for example, a low frequency converted carrier color signal obtained by converting the carrier color signal into a signal form suitable for magnetic recording and reproduction in the color signal recording process circuit 48. The multiplexed signal taken out from the adder circuit 47 is supplied to the recording head 50 via the recording amplifier 9, whereby the magnetic tape 51
recorded in During this recording, a head switching pulse synchronized in phase with the rotation of the recording head 50 is outputted to the output terminal 25 from the drum motor control 53 which controls the rotation of the rotary drum to which the recording head 50 is attached.

The recorded multiplexed signal on the magnetic tape 51 is reproduced by a reproduction head 52 whose rotation is controlled based on the output signal of a drum motor control 53, and is supplied to a head switch 54. As is well known, for example, two reproduction heads 52 are provided facing a rotating drum at 180 degrees, and the magnetic tape 51 is wound around the rotating drum over an angular range of just over 180 degrees while running. The reproduction signals alternately taken out from the two reproduction heads 52 are made into a continuous signal by a head switching pulse from a drum motor control 53 which is supplied to a head switch 54. The reproduced multiplexed signal taken out from the head switch 54 is supplied to a high-pass filter 57 via a preamplifier 55 and an equalizer 56, where the frequency-modulated luminance signal is separated and then sent to an FM demodulator 58. It is supplied as a reproduced luminance signal. This reproduced luminance signal is outputted to the output terminal 26 via the de-emphasis circuit 59. On the other hand, equalizer 5
The output reproduced multiplexed signal of 6 is supplied to a color signal reproduction process circuit 60, where the low frequency conversion carrier color signal is separated and then subjected to known signal processing to reproduce the reproduced carrier color in the original phase in the original band. The signal is converted into a signal and further supplied to the Y/C mixer 61.

The Y/C mixer 61 mixes this reproduced carrier color signal and the first
A reproduced composite color video signal is obtained by mixing the reproduced luminance signal taken out from the output terminal 41 shown in FIG.

Note that the present invention is not limited to each of the above embodiments; for example, f _S may be an odd multiple of f _H /2,
Furthermore, sampling and resampling may be performed on the synchronization signal section, and various modifications are possible, such as integrating the external circuit of the recording/reproducing device 23 into the VTR. .

Effects of the Invention As described above, according to the present invention, the horizontal resolution can be improved to about 300 lines or more using a narrowband recording/reproducing device (for example, horizontal resolution of about 240 lines), and the horizontal resolution can be improved to about 300 lines or more. In one of the fields, the relationship between the upper bits of the write address and read address of the memory circuit and the line is the same, and in the other field, one of the upper bits of the write address and read address is compared to the other. However, since the addresses are specified so that they are relatively different by one address, it is possible to improve the jaggedness of the edges in the horizontal direction of the video signal (especially the luminance signal) of an image without vertical correlation to the extent that it is almost invisible visually. Furthermore, for images with diagonal lines, the present invention has the advantage of being able to improve the jaggedness of the step-like diagonal lines to such an extent that they are almost invisible.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing the configuration of the device of the present invention, and FIGS. 2, 5, and 7 are fields showing the write address or read address of each embodiment of the device of the present invention and each pixel data of a line. Figures 3, 6 and 8 are respectively shown in Figure 2.
Figures 4 and 9 show the pixel data of each line for each field when the pixel data of Figures 5 and 7 are read out from the memory circuit, Figures 4 and 9 are Figures 3 and 8, respectively. FIG. 10 is a circuit system diagram showing an embodiment of the device of the present invention, and FIG. 11 is an embodiment of the memory device in the circuit system shown in FIG. 10. circuit diagram,
12 is a signal waveform diagram for explaining the operation of the circuit system shown in FIG. 11, FIG. 13 is a block system diagram showing an example of the recording/reproducing device in the circuit system shown in FIG.
4 and 16 are diagrams showing the relationship between pixel data to be written and lines and a display image, and FIGS. 15A and 15B and FIG. 17 are diagrams showing each pixel data read out from a memory circuit by a conventional device. , 15th
FIG. C and FIG. 18 are diagrams each showing an example of a main part of an image reproduced by a conventional apparatus. DESCRIPTION OF SYMBOLS 1...Composite video signal input terminal, 2...First signal generation means, 3...Sampling means, 4...Recording means, 5...Reproducing means, 6...AD converter, 7...
Memory circuit, 8...addressing means, 9...reproduction sampling signal generation means, 10...resampling means,
11... Second signal generating means, 12... Playback composite video signal output terminal, 15... Synchronization signal separation circuit,
16... Phase locked loop (PLL),
17... Timing generator, 22... Hold capacitor, 23... Recording and reproducing device, 27...
...Memory device, 30...DA converter, 33...Mixing circuit, 41...Reproducing composite video signal output terminal, 6
6...Random access memory (RAM),
67...address counter, 68...adder, 6
9...Selector, 71...Latch.

Claims (1)

[Claims] 1. In a video signal recording and reproducing device that records an input composite video signal such as a luminance signal on a recording medium and reproduces it, a signal with a sampling frequency f _S related to the horizontal scanning frequency f _H of the input composite video signal is used. It's hot,
a first signal generating means for generating a signal whose phase differs by 180 degrees for each field of the input composite video signal; and sampling the input composite video signal using the output signal of the first signal generating means. a recording means for recording a sampled signal extracted from the sampling means on a recording medium, a reproduction means for reproducing a previously recorded signal on the recording medium, and a reproduction signal extracted from the reproduction means. Convert to pixel data
an AD converter, a memory circuit that writes output pixel data of the AD converter and reads it with a delay of one field; and a memory circuit that is supplied with at least the reproduction signal and that alternately generates a read address and a write address. and the relationship between the upper address of one of the read address and write address in the odd field and the line, and the relationship between the upper address of the read address and the write address in the even field and the line. addressing means that generate addresses relatively different by one address, and first and second reproduced sampling signals having a time difference of one field from input pixel data and output pixel data of the memory circuit. and second signal generating means for generating a signal from the reproduced signal that is equal to the sampling frequency f _S and whose phase differs by 180° for each field of the reproduced signal. Then, the output signal of the second signal generating means is supplied as a switching signal, and the first and second reproduced sampled signals are alternately selected and output every half cycle, and reproduced at a frequency of substantially _2fS . 1. A video signal recording and reproducing device comprising: resampling means for obtaining a sampled reproduced composite video signal.