JPH026222B2 - - Google Patents
Info
- Publication number
- JPH026222B2 JPH026222B2 JP56204072A JP20407281A JPH026222B2 JP H026222 B2 JPH026222 B2 JP H026222B2 JP 56204072 A JP56204072 A JP 56204072A JP 20407281 A JP20407281 A JP 20407281A JP H026222 B2 JPH026222 B2 JP H026222B2
- Authority
- JP
- Japan
- Prior art keywords
- defect
- free layer
- oxygen
- support substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P36/00—Gettering within semiconductor bodies
- H10P36/03—Gettering within semiconductor bodies within silicon bodies
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体装置の製造方法に係り、特にα
線の影響を受けることの少ない半導体装置を製造
する方法に関する。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a semiconductor device that is less affected by wires.
(b) 従来技術と問題点
半導体装置がLSI、超LSIと高密度化され、素
子が微細化されるに伴い、自然界に存在するα線
の影響が益々厳しいものとなつて来る。即ちα線
を受けると半導体素子内に電子と正孔の対が発生
してこれが半導体素子内に拡散するため、例えば
半導体記憶装置に書き込まれていた情報が書き変
えられてしまう等、半導体装置の誤動作を引き起
す原因となる。(b) Prior Art and Problems As semiconductor devices become more densely packed into LSIs and VLSIs, and as elements become smaller, the effects of naturally occurring α rays become increasingly severe. In other words, when α rays are received, pairs of electrons and holes are generated within the semiconductor device and these diffuse into the semiconductor device, causing damage to the semiconductor device, such as rewriting information written in the semiconductor memory device. This may cause malfunction.
このようなα線の影響を防ぐには、α線が半導
体素子内に侵入するのを極力防止することは勿論
であるが、α線の侵入を皆無とすることは不可能
なので、半導体素子にα線が侵入したときに、発
生する電子と正孔の対を出来るだけ少なくするこ
と、及び発生した電子と正孔を速やかに消滅させ
て素子に到達させないようにすることが必要であ
る。 In order to prevent the effects of alpha rays, it goes without saying that it is necessary to prevent alpha rays from entering semiconductor devices as much as possible, but since it is impossible to completely eliminate alpha rays from entering semiconductor devices, When α rays enter, it is necessary to reduce the number of pairs of electrons and holes that are generated as much as possible, and to quickly annihilate the generated electrons and holes so that they do not reach the device.
前者の目的に対しては無欠陥層の幅を薄くすれ
ば良く、後者の目的に対しては半導体支持基板内
に内部欠陥を形成すれば良い。 For the former purpose, the width of the defect-free layer may be reduced, and for the latter purpose, internal defects may be formed in the semiconductor support substrate.
この目的のため、従来は半導体支持基板内に予
め所定量の酸素(O2)を含有せしめ、加熱処理
を施して上記酸素(O2)を析出させることによ
り形成したSiOxの欠陥核を中心に内部欠陥を発
生させ、この内部欠陥のゲツタリング効果を利用
して上記半導体支持基板の表面に無欠陥層を形成
し、その上に所望のシリコン単結晶層をエピタキ
シアル成長法により成長させ、このエピタキシア
ル成長層に所定の半導体素子を形成していた。 For this purpose, in the past, a predetermined amount of oxygen (O 2 ) was contained in the semiconductor support substrate in advance, and heat treatment was performed to precipitate the oxygen (O 2 ), thereby focusing on SiOx defect nuclei. An internal defect is generated, a defect-free layer is formed on the surface of the semiconductor supporting substrate by utilizing the gettering effect of the internal defect, and a desired silicon single crystal layer is grown on the layer by an epitaxial growth method. A predetermined semiconductor element was formed on the Al growth layer.
上記従来の半導体装置の製造方法では、半導体
支持基板表面に形成される無欠陥層の厚さを厳密
に制御することが困難で、そのため内部欠陥層と
その上の無欠陥層との境界と、無欠陥層内に広が
る素子の底面との間に不要な無欠陥層が残存し、
従つてα線の悪影響を十分に排除し得たとは言い
難い。 In the conventional semiconductor device manufacturing method described above, it is difficult to strictly control the thickness of the defect-free layer formed on the surface of the semiconductor support substrate. An unnecessary defect-free layer remains between the bottom surface of the element that spreads within the defect-free layer,
Therefore, it cannot be said that the adverse effects of alpha rays have been sufficiently eliminated.
(c) 発明の目的
本発明の目的は上記問題点を解消して、無欠陥
層の厚さを精度良く形成可能な半導体装置の製造
方法を提供することにある。(c) Object of the Invention An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device that can form a defect-free layer with high precision in thickness.
(d) 発明の構成
本発明の特徴は、シリコン支持基板表面にイオ
ン注入法により酸素または炭素を所定の深さに注
入する工程と、前記シリコン支持基板に650〔℃〕
ないし800〔℃〕の温度で加熱処理を施して前記注
入せる酸素または炭素を核とする欠陥核を形成す
る工程と、前記シリコン支持基板に1070〔℃〕な
いし1250〔℃〕の温度で加熱処理を施して前記シ
リコン支持基板表面に無欠陥層を形成する工程と
を施し、しかる後該無欠陥層上にエピタキシアル
成長法により所望のシリコン単結晶層を成長せし
め、該シリコン単結晶層に所定の素子を形成する
ことにある。(d) Structure of the Invention The present invention is characterized by a step of implanting oxygen or carbon into the surface of a silicon support substrate to a predetermined depth by ion implantation, and a step of implanting oxygen or carbon into the silicon support substrate at 650 [°C].
a step of forming a defect nucleus with the implantable oxygen or carbon as a nucleus by performing heat treatment at a temperature of 1070 [°C] to 800 [°C]; and a heat treatment of the silicon support substrate at a temperature of 1070 [°C] to 1250 [°C]. to form a defect-free layer on the surface of the silicon support substrate, and then grow a desired silicon single crystal layer on the defect-free layer by an epitaxial growth method, and add a desired silicon single crystal layer to the silicon single crystal layer. The purpose is to form an element.
(e) 発明の実施例 以下本発明の一実施例を図面により説明する。(e) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.
第1図〜第5図は本発明の一実施例を製造工程
の順に示す要部断面図である。 1 to 5 are sectional views of essential parts showing an embodiment of the present invention in the order of manufacturing steps.
第1図において1はシリコン(Si)よりなる支
持基板(以下単にSi基板と略記する)で、通常
CZ法により内部に含有する格子間酸素(O2)濃
度を制御して製作される。このSi基板1表面に例
えば加速電圧約200〔KeV〕で酸素イオン(O-)
を凡そ3〜8×1014〔cm-2〕注入することにより、
周知の如く酸素イオン(O-〕2の注入深さを制
御し得る。 In Figure 1, 1 is a supporting substrate (hereinafter simply referred to as Si substrate) made of silicon (Si), which is usually
It is manufactured by controlling the concentration of interstitial oxygen (O 2 ) contained inside using the CZ method. For example, oxygen ions (O - ) are generated on the surface of this Si substrate 1 at an acceleration voltage of about 200 [KeV].
By injecting approximately 3 to 8×10 14 [cm -2 ] of
As is well known, the implantation depth of oxygen ions (O - ) can be controlled.
次いで上記Si基板1に窒素(N2)雰囲気中に
おいて凡そ750〔℃〕で約6〔時間〕加熱処理を施
し、第2図に示す如く前記酸素イオン(O-)2
を析出させることにより、Si基板1内部に欠陥核
3を形成する。 Next, the Si substrate 1 is subjected to a heat treatment in a nitrogen (N 2 ) atmosphere at approximately 750 [°C] for about 6 hours, so that the oxygen ions (O - ) 2 are removed as shown in FIG.
By depositing , defect nuclei 3 are formed inside the Si substrate 1 .
上記工程に引き続いて更に窒素(N2)雰囲気
中において凡そ1200〔℃〕で約30〔分〕の加熱処理
を施すことにより、第3図に見られる如く前記欠
陥核3を中心として内部欠陥4を発生せしめる。
このように内部欠陥4を発生させることにより、
Si基板1表面には周知の如く無欠陥層5が形成さ
れる。 Subsequent to the above process, heat treatment is further performed in a nitrogen (N 2 ) atmosphere at about 1200 [°C] for about 30 [minutes], so that the internal defects 4 center around the defect core 3 as shown in FIG. to occur.
By generating the internal defect 4 in this way,
As is well known, a defect-free layer 5 is formed on the surface of the Si substrate 1.
本実施例においては、上述のように欠陥核を形
成するため所望量の酸素イオン(O-)を所望の
深さに注入することにより、Si基板1表面から所
望の深さに欠陥核3を形成し、もつて無欠陥層5
を所定の厚さに制御することを可能ならしめたも
ので、この結晶成長温度と時間及びこの後の素子
製作プロセス温度で基板上の無欠陥層が消滅した
構造とすることも可能で、この点が従来の製造方
法と異なる。即ち従来の製造方法は、上記一連の
加熱処理工程において、Si基板1内に始から含有
されている酸素(O2)を析出させて欠陥核3′を
形成し、これを中心にSi基板1内部全域に内部欠
陥4′を発生させることによりSi基板1表面に無
欠陥層5を形成していたため、内部に含有せる酸
素濃度の変動等により無欠陥層5の厚さも変動せ
ざるを得なかつた。 In this example, as described above, by implanting a desired amount of oxygen ions (O - ) to a desired depth to form a defect nucleus, the defect nucleus 3 is formed at a desired depth from the surface of the Si substrate 1. After forming a defect-free layer 5
It is possible to control the thickness to a predetermined thickness, and it is also possible to create a structure in which the defect-free layer on the substrate disappears depending on the crystal growth temperature and time and the subsequent device fabrication process temperature. This differs from conventional manufacturing methods in this point. That is, in the conventional manufacturing method, in the series of heat treatment steps described above, oxygen (O 2 ) originally contained in the Si substrate 1 is precipitated to form defect nuclei 3', and the Si substrate 1 is Since the defect-free layer 5 was formed on the surface of the Si substrate 1 by generating internal defects 4' throughout the interior, the thickness of the defect-free layer 5 had to vary due to changes in the oxygen concentration contained inside. Ta.
ここまでの工程で留意すべきことは、この後に
引き続く工程においてSi基板1に加えられる加熱
処理による内部欠陥4の拡散を予め考慮して、上
記無欠陥層5の厚さを選択することである。 What should be kept in mind in the steps up to this point is to select the thickness of the defect-free layer 5, taking into consideration the diffusion of internal defects 4 due to the heat treatment applied to the Si substrate 1 in the subsequent steps. .
次いで第4図に示すように、塩酸(HCl)を用
いて気相エツチングを行つて無欠陥層5表面をエ
ツチングし、次いでエピタキシアル成長法により
所定のSi単結晶層6を形成する。なお上記気相エ
ツチング工程において、残留する無欠陥層5の厚
さが所定の厚さになるよう、結晶成長温度及びそ
の時間を考慮してエツチング量を制御することが
大切であるが、本実施例では無欠陥層5の最初の
厚さが十分に制御されているので、上記気相エツ
チング工程におけるエツチング制御も容易であ
る。 Next, as shown in FIG. 4, the surface of the defect-free layer 5 is etched by vapor phase etching using hydrochloric acid (HCl), and then a predetermined Si single crystal layer 6 is formed by epitaxial growth. In the above vapor phase etching process, it is important to control the etching amount by considering the crystal growth temperature and time so that the remaining defect-free layer 5 has a predetermined thickness. In the example, since the initial thickness of the defect-free layer 5 is sufficiently controlled, the etching control in the vapor phase etching step is also easy.
このあと通常の製造工程に従つて、例えばゲー
ト酸化膜11、n+型のソース領域及びドレイン領
域12,13、二酸化シリコン(SiO2)膜のよ
うな絶縁膜14、アルミニウム(Al)のような
導電材料よりなるゲート電極、ソース電極、ドレ
イン電極15,16,17等を形成し、第5図に
示すように、本実施例による半導体装置が完成す
る。 Thereafter, according to the normal manufacturing process, for example, a gate oxide film 11, n + type source and drain regions 12, 13, an insulating film 14 such as a silicon dioxide (SiO 2 ) film, and an aluminum (Al) film are formed. Gate electrodes, source electrodes, drain electrodes 15, 16, 17, etc. made of a conductive material are formed, and the semiconductor device according to this embodiment is completed as shown in FIG.
上述のようにして得られた本実施例の半導体装
置の完成体においては、前述した如く半導体素子
形成工程における加熱処理により内部欠陥層4が
無欠陥層5内に拡散し(第5図参照)、ソース領
域12、ドレイン領域13直下には不要な無欠陥
層は殆ど存在しない。従つて前述した如くたとえ
α線が侵入しても、その影響により誤動作を引き
起す恐れを殆ど除去することが出来た。同時に動
作層が形成されているエピタキシアル層は当初の
結晶欠陥の無い状態を保持している。 In the completed semiconductor device of this example obtained as described above, the internal defect layer 4 was diffused into the defect-free layer 5 by the heat treatment in the semiconductor element forming process as described above (see FIG. 5). , almost no unnecessary defect-free layer exists directly under the source region 12 and drain region 13. Therefore, as mentioned above, even if alpha rays enter, the possibility of malfunctions due to the influence can be almost eliminated. At the same time, the epitaxial layer on which the active layer is formed maintains its original crystal defect-free state.
なお内部に所定濃度の酸素(O2)等を含有す
るSi基板に上記一実施例のような加熱処理を施せ
ばSi基板に内部欠陥を発生せしめ得ることは既に
知られており、その処理条件としてまず凡そ650
〜800〔℃〕における第1段階の処理と、このあと
に引き続く凡そ1070〜1250〔℃〕における第2段
階の処理とからなる二段階の加熱処理が必要であ
ること、また第1段階の処理は一旦900〔℃〕程度
の温度にした後、温度を下げ、上述の第1段階の
処理を行つても良いこと等も公知である。本発明
を実施するに際しても上記加熱処理条件はすでに
知られている上述のどの条件に従つても良いこと
は勿論である。 It is already known that if a Si substrate containing a predetermined concentration of oxygen (O 2 ) etc. is subjected to heat treatment as in the above example, internal defects can be generated in the Si substrate, and the processing conditions Approximately 650
A two-stage heat treatment consisting of a first-stage treatment at ~800 [°C] followed by a second-stage treatment at approximately 1070-1250 [°C], and the first stage treatment. It is also known that the temperature may be lowered once to about 900 [° C.] and then the above-mentioned first stage treatment may be performed. Of course, when carrying out the present invention, the above-mentioned heat treatment conditions may be in accordance with any of the above-mentioned already known conditions.
本発明は上記一実施例に限定されるものではな
く、種々変形して実施し得る。 The present invention is not limited to the one embodiment described above, but can be implemented with various modifications.
即ち本発明は上記一実施例の説明に掲げたMIS
FETのみならず、MOS FETやバイポーラ型半
導体装置の製作に用いることも出来る。 That is, the present invention is based on the MIS described in the description of the above embodiment.
It can be used to manufacture not only FETs but also MOS FETs and bipolar semiconductor devices.
また欠陥核形成のために注入するイオンは、酸
素(O2)に変えて炭素(C)用いても良い。 Furthermore, carbon (C) may be used instead of oxygen (O 2 ) as the ions implanted to form defect nuclei.
更に上記イオン注入工程における加速電圧やド
ーズ量も、その目的に応じて適宜選択しうること
は言うまでもない。 Furthermore, it goes without saying that the accelerating voltage and dose amount in the ion implantation process can be appropriately selected depending on the purpose.
(f) 発明の効果
以上説明した如く本発明により、無欠陥層の厚
さを良好な精度で制御することが可能となり、従
つてα線の影響を受けることの少ない半導体装置
の製造方法が提供される。(f) Effects of the Invention As explained above, the present invention makes it possible to control the thickness of a defect-free layer with good accuracy, and therefore provides a method for manufacturing a semiconductor device that is less affected by alpha rays. be done.
第1図〜第5図は本発明の一実施例をその製造
工程の順に示す要部断面図である。
図において、1はシリコン(Si)よりなる支持
基板、2は注入されたイオン、3は欠陥核、4は
内部欠陥、5は無欠陥層、6はエピタキシアル成
長層を示す。
FIGS. 1 to 5 are sectional views of essential parts of an embodiment of the present invention showing the manufacturing steps thereof in order. In the figure, 1 is a supporting substrate made of silicon (Si), 2 is an implanted ion, 3 is a defect nucleus, 4 is an internal defect, 5 is a defect-free layer, and 6 is an epitaxial growth layer.
Claims (1)
法により所望のシリコン単結晶層を成長せしめる
に先立ち、前記シリコン支持基板表面にイオン注
入法により酸素または炭素を所定の深さに注入す
る工程と、前記シリコン支持基板に650〔℃〕ない
し800〔℃〕の温度で加熱処理を施して前記注入せ
る酸素または炭素を核とする欠陥核を形成する工
程と、前記シリコン支持基板に1070〔℃〕ないし
1250〔℃〕の温度で加熱処理を施して前記シリコ
ン支持基板表面に無欠陥層を形成する工程とを施
し、しかる後該無欠陥層上にエピタキシアル成長
法により所望のシリコン単結晶層を成長せしめ、
該シリコン単結晶層に所定の素子を形成すること
を特徴とする半導体装置の製造方法。[Claims] 1. Prior to growing a desired silicon single crystal layer on the surface of a silicon support substrate by epitaxial growth, oxygen or carbon is implanted to a predetermined depth into the surface of the silicon support substrate by ion implantation. a step of heating the silicon support substrate at a temperature of 650 [°C] to 800 [°C] to form defect nuclei whose nucleus is oxygen or carbon that can be implanted; ℃〕or
forming a defect-free layer on the surface of the silicon support substrate by performing heat treatment at a temperature of 1250 [°C], and then growing a desired silicon single crystal layer on the defect-free layer by epitaxial growth. Seshime,
A method for manufacturing a semiconductor device, comprising forming a predetermined element in the silicon single crystal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56204072A JPS58103124A (en) | 1981-12-16 | 1981-12-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56204072A JPS58103124A (en) | 1981-12-16 | 1981-12-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58103124A JPS58103124A (en) | 1983-06-20 |
| JPH026222B2 true JPH026222B2 (en) | 1990-02-08 |
Family
ID=16484295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56204072A Granted JPS58103124A (en) | 1981-12-16 | 1981-12-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58103124A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6116532A (en) * | 1984-07-03 | 1986-01-24 | Matsushita Electric Ind Co Ltd | Semiconductor substrate and manufacture thereof |
| JPS6194176A (en) * | 1984-10-15 | 1986-05-13 | N T C Densan Service:Kk | Business form issuing device |
| JPS62181421A (en) * | 1986-02-04 | 1987-08-08 | Mitsubishi Electric Corp | Manufacture of silicon epitaxial wafer |
| KR920002350B1 (en) * | 1987-05-21 | 1992-03-21 | 마쯔시다덴기산교 가부시기가이샤 | Method of manufacturing semiconductor |
| JPH02306622A (en) * | 1989-05-22 | 1990-12-20 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacture |
| JPH11145146A (en) * | 1997-11-10 | 1999-05-28 | Nec Corp | Semiconductor substrate and its manufacture |
| US6830986B2 (en) | 2002-01-24 | 2004-12-14 | Matsushita Electric Industrial Co., Ltd. | SOI semiconductor device having gettering layer and method for producing the same |
| JP7845245B2 (en) * | 2023-03-22 | 2026-04-14 | 信越半導体株式会社 | Epitaxial wafers and SOI wafers, and methods for manufacturing them. |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5787119A (en) * | 1980-11-19 | 1982-05-31 | Toshiba Corp | Manufacture of semiconductor device |
-
1981
- 1981-12-16 JP JP56204072A patent/JPS58103124A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58103124A (en) | 1983-06-20 |
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