JPH026233B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating gate nonvolatile semiconductor memory having a MOS structure. In more detail,
The present invention relates to a nonvolatile semiconductor memory that allows charge to be written to a floating gate electrode with low voltage and high injection efficiency.

Conventionally, a writing voltage (injecting charge into the floating gate electrode) of a floating gate nonvolatile memory using a channel injection method has required a writing voltage of at least 7V. Nowadays, the operating voltage of rotating systems is becoming more and more common to 5V, and the need for non-volatile memory that can be written and read at 4.0V or less is increasing. FIG. 1 shows a cross-sectional view of a conventional floating gate nonvolatile memory that can be written to by channel injection at about 7V. P-type silicon semiconductor substrate 1 (a P-well made on an n-type substrate may also be used)
An n ⁺ source region 2 and a drain region 3 are formed in and connected to the outside through electrodes 8 and 9.

First channel region 11 in contact with source region 2
A selection gate electrode 7 is formed with a gate oxide film 4 interposed therebetween. A floating gate electrode 6 made of polycrystalline silicon is provided on the drain region 3 and the second channel region 12 adjacent to the drain region 3 with a thin (100 Å to 200 Å) gate oxide film 5 interposed therebetween.
is formed and electrically isolated by the oxide film 10.

An extremely short third channel region is formed between the first channel region and the second channel region. The potential V _F of the floating gate electrode 6 is the capacitance between the drain region 3 and the floating gate electrode 6. Therefore, it is controlled by the drain voltage V _D applied to the drain region 3. Now, when no electrons are injected into the floating gate electrode 6, when drain voltage V _D =5V is applied, the potential V _F of the floating gate electrode 6 is also approximately
It will be around 5V. Therefore, the surface potential _SF of the second channel region 12 under the floating gate electrode 6 approaches the potential of the drain region 3. On the other hand, selection gate electrode 7
Since a voltage approximately equal to the threshold voltage is applied to , the surface potential _SS of the first channel region 11 under the selection gate electrode 7 becomes approximately equal to the potential of the source region 2 . Therefore the first channel region 1
From the first channel region 1 to the second channel region 12, the surface potential _S changes sharply from the surface potential _SS to the surface potential _SF . Electrons are accelerated by the electric field at this boundary, become hot electrons under the floating gate 6, and jump into the floating gate 6. In detail, only hot electrons that have obtained energy equal to or higher than the potential barrier of 3.2 eV between the substrate silicon and silicon dioxide can pass through the thin gate oxide film 5 and enter the floating gate 6.

FIG. 2 shows an example of the distribution of the surface potential _S in the memory element having the configuration shown in FIG. 1. region,,
, , are the source region 2, first channel region 11, and third channel region 1 in FIG. 1, respectively.
3, the second channel region 12 corresponds to the drain region 3. The solid line shows the distribution of the surface potential _S when the impurity concentration of the P-type substrate 1 is high. The change in surface potential on the region side is steep, but since the impurity concentration of the substrate 1 is high on the region side, the floating gate electrode 6
The potential of the surface cannot sufficiently invert the surface below it, and the change in surface potential becomes gradual. The broken line shows the distribution of the surface potential _S when the impurity concentration of the P-type substrate 1 is low. Although there is no potential drop in the surface potential _S on the region side, the change in the surface potential _S on the region side becomes gradual. When the surface potential _S changes slowly, the accelerating electric field becomes weaker and the probability of generating hot electrons with high energy is small, making it impossible to lower the write voltage.

The present invention has been made to overcome the above-mentioned drawbacks and provides a low write voltage memory.

Figures 3 to 5 regarding the nonvolatile memory of the present invention
This will be explained in detail using figures.

FIG. 3 is a sectional view showing an embodiment of the nonvolatile semiconductor memory of the present invention. As shown in FIG. 3, the structure is such that an n-type impurity region 14 is provided under the floating gate. The substrate 1 used has a high impurity concentration.

FIG. 4 shows the distribution of surface potential _S when a voltage near the threshold voltage is applied to the selection gate electrode 7 of the memory shown in FIG. 3, and a voltage necessary for writing is applied to the drain region 3. The regions , , , correspond to the source region 2, first channel region 11, third channel region 13, second channel region 12, and drain region 3 in FIG. 3, respectively. P
As mentioned above, when the impurity concentration of the mold substrate 1 is increased,
Although the surface potential of the region increased and a steep change in surface potential _S could not be obtained, by providing the n-type impurity region 14, the surface potential _SF of the region could be sufficiently lowered to near the potential of the drain region 3. It becomes possible. Therefore, the change in surface potential _S from region to region becomes extremely steep and approaches the drain-source voltage V _DS . This strengthens the accelerating electric field and shortens the accelerating region, reducing energy loss due to scattering and increasing the probability of hot electron generation, allowing writing at a low drain voltage (for example, 4 V). Furthermore, since the injection efficiency of channel electrons into the floating gate is increased, it becomes possible to perform writing at high speed with low current consumption.

Next, to read the memory, when a voltage is applied to the selection gate electrode 7 to invert the channel region under it strongly enough, and a read voltage V _R is applied to the drain region 3, the inside of the floating gate electrode 6 is This is possible because a channel current corresponding to the amount of electrons flows between the source and drain regions. In a write state in which a large number of electrons are injected into the floating gate electrode 6, the conductance is low, and conversely, in a state in which no electrons are injected, the conductance is high.

FIG. 5 shows a sectional view of another embodiment of the nonvolatile semiconductor memory of the present invention. In FIG. 3, a highly doped P-type substrate is used, whereas in FIG.
A type region 14 and a heavily doped P-type region 15 under the selection gate 7 are provided. Even if n-type region 14 exists only slightly from the boundary between floating gate 6 and selection gate 7 to the drain side, it is possible to lower the write voltage. Memory reading in this case utilizes the fact that the threshold voltage of the channel region under the floating gate 6 changes depending on the amount of electrons in the floating gate electrode 6.

As described above, according to the present invention, a nonvolatile semiconductor memory with a low write voltage can be manufactured.

Although the present invention has been described using an N-type memory using a P-type silicon substrate, it goes without saying that a P-type memory using an N-type silicon substrate can be formed in exactly the same manner.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional nonvolatile semiconductor memory, FIG. 2 is a potential distribution diagram of the semiconductor surface during writing in the nonvolatile semiconductor memory of FIG. 1, and FIG. 3 is a nonvolatile semiconductor memory of the present invention. A sectional view of one embodiment, FIG. 4 is a potential distribution diagram of the semiconductor surface during writing of the nonvolatile semiconductor memory of FIG. 3,
FIG. 5 is a sectional view showing another embodiment of the present invention. 1...P-type silicon substrate, 2...n ⁺ source region,
3...n ⁺ drain region, 4, 5... gate insulating film,
6... Floating gate electrode, 7... Selection gate electrode, 8...
Source electrode, 9... Drain electrode, 10... Insulating film,
DESCRIPTION OF SYMBOLS 11... First channel region, 12... Second channel region, 13... Third channel region, 14... N type impurity region, 15... P type impurity region.

Claims (1)

[Scope of Claims] 1. Source/drain regions of a second conductivity type different from the first conductivity type provided at intervals on the surface portion of the semiconductor region of the first conductivity type, and a source/drain region formed between the source/drain regions. a first channel region in contact with the source region, a second channel region formed between the source and drain and in contact with the drain region, and a second channel region formed between the first channel region and the second channel region. a third channel region provided on the first channel region; and a first channel region provided on the first channel region.
a second gate insulating film provided on the second channel region and the drain region, a selection gate electrode provided on the first gate insulating film, and a second gate insulating film provided on the second channel region and the drain region; a floating gate electrode provided on the gate insulating film; a separation insulating film between the selection gate electrode and the floating gate electrode provided on the third channel region; and a second conductivity type impurity region provided within the third channel region. 2. The nonvolatile semiconductor memory according to claim 1, wherein the second conductivity type impurity region reaches the drain region. 3. The nonvolatile semiconductor memory according to claim 1 or 2, wherein impurity ions of the first conductivity type are implanted into the first channel region. 4. A patent characterized in that charge is injected into the floating gate by applying a voltage near the threshold voltage of the first channel to the first gate electrode and applying a predetermined voltage to the drain region. A nonvolatile semiconductor memory according to any one of claims 1 to 3. 5. Reading charge information of the floating gate electrode by applying a voltage sufficiently higher than the threshold voltage of the first channel to the first gate electrode and detecting a conductive state between the source and drain. A nonvolatile semiconductor memory according to any one of claims 1 to 4, characterized in that: