JPH026248B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern generator for a communication device.

A conventional pattern generator generates a pattern by taking an exclusive OR of arbitrary outputs of an N-stage serial input parallel output shift register and feeding back the exclusive OR output as an input signal to the shift register. ing. Further, when changing the mark rate of the output, it is executed by calculating the AND of the signal obtained by delaying the output of the pattern generator and the output.

However, conventional pattern generators have the disadvantage that once the circuit is set, they can only generate one type of pattern, and it is necessary to add a new circuit to generate a different pattern or a long series of patterns. It was hot. Another drawback was that the generated pattern series could be easily solved just by knowing the circuit configuration.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a pattern generator which can generate a wide variety of patterns in a simple manner, and which does not cause the generated pattern series to easily unravel.

According to the present invention, a trigger pulse is applied to a memory that inputs or outputs n-bit data with a specified address, and while outputting a low level of a shift register serial/parallel mode designation signal (hereinafter simply referred to as a designation signal). Output and n
a reader/writer that writes bit data to a designated address of the memory after the trigger pulse; and a reader/writer that is driven by the trigger pulse and outputs a pulse of length τ within a range where the designated signal is at a LOW level; a mode setter that sets the memory to a write mode or a read mode; a preset device that is driven by the trigger pulse and outputs m-bit pattern data for a time T shorter than the time τ as a preset serial data signal; /Specified signal from writing device is LOW
level, m is input from the preset device.
The preset serial data of the bits is loaded at the rising edge of the clock pulse, and at the same time, the parallel output data for the memory address of the L bits is outputted to the memory as an address signal for the n-bit input of the memory, and the remaining (m-L) A serial/parallel input shift register that outputs each bit separately, and the n-bit output of the memory are input, and the output of the (m-L) bits of the shift register allows a specified one of the input signals to be output.
a selector for selecting and outputting one of the input signals; and exclusive OR means for outputting a signal obtained by exclusive ORing the input signal and the output of the selector as a serial input signal to the shift register, and A pattern generator is obtained, characterized in that when the designation signal is HIGH, one data is output from the selector every clock according to the value output from the shift register.

Next, a detailed explanation will be given with reference to the drawings.

FIG. 1 is a block diagram of the configuration of a pattern generator that is an embodiment of the present invention.

FIG. 2 is a diagram showing a time chart for explaining the operation of the apparatus shown in FIG. 1. To explain below with reference to FIGS. 1 and 2, while the data reader/writer 1 is outputting the LOW level of the shift register serial parallel mode designation signal (hereinafter referred to as designation signal) a to the terminal 2, Output the trigger pulse to terminals 3 and 4. The mode setter 5 is driven by the trigger pulse input from the terminal 4 and outputs a pulse b of length τ to the terminal 6, and the preset device 7 is driven by the trigger pulse input from the terminal 3 and outputs m bits for T seconds. data c is output to the serial/parallel in shift register 8.
In the drawings, wires with short diagonal lines and marked "xm" mean m wires. Furthermore, when the designation signal a input through the terminal 2 is at the LOW level, the serial-parallel in shift register 8 receives the m-bit data c input from the preset device 7.
It is loaded at the rising edge of the clock pulse d sent from the clock pulse generator 10 via the terminal 9, and simultaneously outputs (m-L) m-bit data to the memory 11 and selector 12 in L pieces as a signal e. When the signal b input through the terminal 6 is at a low level, the memory 11 converts the n-bit data f output from the data reader/writer 1 into the m-bit data output from the serial-parallel in shift register 8. Load the address specified by the L-bit memory address parallel output data. As described above, any data can be written to any address in the memory.

Next, the data reader/writer 1 sends a designated signal a to the serial/parallel in shift register 8 via the terminal 2.
It outputs at HIGH level and makes the line of n-bit data f high impedance. When the designation signal a input from the terminal 2 becomes HIGH level, the serial parallel in shift register 8 shifts m at the rising edge of the clock pulse d input via the terminal 9.
At the same time, the contents of the bit register are shifted by 1 bit, and at the same time, the data signal input via the terminal 13 (described later) is loaded into the register by 1 bit, and the m-bit data e is transferred to the memory 11 and the selector 1.
Output to 2. When the signal b input from the terminal 6 is at HIGH level, the memory 11 transfers the content value of the L-bit address specified by the serial-parallel in shift register 8 to the selector 12 via the n-bit data bus. Output the data. The selector 12 is output from the serial parallel in shift register 8 (m-
L) Specified by bit data. One of the n bits of data input from memory 11
data is output to terminal 14.

The exclusive OR circuit 15 outputs the exclusive OR of the signal input from the terminal 14 and the signal input from the signal source 17 via the terminal 16 to the terminal 13. The signals outputted to the terminal 13 are loaded one after another into the serial/parallel in shift register 8 at the rising edge of the clock pulse d inputted via the terminal 9, and m-bit data e is outputted. As a result, the signals g are output one after another to the terminal 14 in the same manner as described above. In the above, data reader/writer 1
, the preset device 7, and the mode setter 5 can be combined into one circuit.

As explained above, since the pattern generator of the present invention is equipped with a memory whose contents can be preset to any desired pattern, a wide variety of patterns can be obtained with a simple configuration and operation. Also, the receiving side is equipped with a similar memory, but if the contents are preset to be the same as the sending side, the pattern sequence can be understood.
Even if the same receiver is used, the pattern series cannot be understood by anyone who does not know the contents of the presets on the transmitting side, so the secrecy of the patterns is extremely high.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a pattern generator which is an embodiment of the present invention, and FIG. 2 is a diagram showing a time chart for explaining the operation of the apparatus shown in FIG. Explanation of symbols: 1 is data reader/writer, 5 is mode setter, 7 is preset device, 8 is serial parallel in shift register, 10 is clock pulse generator, 11 is memory, 12 is selector, 15 is exclusive logic The sum circuit and 17 each represent a signal source.

Claims (1)

[Claims] 1 A memory that inputs or outputs n-bit data with a specified address, and a shift register that outputs a trigger pulse while outputting the LOW level of the serial/parallel mode designation signal (hereinafter simply referred to as the designation signal) and inputs or outputs n-bit data. a reader/writer that writes data to a designated address of the memory after the trigger pulse; and a reader/writer that is driven by the trigger pulse and receives the designated signal.
Outputs a pulse of length τ within the LOW level range,
a mode setter that sets the memory to a write mode or a read mode; and a time T that is driven by the trigger pulse and is shorter than the time τ.
When the specified signal from the preset device which emits the m-bit pattern data as a preset serial data signal and the read/write device is at LOW level,
The m-bit preset serial data inputted from the preset device is loaded at the rising edge of the clock pulse, and at the same time, the L-bit parallel output data for the memory address is loaded into the n of the memory.
a serial/parallel input shift register that outputs the bit input as an address signal to the memory and separately outputs the remaining (m-L) bits; and the n-bit output of the memory as input;
a selector that selects and outputs a specified one of the input signals based on the output of (m-L) bits of the shift register; and a signal that is an exclusive OR of the input signal and the output of the selector. exclusive OR means for outputting as a serial input signal to the shift register, so that the designated signal is
A pattern generator characterized in that, when HIGH, one data is output from the selector every clock according to the value output from the shift register.