JPH026263B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission system between a plurality of digital control devices connected to a common transmission bus.

In recent years, with the trend toward decentralization of control systems, multiple digital control devices (for example, programmable sequence controllers including microcomputers) connected to a common transmission bus are placed within the same controlled object. Control is performed by mutually exchanging data.

The present invention relates to a data transmission system between such control devices (hereinafter also referred to as controllers), but the conventional transmission system was as follows. In other words, each controller connected to the common bus has an internal transmission memory and a table, and the data transmission/reception area, data, etc. in the transmission memory are determined in advance at the time of system design. The first address is registered in the table. By referring to this table, the system program or application program performs processing such as storing data in the transmission area of the transmission memory of its own controller or reading data from the transmission memory of another controller. It was hot.

However, with such conventional data transmission methods, if the number of controllers connected to a common bus increases due to equipment expansion, etc., and the transmission/reception area and data length in the transmission memory in each controller change, Since the start address of the area also changes, it becomes necessary to rewrite the table in which the start address is registered. in this case,
This was very inconvenient because it was necessary to stop the control operation of the control system consisting of each controller and rewrite the table in each controller.

The present invention has been made in order to eliminate such inconveniences in the prior art, and therefore, an object of the present invention is to provide a system that can be used even if the transmission/reception area and data length of the transmission memory in the controller are changed due to expansion or the like. To provide a data transmission system between a plurality of digital control devices connected to a common bus, which can be handled without rewriting a table and without stopping control operations.

In order to achieve the above object, in the present invention,
A start address registration area is provided in the transmission memory in each controller, and the start address of data whose transmission source is the controller is stored using the identification number of each controller as an address.

Next, the principle of the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram showing a plurality of controllers connected to a common transmission bus. In the same figure,
10 is a common bus, and 0 to 3 each indicate a controller and also serve as an identification number for each controller. That is, the identification number of controller 0 is also 0, the identification number of controller 1 is also 1, the identification number of controller 3 is also 3,
It is assumed that the code indicating the controller and its identification number correspond to each other. Reference numeral 11 denotes a transmission memory provided in each controller, the shaded area is a start address registration area, and the remaining area is a data storage area.

FIG. 1A is a detailed explanatory diagram showing the configuration of the transmission memory 11 in FIG. 1. As seen in the figure, the transmission memory 11 consists of a head address registration area and a data storage area, and the transmission memories belonging to any of the controllers 0 to 3 have the same configuration.

The start address registration area stores the controller identification numbers such as relative address 0 for controller 0, relative address 1 for controller 1, address 3 for controller 3, and so on. The first address registration area of the controller is assigned as the address.

Therefore, for example, by looking at address 3 of the transmission memory 11, the start address in the storage area of data related to the controller 3, that is, data transmitted from the controller 3, or data to be transmitted to the controller 3, can be found. can be easily read and written.

If the number of controllers connected to the common bus increases due to expansion of equipment, etc., it is sufficient to allocate the first address registration area of the corresponding controller with its identification number as an address, and also to change the data length or Even if the leading address is changed accordingly, the memory system as shown in FIG. 1A can be adapted to the change as is, and there is no inconvenience that the memory system cannot be adapted unless the control operation of the control system is temporarily stopped.

This concludes the explanation of the principle of the present invention, and next, one embodiment of the present invention will be explained.

FIG. 3 is a block diagram showing essential parts of an embodiment of the present invention. In the same figure, 0 is the controller,
10 is a common bus, 11 is a transmission memory (its configuration is as shown in FIG. 1A), 21 is a driver, 22
is a receiver, 23 is a transmission data register, 24 is a reception data register, 25 is an address counter,
26 is a transmission/reception end check counter, 28 is a header table, 29 is an internal bus for both data and address, 30a is an internal data bus, and 30b is an internal address bus.

FIG. 2 is an explanatory diagram showing the transmission format of data sent and received between controllers via a common bus. As shown in the figure, the header section is transmitted before the data section, and the header section is
The identification number of the source controller is made up of the number of transmitted data (the number of words of the transmitted data) and the source head address (the head address of the source transmission data area).

Data transmission and reception operations will be explained with reference to FIGS. 1A, 2, and 3.

First, the data reception operation in controller 0 will be explained. The source controller identification number of the header section sent via the common bus 10 is
Through the receiver 22 and the reception data register 24,
The data is taken into the address counter 25 via the internal bus 29. The number of transmission data following the identification number is also sent to the transmission/reception completion check counter 2 through the same route.
Incorporated into 6. The source head address following the number of transmitted data is latched in the reception data register 24 and then taken into the address counter 25 as the controller identification number (for example, if it is 3, set it as 3). ，
The data is stored at address 3 in the first address registration area in the transmission memory 11 via S, 30a. At the same time, the sender's first address is address counter 2.
5, and is used thereafter as a storage address for incoming received data. That is, the first arriving data is latched in the reception data register 24, and then transferred to the bus 2 using the first address stored in the address counter 25 as the address.
9, S, and 30a to the data storage area of the transmission memory 11.

Then, the first address in the address counter 25 is incremented by 1, and the next data is latched into the reception data register 24 and then
Similarly, the received data is stored at the next address in the data storage area of the transmission memory 11 via the buses 29, S, and 30a, and thereafter, the received data is stored in the storage area of the transmission memory 11 one after another in the same manner. In addition,
The number of transmission data previously taken into the transmission/reception end check counter 26 is determined when the number of words of data received as described above and stored in the data storage area of the transmission memory 11 reaches a predetermined number of words, and reception is completed. It is used to check whether the

Next, the transmission operation will be explained. When sending,
The controller identification number (0 in this example) taken out from the header table 28 is sent to the transmission register 23,
It is output to the transmission bus 10 via the driver 21 and simultaneously taken into the address counter 25. Similarly, the number of transmission data taken out from the header table 28 is also output to the transmission bus 10 through the same route, and is also output to the transmission/reception end check counter 26.
be taken in. The source head address from the header table 28 is set to the transmission bus 10 in the same manner as before.
At the same time, as in the case of reception, the controller identification number 0, which was taken in earlier by the address counter 25, is stored in the first address registration area in the transmission memory 11 as an address, and then latched into the address counter 5, and from then on. This address is used as the address for reading transmission data from the data storage area in the transmission memory 11. In other words, each time one piece of transmission data is read, the address counter 2
The start address latched at 5 is incremented by 1, and data is sequentially read out from each address following the start address from the data storage area in the transmission memory 11 and output to the transmission bus 10. It goes without saying that the number of transmission data taken into the transmission/reception end check counter 26 from the header table 28 is used to check whether the number of words of the transmission data has reached a predetermined number and transmission has ended. Probably not.

As a result of the above operations, as shown in FIG. 1A, addresses 0 to 3 (relative addresses in the transmission memory) corresponding to the controller identification numbers of the transmission memory 11 are assigned the transmission information of each controller connected to the transmission bus. The starting address of the data storage area in the memory will be stored. Therefore, an application or a system program can determine the starting address of the data storage area in the transmission memory of each controller by referring to the contents of the address in the transmission memory corresponding to the controller identification number.

According to the present invention, each controller connected to a common bus uses the normal data transmission cycle and reception cycle when transmitting and receiving data, so that the transmission memory of each controller can be stored without any particular transmission time loss. Since the start address of the data storage area is stored in the start address registration area at the address corresponding to the controller identification number, there is no need to register it in the table, and even when changing the data storage area in the transmission memory, the controller that has been changed can The effect is that all you need to do is change the header.

Note that the present invention is applicable to transmission control devices in general.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a plurality of controllers connected to a common bus, FIG. 1A is a detailed explanatory diagram showing the configuration of the transmission memory 11 in FIG. 1, and FIG. 2 is an explanatory diagram showing the data transmission format. FIG. 3 is a block diagram showing essential parts of an embodiment of the present invention. Code explanation, 0-3...controller, 10...
Common bus, 11...Transmission memory, 21...Driver, 22...Receiver, 23...Transmission data register, 24...Reception data register, 25...Address counter, 26...Transmission/reception end check counter, 28... Header table, 29... data/address dual use internal bus, 30a... internal data bus, 30b... internal address bus.

Claims (1)

[Claims] 1 A data transmission method between a plurality of digital control devices connected to a common transmission bus, in which each control device has a start address registration area in its own transmission memory, and upon reception, the control device Receives the header section sent before the data section, uses the identification number of the other party's control device included therein as an address, writes the source head address following the identification number in the registration area, and writes the next address. The data section following the header section is received and written into the transmission memory using the source's first address as the first address, and at the time of transmission, the control device first sends the data section to the other party's control device as the header section before the data section. Sends the identification number of the control device, then uses the identification number as an address to read and send the source start address from the start address registration area in the transmission memory, and thereafter uses the start address as the start address to transmit data from the transmission memory. A data transmission method characterized by reading and transmitting.