JPH0262878B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voice response device comprising a control section, a storage section, and a voice synthesis section including a plurality of voice synthesis circuits.

In recent years, advances in speech analysis and synthesis technology and semiconductor technology have led to the emergence of speech synthesis LSIs based on methods such as LPC, PARCOR, and LSP, which are already being used in various fields. 2. Description of the Related Art In various systems, voice response devices for instructing users on how to use the system by voice are also on the verge of being put into practical use.

When applying the above parameter synthesis method to a voice response device used in a system where one center is shared by many people, it is necessary to prepare many types of messages, so it is necessary to accumulate voice data. Since a large-capacity storage device is used for storage, it is common to reduce the price per speech synthesis unit by sharing this storage device with a plurality of speech synthesis units.

Conventionally, a magnetic bubble memory has been used as this large-capacity storage device to perform the following control.

1. The basic unit of composition is a word, and the length of all words is fixed.

2 The structure of memory is the data for the first frame of each word, then the data for the second frame of each word,...
..., in the order of the final frame data of each word.

3. Speech synthesis of one word is performed by selectively transferring only the data of a specific word number out of the data having the above structure to the speech synthesis unit.

4. Speech synthesis of one message can be accomplished by rotating the magnetic bubble in cycles of one word length, selecting the necessary words for each rotation, and repeating this process for the required number of words.

5. When operating multiple speech synthesis units, data for each unit may be selected during one revolution of the magnetic bubble and transferred to the corresponding unit.

At this time, the following problems arose.

1 Even if there are messages of various lengths, they all need to be divided into the same length. Conversely, if the sound is shorter than the fixed length, it is necessary to compensate for silence.

2. Control of audio data selection and distribution is complicated.

3. It is necessary to synchronize all the speech synthesis units, and it is not possible to use speech data with variable frame length due to the nature of speech.

An object of the present invention has been made to solve the above-mentioned problems, and includes a storage section, a control section, and a speech synthesis section including a plurality of speech synthesis circuits, and the control section is connected from the storage section to the speech synthesis section. In a device that synthesizes speech by transferring data, each speech synthesis circuit can independently request data transfer from the control unit at a fixed or variable period, allowing for multiple operations of multiple speech synthesis circuits. The purpose is to provide a suitable data transfer method.

According to the present invention, the above object includes a speech synthesis section including a storage section, a control section, and a plurality of speech synthesis circuits, and the control section has means for controlling the transfer of data from the storage section to the speech synthesis section. The speech synthesis section is composed of a synthesis circuit control section, a plurality of speech synthesis circuits, and a plurality of speech output circuits, and the synthesis circuit control section receives one data out of the data requests asynchronously generated from the speech synthesis circuit. This is achieved by selecting a request, transferring the data read from the storage unit to the selected speech synthesis circuit, and outputting the signal from the selected speech synthesis circuit as speech. Ru.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a voice response device to which the present invention is applied. 1 is a storage unit that stores audio data; 2 is a control unit that activates a specific audio synthesis circuit, edits the address of audio data, transfers audio data, etc. according to instructions from the outside; 3 is a controller that controls a plurality of audio synthesis circuits; 4 is a control bus for exchanging instructions and data between the control unit and the outside, 5 is a memory bus for reading and writing data in the storage unit, and 6 is a control unit and voice synthesis unit. A synthesizer bus 7 is for exchanging audio data, status information, etc. between the two, and 7 is a signal line for outputting the synthesized audio signal to the outside.

FIG. 2 is a block diagram showing the configuration of the speech synthesis section 3, in which 30 controls a designated speech synthesis circuit from the speech synthesis circuit number, control information, audio data, etc. sent through the synthesis section bus, and also controls the designated speech synthesis circuit. a synthesis control unit that selects state information of the synthesis circuit;
310 to 317 are speech synthesis circuits having circuit numbers 0 to 7, respectively, and 320 to 327 are speech synthesis circuits 310.
This is an audio output circuit consisting of a digital-to-analog conversion circuit, a low-pass filter, a low-frequency amplifier, etc. corresponding to 317.

FIG. 3 is a time chart for explaining the independent operation of the speech synthesis circuits 310 to 317.
2 shows the state signal of the speech synthesis circuit from normal startup to stop, and 2 shows the state signal of the speech synthesis circuit when the transfer of audio data is delayed for some reason during normal operation. Among these, RUN is an in-operation indication, REQ is a data request, ALM is a data shortage indication, and FP is a frame signal indicating the frame period.

The basic operation of the speech synthesis circuits 310 to 317 will be explained below.

When started externally, the RUN signal is set to '1',
At the same time, operations to initialize internal shift registers, etc. are started. Here the data request signal
Since REQ is set to '1', if one transfer unit of audio data, for example 48 bits, is transferred to the speech synthesis circuit in response to this, the speech synthesis circuit will request the data.
Start speech synthesis operation by setting REQ to '0'. The conversion for the first transfer unit is completed while the frame signal FP becomes '1' immediately after the transfer, and the data request REQ is set to '1' at the same time as the frame signal FP becomes '0'. Subsequent data request REQ
If the audio data is input to the audio synthesis circuit in one transfer unit per frame in response to 327, an analog audio signal can be obtained. When the voice synthesis circuit receives voice data whose control information indicates that the operation is stopped, the voice synthesis circuit performs a voice synthesis operation on the voice data and then stops.

2 in FIG. 3, if data transfer is not completed within about one frame period after the data request REQ becomes '1' during normal operation, the frame signal FP becomes '1'.
Instead, the data shortage display ALM is '1'.
become. Thereafter, when the data transfer of one transfer unit is completed, both the data request REQ and the data shortage indication ALM become '0', and then the frame signal becomes '1', and thereafter the normal operation returns. Insufficient data display
Even while ALM is set to '1', the synthesis operation of the speech synthesis circuit continues, and the speech is not interrupted. (The voice immediately before the data shortage indication ALM becomes '1' is extended.) FIG. 4 is a block diagram showing an embodiment of the present invention, and shows the control unit 2 and voice synthesis unit 3 in FIG. Only the portions related to the data transfer operation are extracted from the synthesizer bus 6 and the synthesizer bus 6. The ENC 301 selects only one of the data requests REQ generated asynchronously from the speech synthesis circuits 310 to 317,
and a priority encoder for generating the circuit number, which includes voice synthesis circuits 310 to 310.
317 data requests REQ, and a synthesis in progress display provided for each circuit to display whether each circuit is in the middle of synthesizing one message.
A signal that has an AND condition with BUSY is input, and is output in correspondence with the synthesis circuit numbers 0 to 7 so that the output becomes '000' to '111' in binary. SEL1 to SEL4 302 to 305 are selectors that select the state of a designated one of the speech synthesis circuits 310 to 317. 63 is one of the signals in the synthesis section bus 6, and is a priority encoder.
This is a gate signal that instructs to open the gates G01 to G03 and output the output information of the ENC to the bus BUS in the control unit 2. Similarly, 64 is SEL1~
This is a gate signal for outputting SEL4 output information to the bus BUS. 65 is a select signal that specifies which one of SEL1 to SEL4 is selected. INT21
is an interrupt circuit that accepts various interrupts and changes the sequence of the microprogram in the control section.
SEQ22 is a sequencer that controls the sequence of microprograms, CM23 is a microprogram memory, CMIR24 is an instruction register that maintains the successive output results of the microprogram memory CM for the required time, ALU25 is an arithmetic circuit, and REG26 is a register for arithmetic operations.

FIG. 5 is a time chart for explaining the operation of the circuit shown in FIG. 4.

When the voice response device is activated from outside,
In order to have the voice message synthesized by the voice synthesis circuit with the designated circuit number, the control unit 2 first checks the start address of the block of voice data corresponding to a single or multiple speech pieces constituting the voice message, and then Save the results in the area corresponding to the line number. This process is hereinafter referred to as editing. After editing, a designated circuit number, for example 0, among the speech synthesis circuits 310 to 317 is activated. At this time,
Both the synthesis display BUSY and the operation display R/N are '1'.
On the other hand, the data request REQ is set to '1' at this point, so the AND of the compositing display and the data request is performed.
Priority encoder ENC when condition is met
Since '1' is input to the input terminal of 301, EO
and the output will appear on the encode output output terminal.
The interrupt circuit INT of control unit 2 is activated by the signal from the EC terminal.
21 operates to cause the sequence circuit 22 to execute the interrupt processing microprogram from the synthesis section 3. As a result, the control unit 2 learns that there is an interruption from the synthesis unit 3, and
In order to know the circuit number that caused the interrupt, the gate signal 63 is set to '1', gates G01 to G03 are opened, the circuit number is read, and the circuit number is used as the select signal 65.
Open gates G11 to G14 to read and check the status information. From the circuit number read, the edited result saved earlier and the contents of the composite circuit control word prepared separately for the circuit number are The voice data in the first transfer unit of the first block is read out from the storage unit 1 and transferred to the voice synthesis circuit with circuit number 0. When the transfer of one transfer unit is completed, the data request of this circuit becomes '0', so the control unit 2 switches the priority encoder ENC310.
By checking the EO output of , it is checked whether other low-priority speech synthesis circuits are issuing a data request REQ, and if so, the circuit number is read and the same operation is performed. Thereafter, the activated voice synthesis circuits 310 to 317 issue data requests REQ to each other independently of other circuits every frame period, and each time the memory section performs the above-described operation. For the circuit with circuit number 0, the second transfer unit of the first block, the third,...
and transfer the final transfer unit of the first block. After that, when an interrupt occurs from circuit number 0, the status information indicates that the operating display RUN is '0', so the control unit determines that the next block should be transferred, and transfers the first block for the second block. The audio data is transferred to the synthesis section 3 in order from unit to unit. By repeating this operation until the final block, the desired voice message can be synthesized. Other speech synthesis circuits perform similar operations.

The above is a case where the competition result between the synthesis display BUSY and the data request REQ of the speech synthesis circuits 310 to 317 is used as a signal for interrupting the control unit 2 from the synthesis unit 3. display
By creating an ALM contention result and causing an interrupt to the control unit, and setting this priority higher than the previous interrupt signal, processing of the circuit number where the data shortage indication ALM is '1' can be performed. You can prioritize it.

As explained above, according to the present invention, even when a plurality of speech synthesis circuits are operating at the same time, it is possible to easily respond to requests for data generated independently from each other. This method has the advantage that it does not need to be constant, and that a very large number of speech synthesis circuits can be handled using almost the same method.

In the explanation, the number of speech synthesis circuits is eight, but the number is not limited to eight. The configuration of the competition circuit and the configuration of the control section are not limited to those illustrated in the drawings.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of the voice response device, Figure 2 is a block diagram showing the internal configuration of the synthesis section of the voice response device, Figure 3 is a time chart showing the operation of the voice synthesis circuit, and Figure 4 is the data FIG. 5 is a circuit diagram showing an embodiment of a control circuit related to transfer, and a time chart showing the operation of the voice response device according to the present invention. 1...Storage unit, 2...Control unit, 3...Synthesis unit,
4...Control bus, 5...Memory bus, 6...Synthesizing section bus, 7...Audio signal output line, 30...Synthesizing circuit control section, 310-317...Speech synthesis circuit, 3
20-327...Audio output circuit, 301...Priority encoder, 302-305...Selector, 21...Interrupt circuit, 22...Sequence circuit, 23...Microprogram control storage device,
24...Microinstruction register, 25...Arithmetic circuit, 26...Register, 27...Bus.

Claims (1)

[Scope of Claims] 1. Consists of a speech synthesis section including a storage section, a control section, and a plurality of speech synthesis circuits, the control section having means for controlling the transfer of data from the storage section to the speech synthesis section,
The speech synthesis section includes a synthesis circuit control section, a plurality of speech synthesis circuits, and a plurality of speech output circuits, and the synthesis circuit control section responds to one data request among the data requests asynchronously generated from the speech synthesis circuit. and transmitting the data read from the storage unit to the selected speech synthesis circuit, and the audio output circuit outputs the signal from the selected speech synthesis circuit as audio, and the data read from the storage unit. The data has multiple transfer units of a certain amount that are transferred in response to one data transfer request, and each transfer unit is given an instruction as to whether or not to stop the speech synthesis operation after processing that transfer unit. Further, the speech synthesis unit is configured to include control information to control the control information when the speech synthesis circuit detects a case where the data transfer of one transfer unit is not completed within a certain period of time after the speech synthesis circuit requests the data transfer. An audio data transfer method characterized in that the controller has means for notifying a warning signal to a controller, and the controller is configured to preferentially transmit data to a speech synthesis circuit outputting the warning signal. .