JPH026290B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for detecting a ground fault phase in an ungrounded power distribution line.

Conventionally, there has been a device of this type as shown in FIG. In the figure, 1a, 1b, 1c are three-phase balanced power supplies, 2a, 2b, 2c are distribution lines connected to the power supplies 1a, 1b, 1c having voltages e _a , e _b , e _c , and 3
a, 3b, 3c are capacitances existing between the distribution lines 2a, 2b, 2c and the ground; 4 is a switch that equivalently indicates the occurrence of a grounding fault along with resistance Rg; 5a, 5
b, 5c are capacitors, and the distribution lines 2a, 2
A voltage divider that divides the voltages of b and 2c, 6a, 6b,
6c is the voltage v _a , v b , v _c of voltage divider 5 a, 5 _b , 5 c
An adder that adds up two voltages, 7 is the power supply 1
It is a resistor with a resistance value R _M that grounds the neutral points of a, 1b, and 1c.

Next, the operation will be explained. Voltage divider 5a, 5
The voltages v _a , v _b , v _c of adders 6 a, 6 b,
6c, and voltages v ₁ , v ₂ , v ₃ as shown in the following equations are generated at their output terminals.

v ₁ = v _a + v _b /2, v ₂ = v _b + v _c /2, v ₃ = v _c + v _a /2 Switch 4 is turned on, and the a-phase distribution line 2a is
When a ground fault occurs, the capacitance 3a, 3b, 3c and resistance
As the value of Rg changes, the center of the vector 0 moves to 0' along the circle 8, as shown in the vector diagram in Figure 2, and the voltage v ₁ of the fault phase becomes smaller than the voltages v ₂ and v ₃ . becomes smaller, and becomes |v ₁ |<|e _a |<|v ₂ | or |v ₃ |. This relationship is detected by a logic circuit (not shown), and a response is taken if an accident occurs.

As described above, the conventional ground fault phase detection device detects changes in the absolute value of the ground voltage of each phase before and after an accident occurs, and determines a ground fault phase based on the magnitude relationship between them. However, if both the capacitance and the ground fault resistance of the power distribution line are large at the time of an accident, the difference between the power distribution line and the normal state will not be significant, and the detection accuracy will decrease. To increase detection sensitivity,
It is necessary that the voltage divider ratio and the operation of the adder be highly stable. Even if such stabilization could be achieved, it would not be possible to determine that an open phase has occurred due to poor contact or the like in the connected portion.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and detects the zero-sequence voltage generated in proportion to the fault current due to a ground fault. It is an object of the present invention to provide a ground fault phase detection device that can determine a ground fault phase by multiplying the ground fault phase with a signal based on the voltage, further integrating it, and finally comparing it with a reference voltage.

An embodiment of the present invention will be described below.
FIG. 3 is a circuit diagram of the ground fault phase detection device of the present invention. In the figure, 9 denotes a winding 9a connected in delta to the distribution lines 2a, 2b, _2c , and a reference voltage u _a0 , which is a reference voltage that is advanced by a predetermined phase with respect to the voltages e _a , e b , e _c .
Star-connected windings and voltages e _a , which generate u _b0 , u _c0 ,
A transformer having a star-connected winding 9c that generates voltages u _a0 ′, u _b0 ′, u _c0 ′, which are reference voltages that are advanced by a predetermined phase with respect to e _b , e _c , 10 is a distribution line 10 a, 1
Capacitor 10a connected in star shape to 0b and 10c
~10c and a capacitor 10 connected between the center point of the connection of capacitors 10a to 10c and ground.
Voltage dividers 11a to 11c having voltages 11a to 11c phase shift the voltages U _a0 , U _b0 , and U _c0 of the winding 9b by a clock signal to generate voltages U _a , U _b , and U _c , and are designed to generate voltages U a , U b , and U c . A delay element consisting of a device (BBD) or a charge coupled device (CCD), 11d to 11f are the voltages of the winding 9c.
It generates voltages u _a ′, u _b ′, u _c ′ by shifting the phase of U _a0 ′, U b0 ′, and U _{c0 ′} using a clock signal, and includes delay elements 1 and 1 having the same configuration as delay elements 11a to 11c.
2 is a differentiator that differentiates the voltage v ₀ of the voltage divider 10, 13
a to 13c are the voltage v ₀ of the voltage divider 10 and the delay element 11
Take the product of the voltages Ua, Ub, and Uc of a to 11c,
Multiplier generating signals w _a1 , w _b1 , w _c1 , 13d~
13f is the voltage v ₀ ' of the differentiator 12 and the delay element Ua',
Multipliers 14a, 14b, 14c take the product of Ub', Uc' and generate signals w _a2 , w _b2 , w _c2 ; multipliers 13a, 13d; 13b, 13e;
Integrators 15a, 15b, 15c are integrators 14a, 15c which add and integrate the signals w _a1 , w _a2 ; w _b1 , w _b2 ; w _c1 , w _c2 to generate signals Wa, Wb, Wc.
4b, 14c signals Wa, Wb, Wc and reference voltage Wt
a comparator that generates signals a, b, and c indicating a ground fault when the former becomes less than the latter;
a, 16b are multipliers that square the voltage v ₀ of the voltage divider 10 and the voltage v ₀ ' of the differentiator 12 to generate the signal v ₀ ² +v ₀ '²; 17 is the signal v ₀ ² , V ₀ ' ² An adder 18 generates a signal V ₀ consisting of the amplitude V ₀ of the voltage V ₀ by adding the constant A ₁ times the signal V ₀ ² and the constant A ₀ .
Adder that generates A ₀ +A ₁ V ₀ ² , 19 is the signal A ₀ +
A ₁ V ₀ ² is converted into voltage and frequency to delay element 11a ~
11f.

Next, the operation will be explained. Power supply 1a, 1
The voltages e _a , e _b , and e _c of b and 1c can be expressed by the following equations.

e _a = Esinωt e _b = Esin (ωt-2/3π) e _c = Esin (ωt-4/3π) The transformer 9 shifts the voltages e _a , e _b , and e _c by the phase α ₀ to generate a voltage Let U _a0 ~ U _c0 and U _a0 ′ ~ _{U c0} ′ be as shown in the following equation.

U _a0 = E・sin (ωt+α ₀ ) U _b0 = E・sin (ωt+α ₀ −2/3π) U _c0 = E・sin (ωt+α ₀ −4/3π) u _a0 ′=E・cos (ωt+α ₀ ) u _b0 ′=E・cos (ωt+α ₀ −2/3π) u _c0 ′=E・cos (ωt+α ₀ −4/3π) Voltage u _a ~ u _c , u _a ′ ~ u _c ′ is the voltage as reference voltage
Like u _a0 ~ u _c0 and u _a0 ′ ~ _{u c0} ′, it is related to the line voltage, so it does not change even if a ground fault occurs.
However, if an accident with resistance R _g occurs in phase a, 3
The potential at the neutral point of the phase circuit changes and a voltage v ₀ is generated. The voltage v ₀ is the resistance Rg and the capacitance C ₀ of the three-phase line,
It is also related to the resistance R _N of the neutral point of the power supplies 1a to 1c,
It is expressed as follows.

v ₀ = −V ₀・sin(ωt−Θ) However, Figure 4 shows the voltages e _a , e _b , e _c , u _a0 , u _b0 , u _c0 , u _a ,
This is a vector diagram showing the relationship between u _b , u _c and v ₀ . When the value of resistance Rg changes, the foot of voltage v ₀ moves on line 8.

Zero-phase voltage v ₀ and voltages u _a , u _b , u _c are multiplier 13
Multiplied by a to 13c, a signal as shown in the following formula
They become w _a1 , w _b1 , w _c1 .

w _a1 =v ₀・u _a =−1/2V ₀・E{cos(Θ−α)−
cos(2ωt−Θ−α)} w _b1 =v ₀・u _b =−1/2V ₀・E{cos(Θ−α−2
/3π)−cos(2ωt−Θ−α−2/3π)} w _c1 =v ₀・u _c =−1/2V ₀・E{cos(Θ−α−4
/3π)-cos(2ωt-Θ-α-4/3π)} The first term on the right side of each of the above equations is the DC component proportional to the voltages u _a , u _b , u _c , and the second term is the DC component proportional to the power supply frequency. It is an alternating current component that changes at twice the angular frequency. Information regarding the accident phase is included in the DC component in the first term,
The second term is an obstacle in determining the accident phase, so
It is canceled by the integrators 14a to 14b as follows.

The voltage v ₀ is input to the differentiator 12 and differentiated, so that the voltage v ₀ '=1/ωdv ₀ /dt. The voltage v ₀ ' leads the voltage v ₀ by 90° in phase as shown by the following equation.

Voltage v ₀ ′ and voltages u _a ′, u _b ′, u _c ′ are multiplier 13d,
13e and 13f produce a signal as shown in the following formula
w _a2 , w _b2 , w _c2 .

w _a2 =v ₀ ′・u _a ′=−1/2V ₀・E｛cos(Θ−α
)＋cos(2ωt−Θ−α)} w _b2 =v ₀ ′・u _b ′=−1/2V ₀・E{cos(Θ−α
−2/3π) + cos(2ωt−Θ−α−2/3π)} w _c2 =v ₀ ′・u _c ′=−1/2V ₀・E{cos(Θ−α
−4/3π)+cos(2ωt−Θ−α−4/3π)} The alternating current component of the second term on the right side of the above equation is the signal w _a1 , w _b1 ,
Since the sign is opposite to the alternating current component of w _c1 , the alternating current component is eliminated by adding both equations. This addition is performed by integrators 14a, 14b, and 14c. Expressed as a formula, it is as follows.

w _a = w _a1 + w _a2 = −V ₀・Ecos (Θ − α) w _b = w _b1 + w _b2 = −V ₀・Ecos (Θ − α − 2/3π) w _c = w _c1 + w _c2 = −V ₀ ·Ecos (Θ−α−4/3π) Here, the signal w _a is from the fault phase, and the signals w _b and w _c are from the healthy phase. In the above formula,
When Θ=α, the following equation is obtained, which makes it easy to distinguish between the signal w _a and the signals w _b and w _c .

w _a = -V ₀・E w _b = w _c = 1/2V ₀・E As shown in Figure 4, the foot of voltage v ₀ moves on circle 8 depending on the size of resistance Rg, so The angle Θ is not constant. Therefore, in order to make Θ=α, it is necessary to automatically adjust the angle α depending on the degree of the accident.

Figure 5 shows the voltage u _a0 of the fault phase (here a phase),
It is a vector diagram of u _a and voltage v ₀ . According to FIG. 5, the angle Θ is expressed by the following equation based on the amplitude E of the voltage e _a and the amplitude V ₀ of the voltage v ₀ .

Θ=cos ^-1 V ₀ /E Here, the delay elements 11a to 11c have n stages.
BBD, and the voltages u _a - u _c are obtained by delaying the voltages u a0 - _{u c0} by an angle nω/f. However, f
is the frequency of the clock signal, and ω is the angular frequency of the power supplies e _a to e _c .

At this time, the angle α at which the voltages u _a0 to u _c0 lag behind the voltage e _a is α=nω/f−α ₀ , and in order to match the angle Θ, it is necessary to satisfy the following equation.

nω/f−α ₀ =cos ⁻¹ V ₀ /E Therefore, f=n·ω/α ₀ +cos ⁻¹ V ₀ /E The above equation can be approximately expressed by the following equation.

fA ₀ +A ₁ +V ₀ ² A ₀ =n・ω/α ₀ +π/2, A ₁ =2π/3・n・ω/(α ₀ +π/3) (α ₀ +π
/2)・1/E The adder 17 adds the signals v ₀ ² and v ₀ ′ ₂ to
We are looking for V ₀ ² . As shown below, V ₀ ² = v ₀ ² + (1/ω d・v ₀ /dt) ² The signal V ₀ ² and the constant A ₀ are input to the adder 18, and the signal A ₀ +A ₁ V ₀ ² and Become. The signal A ₀ +A ₁ V ₀ ² is converted by a converter 19 into a clock signal with a frequency proportional to its value. This clock signal is transmitted to the delay element 11a.
~11c, and the delay elements 11a to 11c are inputted to delay elements 11a to 11c so that the voltages u _a0 to u _c0 are at an angle α equal to the angle Θ.
to drive. Since delay elements 11d to 11f are driven by the same clock signal, delay element 1
Obtain similar results to 1a-11c.

As described above, α=Θ signals w _a1 , w _b1 ,
w _c1 , w _a2 , w _b2 , w _c2 are outputted from multipliers 13a to 13f, and integrators 14a to 14c obtain signals Wa to Wc by calculating the following equations.

W _a =∫ ^t _tg w _a dt=-V ₀・E (t-t _g ) W _b =∫ ^t _tg w _b dt=1/2V・E (t-t _g ) W _c =∫ ^t _tg w _c dt=1/ _2V0・E(t- _tg ) As mentioned above, the signals _wa to _wc are the voltages _ua , _ub ,
It has a value proportional to u _c , and if there is no ground fault and the three phases are balanced, all will be zero. Therefore, the signal
Wa~Wc also becomes zero.

Figure 6 is a waveform diagram of signals Wa to Wc. From time tg when the accident occurred, signal Wa goes in the negative direction.
Wb and Wc increase in the positive direction.

The comparators 15a to 15c compare the signals Wa to Wc, which change as shown in FIG. shows the detection of the accident phase.

The case where the integrators 14a, 14b, and 14c perform complete time integration has been described above, but if there is even a slight DC component due to the calculation accuracy of the multipliers 13a to 13e, this will accumulate. In order to avoid this, it is necessary to set the characteristics of the integrators 14a, 14b, and 14c to integration with an appropriate time constant, that is, the transfer function of the first-order lag element 1/1+ST.

Note that if the time constant T of integration is set large compared to the ground fault to be detected, the above-described function can be maintained as is.

Furthermore, in the above embodiment, the voltages u _a ~ u _c and u _a ′ ~ u _c ′ are used as sine waves, but these are converted into rectangular waves with the same phase and constant amplitude as the sine waves using a waveform converter. However, the same effects as in the above embodiment can be achieved. 7th
The figure shows the waveform of such an embodiment, in which a is a rectangular wave due to voltage u _a , b is a rectangular wave due to voltage u _b ,
c represents voltage v ₀ , d represents voltage v ₀ ', e represents signal w _a1 , f represents signal w _a2 , and g represents signal w _a .

FIG. 8 is a waveform diagram showing a signal Wa obtained by integrating the signal w _a shown in FIG. 7 before and after the time t _g of the occurrence of the accident. Although the illustrated signal Wa has a vibration component unlike that in FIG. 6, it can be compared with a reference voltage for determining a ground fault phase in the same manner as in the above embodiment.

Further, in the above embodiment, the reference voltage is a rectangular wave, but the same effect as in the above embodiment can be obtained even if the zero-phase voltage is shaped into a rectangular wave and inputted to the multiplier.

Additionally, when detecting a ground fault phase by increasing the detection sensitivity of the zero-sequence voltage, saturation may occur in the zero-sequence voltage signal due to the dynamic range constraints of the arithmetic circuit. Since this information is retained, it is possible to detect a ground fault phase.

In the above embodiment, the integrator circuit is provided with an appropriate time constant in order to prevent malfunctions caused by zero-sequence voltages that occur even during normal operation due to slight unbalance in the system or unbalance in the detector. ing. Therefore, in the signals w _a , w _b , w _c caused by the unbalance, DC bases having different values are generated even before a ground fault occurs, which adversely affects ground fault detection using a threshold value. Therefore, as shown in FIG. 9, the output of the integrator (first-order lag element with time constant T) may be passed through the capacitor c. The resistor R placed after the capacitor c is to set the output base to zero at all times, and the value of the time constant CR is determined based on the expected ground fault phenomenon and the constant system disturbance, as well as the integration time constant T. Choose the one that takes into account the degree of Even if the positions of the CR circuit and the integrating circuit are swapped, the effect will be the same.

In the above embodiment, the angles α and Θ are made to match, but the angles α and Θ may be substantially the same.

In the above embodiment, a three-phase phase shift transformer was used to derive the voltages u _a0 to u _c0 and u _a0 ′ to u _c0 ′, but a capacitive voltage divider was used to derive the voltages u a0 to u c0 and u a0 ′ to u c0 ′. It may be derived as follows. The circuit diagrams shown in FIGS. 10 and 11 are for the case where the leading phase α is 30°.

In FIG. 10, the outputs of voltage dividers 5a, 5b, 5c are input to adders 6a, 6b, 6c to obtain voltages U _a0 ,
Derive U _b0 and U _c0 , and further differentiate the differentiators 20a, 20b,
20c to derive voltages U _a0 ′, U _b0 ′, and U _c0 ′.

In FIG. 11, the voltages of adders 6a, 6b, 6c
U _a0 , u _b0 , and u _c0 are input to adders 6d, 6e, and 6f, from which voltages u _a0 ', u _b0 ', and u _c0 ' are obtained.

In the above embodiment, the angles Θ and α are made to match each other, but the same effect can be obtained even if the angles are made to substantially match.

As described above, according to the present invention, the zero-phase voltage signal of the grid is multiplied by the phase-shifted reference voltage signal, further integrated for a predetermined period, and the reference voltage and level are determined. This makes it possible to reduce the influence of noise and has the effect of providing a device that operates stably.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional ground fault phase detection device, Figure 2
The figure is a voltage vector diagram of each phase and zero phase when a ground fault occurs, Figure 3 is a circuit diagram of a ground fault phase detection device according to an embodiment of the present invention, and Figures 4 and 5 are as shown in Figure 3. 6 is a waveform diagram of the operation of the device shown in FIG. 3, and FIGS. 7 and 8 are waveform diagrams of the operation of the ground fault phase detection device according to other embodiments of the present invention. , FIGS. 9 to 11 are circuit diagrams of a ground fault phase detection device according to another embodiment of the present invention. 3a-3b, 5a-5c, 11a-11d, c
...Capacitor, 4...Switch, 6a to 6f,
17, 18... Adder, 9... Transformer, 10...
Voltage divider, 11a to 11f...Delay element, 12, 2
0a-20c...Differentiator, 13a-13f, 16
a, 16b... Multiplier, 14a-14c... Integrator, 15a-15c... Comparator, 19... Converter. In addition, in the figures, the same reference numerals indicate the same parts.

Claims (1)

[Scope of Claims] 1. A circuit that introduces voltages of each phase from an AC system and generates first and second voltage signals that are proportional to the voltage and phase-shifted; a plurality of delay elements that delay a voltage signal in accordance with a clock signal; first and second delay elements that take the product of the voltage signal output from the delay elements and a zero-sequence voltage of the AC system and a differential voltage of the zero-sequence voltage; a first adder for each phase that adds the outputs of each corresponding phase of the first and second multipliers, and each output of this first adder has a preset reference voltage. a comparator that outputs a signal indicating detection of a ground fault phase when the
an arithmetic circuit that squares and adds the zero-sequence voltage and differential voltage to calculate the square value of the amplitude of the zero-sequence voltage; and a converter that converts the frequency of the output of this arithmetic circuit to generate the clock signal. Ground fault phase detection device. 2. Ground fault phase detection according to claim 1, characterized in that the zero-sequence voltage and its differential voltage are supplied to the first and second multipliers, respectively, via a waveform conversion circuit that converts the zero-sequence voltage and its differential voltage into rectangular waves. Device. 3. The earth fault phase detection device according to claim 1 or 2, characterized in that a DC interrupting capacitor is connected in series to the integrator.