JPH02711B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a character pattern generating device that converts the rows and columns of document (text) information and records or displays the same.

[Prior Art] Various devices have been developed and proposed for outputting page information using, for example, electrostatic recording devices or inkjet recording devices using laser beams, optical fibers, etc., CRT display devices, and the like.

This type of device is used, for example, when recording documents.
By sequentially extracting recorded document (text) information line by line, character codes are output continuously for each line in the sweeping direction of a scanning means such as a laser beam, and the necessary character signals are generated accordingly. let me,
It records characters on recording paper.

Therefore, in the conventional recording apparatus, as shown in FIG.
3) The text is recorded line by line in the direction orthogonal to (hereinafter referred to as vertical mode).

However, as shown in FIG.
There are cases where it is necessary to record sentences line by line in parallel with 3 (hereinafter referred to as horizontal mode). The opposite may also be the case.

Conventional recording devices cannot perform such conversion of the arrangement direction of sentences, which is very inconvenient. Furthermore, when one page of recording is finished and the next page of text information is to be recorded, in a recording device that has a storage capacity of only one page, the next page can be started immediately after the previous page has been recorded. It had the disadvantage that pages could not be recorded and continuous high-speed recording could not be performed.

Furthermore, in order to change the arrangement direction of the text with respect to the direction of the recording medium, it is necessary to rotate the character dot pattern obtained from the character generator.

Conventionally, a method of performing matrix calculation using software has been used to rotate this pattern. This method required a lot of processing and did not allow rapid rotation of the dot pattern.

Furthermore, in devices that record or display characters, the dot patterns of characters are often stored in a directional manner (horizontal mode or vertical mode), and recording can be performed in both horizontal and vertical modes. In a character display device, it is necessary to prepare two types of character dot patterns: a character dot pattern for horizontal mode and a character dot pattern for vertical mode. Therefore, the memory capacity is reduced to 2
Therefore, in a system that allows character display in both horizontal and vertical modes, the memory increases and becomes uneconomical.

In addition, in the conventional device that outputs page information, it is not possible to change the font size on a page or line basis, and differences in character output formats, such as differences in the number of characters/line, number of lines/page, or proportion It was not possible to accommodate differences in regional spacing, uniform spacing, etc.

[Object of the present invention] The present invention was made in view of the above circumstances, and an object of the present invention is to provide a character pattern generating device that can easily generate characters of any size.

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 3 is a perspective view showing an outline of a recording apparatus using a laser beam.

In FIG. 3, 301 is a laser oscillator;
2 is a reflecting mirror, 303 is a modulator, 304 is a beam expander, 305 is a rotating polygon mirror, 307 is an f/θ lens, 308 is a photosensitive drum, and 311 is a recording paper.

A laser beam oscillated by a laser oscillator 301 is guided to an input aperture of a modulator 303 via a reflecting mirror 302. The reflecting mirror 302 is inserted to bend the optical path in order to reduce the space of the apparatus, and can be removed if unnecessary.

For the modulator 303, an acousto-optic modulation element using a known acousto-optic effect or an electro-optic element using an electro-optic effect is used.

In the modulator 303, the laser beam is modulated in intensity according to the input signal to the modulator 303.

In addition, when the laser oscillator 301 is a semiconductor laser, a gas laser, etc. that can perform current modulation, or an internally modulated laser that incorporates a modulation element in the oscillation optical path, The modulator 303 is omitted and the beam is guided directly to the beam expander 304.

The beam diameter of the laser beam from the modulator 303 is expanded by a beam expander while remaining a parallel beam. Furthermore, the laser beam whose beam diameter has been expanded is incident on a polyhedral rotating mirror 305 having one or more mirror surfaces. The polyhedral rotating mirror 305 is mounted on a shaft supported by a high-precision bearing (for example, an air bearing) and is driven by a motor 306 that rotates at a constant speed (for example, a hysteresis synchronous motor, a DC servo motor). As a result, the horizontally swept laser beam 312 is imaged as a spot on the photosensitive drum 308 by the imaging lens 307 having f/θ characteristics.
In a general imaging lens, when the incident angle of a ray is θ, the image forming position f on the image plane has the following relationship: γ=f・tanθ−(1) (f: focal length of the imaging lens) As in this embodiment, the incident angle of the laser beam 312 reflected by the fixed polyhedral rotating mirror 305 to the imaging lens 307 changes linearly with time. Therefore, the moving speed of the imaged spot position on the photosensitive drum 308, which is the image surface, changes non-linearly and is not constant. That is, the moving speed increases at the point where the angle of incidence increases. Therefore, when a row of spots is drawn on the photosensitive drum 308 by turning on the laser beam at regular time intervals, the spacing between the spots will be wider at both ends than at the center. To avoid this phenomenon, the imaging lens 307
is designed to have the characteristic γ=f・θ −(2).

Such an imaging lens 7 is called an f/θ lens.

Furthermore, when collimated light is imaged into a spot by an imaging lens, the minimum diameter of the spot dmin is dmin = fλ/A - (3) where f: focal length of the imaging lens λ: wavelength of the light used A : Given by the entrance aperture of the imaging lens, and if f and λ are constant, a smaller spot diameter dmin can be obtained by increasing A. The beam expander 304 mentioned above is used to provide this effect. Therefore, the necessary
If dmin is obtained by the beam diameter of the laser oscillator, the beam expander 304 is omitted. The beam detector 318 includes a small entrance slit and a fast response time photoelectric conversion element (e.g.
PIN diode). Beam detector 318
detects the position of the swept laser beam 312, and uses this detection signal to determine the start timing of the input signal to the modulator 303 for providing desired optical information on the photosensitive drum. As a result, errors in the division accuracy of each reflective surface of the polyhedral rotating mirror 305 and synchronization deviations of horizontal signals due to uneven rotation can be greatly reduced, and a high-quality image can be obtained. The tolerance range of accuracy required for the drive motor 306 is increased, and the drive motor 306 can be manufactured at a lower cost.

As described above, the deflected and modulated laser beam 312 is irradiated onto the photosensitive drum 308, visualized by a known electrophotographic processing process, and then transferred and fixed onto the recording paper 311 and output as a hard copy.

FIG. 4 shows an example of a control block diagram of the laser beam printer of FIG. 3 according to the present invention.

In the figure, 100 is a magnetic tape (MT), 101 is an interface for exchanging information signals with the MT 100, 102 is a first control unit, 1
03 is a data selector that switches data address bus lines, etc.; 104 is a page storage device that stores text information for one page; 105 is a second control unit that converts the contents of the first storage device into columns; and 106 is a data selector. , 107, 107' are first and second column storage devices each having one column of information obtained by column-converting the input text information by the second control unit 105. 108 is a data selector, 109 is a character generator, and this output signal 303S is input to the modulator 303 in FIG. 3, so that character information is formed on the photosensitive drum 308. 318S is the signal from the beam detector.

FIG. 5 shows the input form of character information, and FIG. 6 shows the state in which the text information is recorded on the recording paper. An arrow 11 in FIG. 5 indicates an input direction, and input is made along the direction of the arrow 11. Arrow 12 in FIG. 6 indicates the output direction to the recording medium (main scanning direction), and arrow 13 indicates the moving direction of the recording medium (sub-scanning direction).

Now, when text information is continuously input line by line, the information is received by the interface 101 and supplied to the first control unit 102. In this case, the first control section 102 controls the data selector 103 and directs the page storage device 104 toward the first control section 102 . Then, the supplied text information for each line is sequentially stored in one storage device 104. As a result, one page of text information is stored in the page storage device 104 in a format corresponding to the input format shown in FIG. When all text information for one page is stored in the page storage device 104, the first
The control unit 102 switches the data selector 103 to connect the second control unit 105 and the page storage device 104, and instructs the second control unit 105 to start printing. Then, the photosensitive drum 308 starts rotating, and the photosensitive surface of the photosensitive drum 308 is charged by the charger. In parallel with this, the second control unit 105 performs a column conversion operation (described later) from the text information in the page storage device 104 to perform one column's worth of information ("Kan", "X" in the example of FIGS. 5 and 6). ”, “1”, “A”) are transferred to the first column storage device 107'. In this case, the data selector 106 is connected to the second control unit 105 and the first column storage device 10.
7, the data selector 108 couples the character generator 109 and the second column storage 107'. The character generator 109 inverts the data selectors 108 and 106 in response to the first detection signal from the beam detector 318 in the recording device, so that the character generator 109 and the first column storage device 107 are coupled.
The second control unit 105 and the second column storage device 107' are coupled. Naturally, the first
The column storage device 107 completely stores the information in the first column of text information. At the same time, character generator 1
From 09 onwards, an interrupt is generated in the second control unit 105.

At the same time as these processes, the character generator 109 transfers the last line character (in this example, "Kan") among the characters to be recorded in the first column of the recording paper (text information) from the first column storage device 107. ) and select the corresponding character (“Kan”)
The dot information signal 303S of the first column is output from the character generator 109. This signal 303S modulates the modulator 303 and exposes a latent image corresponding to the dot information in the first column of the last row of characters among the characters to be recorded in the first column of the recording paper (text information). Formed on drum 308. Next, among the characters to be recorded as the first column of text information on the recording paper, the character in the second line from the last line (in this example, “X”)
The first column of dot information is output from the character generator 109, which modulates the modulator 303 to form its latent image on the photosensitive drum. This operation is performed by creating a latent image of each character (“Kan”, “X”, “1”, “A”) to be recorded in the first column of the recording paper (text information) for the dot information in the first column. This process is repeated until all the latent images of the characters in the first column of the recording paper (text information) are completely formed. For example, if the characters are formed by a 16 x 32 dot matrix, regardless of the number of characters in the first column of text information.
Repeated 16 times.

While this scanning is repeated 16 times, the second control unit 105 interrupts to store each character to be recorded in the page storage device 104 as the second column of text information.
The data are sorted while performing a column conversion operation and transferred to the second column storage device 107'. It goes without saying that this operation must be performed reliably during 16 scans. In this way, the character generator 109
When all the character information in the column storage device 107 has been formed as a latent image, that is, when 16 scans have been completed, the data selectors 106 and 108 are inverted again and at the same time an interrupt is generated in the second control section 105.

This time, the character generator 109 and the second column storage device 1
07' is coupled, the second control unit 105 and the first column storage device 107 are coupled, and the above repetition is executed.

As this repetition progresses, 1 in the page storage device 104
The second control unit 105 generates a completion signal to the first control unit 102 at the time when all of the text information for a page has been converted into a latent image.

If copying is required, the first control unit 102 instructs to start printing again and repeats the same process.

FIG. 7 shows another example of the control block diagram.

In FIG. 5, parts having the same functions as those in FIG. 4 are given the same numbers. Reference numerals 203 and 203' designate data selectors for switching bus lines for data addresses, and reference numerals 204 and 204' designate first and second page storage devices that each store one page's worth of text information.

Now, when text information is input consecutively line by line,
The information is received by the interface 101 and provided to the first control unit 102'. At this time, the first control section 102' controls the data selector 203, and the first control section 102' controls the data bus 21 from the first control section 102'.
1 and the data bus 212, and the text information is connected to the first
Written to page storage 204. Meanwhile, at this time, the data selector 203' connects the bus line 214 from the second page storage device 204' and the bus line 216 to the second control section 105'.

The text information on the first page input line by line in this manner is sequentially stored in the first page storage device 204 in a form corresponding to the input format shown in FIG.

All text information for one page is stored in the first page storage device 204
, the first control unit 102' switches the bus line selection of the data selector 203', and the data selector 203' selects the bus lines 215 and 216.
1 stored in the first page storage device 204.
The page information is output to the second control section 105'.
The second control unit 105' executes the column conversion operation described in FIG. On the other hand, the first control section 102' is completely free from the time when the control of the recording device is transferred to the second control section 105' until the recording is completed.
The page storage device 204' is also in an idle state. Therefore, the first control section 102'
3' connects bus lines 215 and 216, and at the same time, data selector 203 connects bus lines 211 and 213. As a result, at the same time as the first page information stored in the first page storage device 204 is output, the first control unit 102' outputs the second page information to the second page storage device 204' via the interface 101. It becomes possible to memorize.

When the reception of the text information of the second page is completed and the recording completion is confirmed from the second control unit 105', the data selectors 203 and 203' are switched again, and the second page memory The device 204' and the first control section 102' are coupled to the first page storage device 204, and a print instruction is issued to the second control section 105', and this operation is repeated.

Since data writing and reading can be performed in parallel in this way, efficient data transfer and continuous recording without waiting time are possible.

The column conversion method performed by the second control units 105, 105' will be described. page storage devices 104, 204,
Text information is input line by line to 204' as described above. Here, it is assumed that a maximum of 132 characters are input per line (this number of characters is _Inax ) and a maximum of 66 lines per page (this number of lines is _Jnax ). Therefore, the format of the input page information is as shown in FIG. 8th
Each block BK in the figure is organized by letter, and the numbers within the block BK indicate the order in which they are input. This input information is stored in page storage devices 104, 204, 204'.
For example, as shown in FIG. 9, the data are stored sequentially from the first row.

To convert this into columns, C _o = (66-V)・132+W ...(1) V: Number of columns after column conversion 1, 2, ..., 66 W: Number of rows after column conversion 1, 2 ,...132 C _o : Numerical numbers 1, 2,... in block BK
8712 In other words, the numerical number C _o in block BK is applied to row W and column V after column conversion. Therefore, first W=1
output by changing V sequentially from 1 to 66,
Next, by setting W=2 and varying V from 1 to 66, output is made.If this is repeated until W=66, the output as shown in FIG. 10 can be obtained. If this is extended to a general formula, C _o =(J _nax −V)·I _nax +W (2) holds true. According to formula (2), W=1 V=1,2,3,..., J _nax W=2 V=1,2,3,..., J _nax 〓 〓 〓 〓 W=I _nax V=1 , 2, 3, ..., J _nax can be output in the order of column conversion.

With such a configuration, the first control section 10
2,102' converts the input code to internal code,
Since information is stored in the page storage units 104, 204, and 204', and the second control unit performs column conversion, an efficient control system can be formed.

For example, if you want to input kanji or special shapes,
If a code system compliant with JIS C6228-1975 ``Extension of Codes for Information Exchange'' is input from the outside, just interpreting its meaning becomes a considerable burden. Furthermore, column conversion operations are performed and the page storage devices 104 and 20
4,204', it takes a considerable amount of time from the start of code input until the print instruction is issued, which reduces the overall efficiency (Through
put) is not desirable. In this embodiment, regardless of whether it is in portrait or landscape mode, the pages are stored in the order of the codes input to the page storage device, so pages can be stored in the minimum amount of time, and when page storage is completed, the print state immediately returns. Column conversion is performed through gaps in the recording system where there is sufficient time, so
Overall efficiency (throughput) is improved. or,
By having a plurality of page storage devices, the reception of the next page's text information is completed before the recording of the previous page is completed, so that the maximum throughput can be obtained.

Note that when column conversion is not required (recording in vertical mode), the second control unit 105, 105' converts the information input row by row into the page storage devices 104, 204, 204' as it is, row by row. column storage device 107,1
Transfer to 07'. That is, column storage devices 107, 10
7' stores information for one line. The vertical and horizontal mode signals are transmitted through the interface 101 and the first control unit 10.
The signal is input from the MT 100 to the second control unit 105, 105' via 2, 102'. Second control unit 10
5, 105' determines whether or not to perform column conversion by determining the vertical and horizontal mode signals.

As described above, it has become possible to change the arrangement direction of sentences with respect to the recording medium or the sub-scanning direction as shown in FIG. However, if the sub-scanning direction 13 is constant, the result will be as shown in FIG. 11 unless the arrangement of the character dot patterns is converted. Although the arrangement shown in FIG. 11 has high utility value as a Japanese or Chinese text, it is difficult to use it as a written text such as English or French text. To prevent this, the array of character dot patterns obtained from the character generator must be rotated by 90 degrees. This rotation of the dot pattern is performed by the character generator 109 shown in FIGS. 4 and 7.

The method of rotating the dot pattern will be explained in detail below.

FIG. 12 shows an example of the dot pattern dividing method according to the present invention, in which the dot pattern of one character is divided into unit matrix groups _AMN of M rows and N columns, and the unit matrices _AMN are further divided as shown in FIG. Divide into elements aij corresponding to each dot. Each element aij of the unit matrix _AMN is arranged sequentially as shown in FIG. 13 and stored in a memory of one word (i.j) bits. For example, if i = j = 4, it may be stored in a memory with 16 bits per word, or if the memory is 8 bits per word, two sets of memory elements may be prepared and these two sets of memory may be accessed simultaneously. Just leave it there. It goes without saying that in the case of a memory with 4 bits per word, 4 sets should be prepared, and in the case of 1 bit per word, 16 sets should be prepared. What is important here is that (i and j) bits can be accessed simultaneously.

If such memory is prepared for (M·N) words, all the dots of the dot pattern can be stored.

When a pattern is generated using a memory in which the dot pattern is divided in this way, A ₁₁ , A ₁₂ ,
The memory is accessed in the order of A ₁₃ ,...A _MN , and the output data, i.e., aij, is as shown in Figure 14.
A normal pattern can be obtained by using a ₁₁ , a ₁₂ , a ₁₃ , a ₁ j, a ₂₁ , . . . , a _{i (j-1)} , a ij as a video signal for a pattern generator in this order.

Also, access the memory A _M1 , A(M-1)
1, ...A ₁₁ , A _M2 , A _(M-1)2 , ..., A _MN , ...A _1N and output data aij as ai ₁ ,
If the sequence a _(i-1)1 , ...a ₂₁ , a ₁₁ , a _i2 , ..., a _2j , a _1j is used as a video signal for a pattern generator, a pattern rotated 90 degrees to the right can be obtained.

Similarly, A _MN , A _M(N-1) , ...A _M2 , A _M1 , ...A _(M-1)2 ,
A _(M-1)1 ...A _1N , A _1(N-1) , ...A ₁₁ are accessed in this order, and data aij is accessed as a video signal in the order of aij, ai _(j-1) , ... ai ₂ , ai ₁ , etc. This will give you a pattern rotated 180 degrees.

In this way, patterns can be easily rotated simply by converting the order of accessing the unit matrices A _MN and the order of reading data aij.

In order to keep the operation speed constant due to the rotation of the pattern, it is desirable that the number of elements of the unit matrix _AMN is a square matrix. That is, i=j
This is preferable because the circuit can be simplified.

Furthermore, considering the development status of computer peripheral elements in recent years, i=j=2l (l=1, 2, . . . ) is advantageous, but this does not essentially limit the scope of the present invention.

In addition, in order to speed up pattern generation, i,
This can be easily achieved by increasing j.

There is no need to impose any restrictions on M and N, which determine the size of the matrix group, but M, N = 2L (L =
1, 2, 3...), it goes without saying that the circuit can be simplified. FIG. 15 is a block diagram of a pattern generator having a memory structure according to the present invention.

400 is an address control circuit, 401 is a dot pattern memory according to the present invention, and 402 is a data selection circuit that selectively outputs output data from the memory and outputs a video signal to the optical modulator 303 in FIG. 3.

Signal 403 that determines the image rotation angle of the input pattern
When the (vertical/horizontal mode signal) is input, the address control circuit 400 determines the address sequence to the memory so that data is output as described above.
Upon receiving the horizontal synchronization signal 318S and vertical synchronization signal 405 from the recording device 300, a necessary address is determined in accordance with these signals, and the contents of the memory 41 corresponding to this address are output to the data selection circuit 402. . In addition, the horizontal synchronization signal 318S
is a signal obtained from the beam detector 318 (Fig. 3) for each scan of the beam, and corresponds to the row clock described later, and the vertical synchronization signal 405 is obtained a certain period of time after the beam detector 318 detects the beam. This clock signal corresponds to the column clock described below. A delay circuit 421 and a clock generator 422 are provided to obtain the column clock.

At the same time, a clock 407 is output from the address control circuit 400 to the data selection circuit. Using this clock and the image rotation control signal 403, the data selection circuit selects the necessary signal from among the data output from the memory 401 and converts the video signal 303 into the video signal 303.
Generate S.

Next, a specific example of the present invention will be described.

Figure 17 shows i=4, j=4, M=4, N=8,
This is an example of a case where the unit matrix memory is composed of two types.

FIG. 16 shows a unit matrix memory corresponding to FIG. 13, and FIG. 17 shows a specific example of a memory matrix group under the above conditions corresponding to FIG. 12.

The unit matrix 112 in the matrix group is the first
6, it is composed of two different types of memories: an 8-bit memory A110 and an 8-bit memory B111.
The △ numbers in the memory indicate the data address address when writing to the memory, and the numbers inside ◯ indicate the data address address when reading. For example, when considering the letter "P" in this memory matrix group, the result is as shown in FIG. 18.

Both A and B memories are 1 cell (1 word)
This is a case where the memory has an 8-bit structure (ROM RAM or any other type of memory is fine. In the case of RAM, characters can be registered using a controller MPU etc. connected to the CG). As shown in FIG. 19, memories A and B store a plurality of a ₁ to a _o and b ₁ to each character unit.
It is composed of b _o , and this character unit a ₁ ~ _{a o}
and b ₁ to b _o are detailed as memory a _x and memory b _x .

These memories a _x and b _x correspond to the memory matrix group (dot pattern) in Fig. 18, and in the case of the letter "P" in Fig. 18, the data in memories a and b are recorded as shown in Fig. 19. ing.

Both memories A and B are 1 cell (1 word)
We used an 8-bit version as an example, but the character generation speed, memory speed, or data writing convenience in the case of RAM (for example, when writing with a CPU, the CPU
This is done by determining the numerical values of (i and j) in the unit matrix mentioned above, taking into account various hardware conditions such as the data parallel processing capacity of the CPU. For this reason, it is set to 8Bit.

In this case, in both memories A and B, 1 cell (1 word) has 8 1-bit cells, 4 2-bit cells,
A similar effect can be obtained by using two 4-bit bits.

Next, the relationship between scanning and the memory described above will be described.

20 and 21 are diagrams showing an example of character output, and the arrows X in display diagrams 20-1 and 21-1
indicates the main scanning direction at the time of output, and arrow Y indicates the sub-scanning direction.

Furthermore, 20-1 shows the display screen for vertical mode output, and 21-1 shows the display screen for horizontal mode output, and the enlarged views of each are shown in 20.
-2, shown in 21-2.

In 20-2, 21-2, l ₀ , l ₁ , l ₂ , l ₃ ... are Y
C ₀ , C ₁ , C ₂ , C ₃ ... indicates the direction scanning line number.
Shows direction clock number. These l ₀ , l ₁ ,
l ₂ , l ₃ ..., C ₀ , C 1 , C ₂ , C ₃ ... are l ₀ , l ₁ , l ₂ , _{l 3 ...} , C ₀ , C ₁ , C ₂ , _C3 ,
It corresponds to...

That is, in this example, if we take only a single character as an example,
In the case of vertical mode, the address address of the unit memory matrix (the number in the circle in Figure 17) is set to 0, 1,
Access in the order of 2, 3, 4, 5, 6...31.

In the case of horizontal mode, 28, 24, 20, ..., 0, 29,
Access in the order of 25, ..., 1, 30, ..., 2, 31, ...3.

Data selection (here, as shown in FIG. 16, the data in the cells of the memory A110 are D _a0 ,
D _a1 ...D _a7 , data in the cells of memory B111
Indicated by D _b0 , D _b1 ,...D _b7 . ) In the case of vertical mode, D _a0 , D _a1 , D _a2 , D _a3 , ...D _a4 , D _a5 , D _a6 ,
D _a7 ,..., D _b0 , D _b1 , D _b2 , D _b3 ,..., D _b4 ,
Perform D _b5 , D _b6 , D _b7 ... in this order.

In addition, in the case of transverse mode, D _b4 , D _b0 , D _a4 , D _a0 , ..., D _b5 , D _b1 , D _a5 ,
D _a1 ,..., D _b6 , D _b2 , D _a6 , D _a2 ,..., D _b7 ,
D _b3 , D _a7 , D _a3 ... are performed in this order.

FIG. 22 shows a more detailed control block diagram of the character generator 109. In this example, RAM is used as the dot pattern memory in order to enable the registration of character dot pattern data by the CPU or the like.

500 is a control circuit for the registration.

501 is for registering character data in RAM.
It is the CPU. This CPU has other Mass Memory
(MT, DISC etc) (not shown).
It has a function of extracting character data from the mass memory and registering it in the dot pattern memories A and B 509 and 510.

502-1 is a data line from the CPU, character data passes through this data line 502-1, further passes through data gate A of 504, data gate B of 505, and output line 508- of data gates 504 and 505. 1,508-2 to dot pattern memories A509 and B510.

The address bus 503-1 for accessing the dot pattern memory from the CPU 501 is applied to the dot pattern memories A 509 and 510 via the bus 507 through the address gate 506. Line 511 is an address line, but the dot pattern memory (hereinafter referred to as character memory) is A50.
The specific bit divided into 9 and B510 is used as a memory select line (hereinafter referred to as MS line) of the character memory.

In the example of FIG. 17, when the least significant bit (LSB) of the address line is "0", character memory A509 is selected, and when it is "1", character memory B510 is selected. It will be done. 512
is an inverter that inverts “0” and “1” of the address line 511.

Reference numerals 513 and 514 are OR circuits, which perform the above-mentioned MS based on the address line 511. In the case of character generation (hereinafter referred to as CG) operation, both memories 5
It is provided for simultaneous access to 09 and 510.

A line 515 is a control line through which a CG operation signal is supplied from the second control section 105 or 105' when the CG is operated. This CG operation signal is applied to data gates A and B 504 and 505 and address gate 506, and prohibits the CPU 501 from coupling the memory for registering dot pattern data with the character memory.

On the other hand, this CG operation signal is
509 and 510 to simultaneously enable both memories.

This CG operation signal is also applied to the address gate 516 to control the character selection signal line 517 and the unit memory matrix selection signal line 518 to be coupled to the character memories A, B 509, 510.

519 is a memory address determining circuit that generates a unit memory matrix in the above-described order. 521 is a line counter through line 520-1, that is, l ₀ in FIGS. 18, 20, and 21,
It is a row counter that counts l ₁ , l ₂ , l ₃ ,...l ₁₅ , etc. This row counter 521 is a 5-bit counter and repeatedly counts from 0 to 31. Also 52
3 is the column counter through line 22, i.e., FIG.
Clocks C ₀ , C ₁ , in FIGS. 20 and 21,
This is a counter that counts C ₂ , C ₃ , etc. This column counter 523 is a 5-bit counter similar to the counter, and repeatedly counts from 0 to 31. These row counters 521 and column counters 523
The row clock, that is, the synchronization signal of the X direction scanning line (3 in FIG. 7 and FIG.
18S) and a column clock, that is, a signal synchronized with the pixel frequency, respectively, to perform counting operations.

The row counter 521 sends a row end signal through a line 526 every time it completes counting 32 items in the vertical mode and every time it completes counting 16 items in the horizontal mode.
Data selector 1 given to control units 105, 105'
Switch between 06 and 108.

In addition, the column counter 523 sends a column end signal to the column storage device 107 or 1 via line 527 every 16 counts in the vertical mode and every 32 counts in the horizontal mode.
Access 07' to switch characters. This is because the character dot pattern of this embodiment is formed with a size of 16×32 in width and height.

The external control circuit knows that it is necessary to switch characters every time it receives a column end or row end signal and sends the address bus 517.
The memory address for character selection is changed and given.

The row counter 521, column counter 523, and address determining circuit 519 receive vertical and horizontal mode signals through a line 528, and perform the various operations described above.

On the other hand, character memories A and B50 in CG operation
9,510 data output bus is 508-1
(8 Bits in parallel), 508-2 (8 Bits in parallel), and is supplied to the digital selector (1) 529 and then to the digital selector (2) 531 through the bus 530. The digit selector (1) 529 selects characters from both A and B character memories.
In the vertical mode, the data (D _a0 , D a1 , D a2 , D _a0 , D a1 , D _a2 , D _a3 ), (D _a4 ,
D _a5 , D _a6 , D _a7 ), (D _b0 , D _b1 , D _b2 , D _b3 ), (D _b4 ,
D _b5 , D _b6 , D _b7 ) of 4 bits each are sequentially selected as one group. Also, when in transverse mode (D _b4 , D _b0 ,
D _a4 , D _a0 ), (D _b5 , D _b1 , D _a5 , D _a1 ), (D _b6 , D _b2 ,
D _a6 , D _a2 ), (D _b7 , D _b3 , D _a7 , D _a3 ), each 4Bit
are sequentially selected as one group. Digit selector (2) 531 receives the signal of the lower two bits of the column counter on line 532, and selects digit selector (1) 52.
Select to sequentially output the 4-bit signal selected in step 9. This selected signal becomes a 1-bit signal synchronized with the column clock from the output line 533 to the recording device 3.
A video signal of 00 is obtained. This signal is also
It can be used for various purposes such as display on a CRT surface, printing using a laser beam, inkjet, or other recording method, or image transmission using a facsimile. In the present invention, a dot pattern is obtained as a time series signal, but by providing a serial input-parallel output shift register, it is possible to obtain a full multi-stylus head and a full multi-ink jet head arranged in a line in the main scanning direction. It is also possible to simultaneously drive the full multi-heads of a recording device having the following.

The above is an outline of one column for rotating a character dot pattern.
This will be explained in further detail based on the figures.

The row counter 521 of this embodiment is a 5-bit binary counter that operates in response to a scanning line synchronization signal. This counter 521 is 0.1.2.3~
31, 0.1.2.3 to 31 and 32 counts are repeated, and this 5-bit output line is connected from the MSB (most significant bit) side.
Let L ₄ , L ₃ , L ₂ , L ₁ , L ₀ .

On the other hand, the column counter 523 is a 5-bit binary counter that operates in synchronization with the pixel clock. This counter is 0.1.2.3.~31, 0.1.2.3.~31
, repeat the count of 32, and convert this 5Bit output line to
Assign C ₄ , C ₃ , C ₂ , C ₁ , and C ₀ from the MSB side.

The address determination circuit 519 accesses the unit matrix memory in the order according to the vertical and horizontal modes of the memory matrix group shown in FIG. 17 by simply selecting the output signals of both counters using the vertical and horizontal mode signals. .

That is, if the outputs of the address determination circuit 519 in FIG. 23 are A ₄ , A ₃ , A ₂ , A ₁ , A ₀ from the MSB side, then in the vertical mode A ₄ = L ₄ , A ₃ = L ₃ , A ₂ = L ₂ , A ₁ =
By determining C ₃ , A ₀ =C ₂ , the data address addresses of the unit matrix 412 for one character can be accessed in the order of 0, 1, 2, 3, . . . , 31.

The entire page is as shown in FIG. 24.
In FIG. 24, C is a column clock, l is a row clock, 0 to 31 are one-character data address addresses, and the numbers inside squares are character numbers.

Also, in the case of transverse mode, A ₄ = ₄ A ₃ = ₃ , A ₂ = ₂
By determining A ₁ = L ₃ A ₀ = L ₂ , the data address address of the unit matrix 412 for one character is set to 28, 24, 20, ..., 0, 29, 25, ...
1, 30, 26, ... 2, 31, 27, ..., 3 can be accessed in this order. The entire page is as shown in FIG. 25.

The address determining circuit 519 is an inverter.
Consisting of I ₁ , I ₂ , I ₃ and switches S ₀ , S ₁ , S ₂ , S ₃ , and S ₄ , in the case of vertical mode, S ₀ to _{S 4} are switched to the A side by the vertical/horizontal mode signal of the vertical/horizontal mode signal line 528. , in the case of transverse mode, by connecting S ₀ to S ₄ to the B side, the above
Signals from A ₀ to _{A 4} are obtained.

Next, the digital selection function will be explained.

The details of the digit selection circuit are shown in FIGS. 26 and 27. From character memory 509,510
16Bit parallel data is on bus 508-1,5
It enters the digit selector (1) 529 through 08-2.
In other words, 16 bits of one unit matrix are accessed simultaneously. Here, line 528, line 520-2
By the vertical and horizontal mode signal, L ₁ of the row direction counter,
In response to L ₀ , internal switch circuits S ₁₀ to _{S 13} are driven by these three control signals to switch 508-1, 50
8-2 data signal is selected. The operations S ₁₀ to S ₁₃ according to this control signal are shown in the truth table of FIG. 27(1). The 4-bit data signal obtained in this way is sent to the second digit selector (2) via the bus 530.
531. The circuit 531 consists of a single switch S ₂₀ which connects input data to line 32.
A specific 1 bit is selected from the lower 2 bit signals C ₁ and C ₀ from the column direction counter input via the column direction counter. The operation of switch S is shown in FIG. 27(2). With this configuration, in the longitudinal mode, D _a0 , D _a1 ..., D _a3 , D _a4 , ..., D _a7 , D _b0 ,
Select D _b1 , ..., D _b7 in this order.

Also, in the case of transverse mode, D _b4 , D _b0 ,
Digits are selected in the order of D _a4 , D _a0 , D _b5 , D _b1 , D _a5 , ..., D _a7 , D _a3 .

As described above, it is possible to read characters in both the vertical mode and the horizontal mode shown in FIGS. 20 and 21 from the same memory.

The rotation operation of the dot pattern has been described above.

[Second Embodiment] Next, another embodiment of the present invention having a function of rotating a character pattern when converting rows and columns of a character pattern of an arbitrary size will be described.

For the memory matrix group in Figure 17, we have explained the case where the number of dots for one character (horizontal x vertical) is 16 x 32 to simplify the explanation, but this is not fixed, and If the numbers M and N in the column direction can be changed, the present invention can be applied to character patterns of arbitrary sizes.

22 using the memory matrix group of FIG. 17
In the circuit shown in the figure, in the vertical mode, the column counter 523 counts 16 column clocks and outputs a column end signal from the line 527 since N=4 (4×N).

Also, since the row counter 521 is 4×M and M=8,
Count 32 row clocks and send the row end signal to line 526.
It was outputting more.

In order to explain the second embodiment of the present invention, a description will be given based on the memory matrix group of FIG. 28, which is obtained by expanding the memory matrix group of FIG. 17 twice in the column direction.

In Figure 28, if N = 4 and M = 8 are set, frame F1 will be selected, and the number of dots of the character designed in frame F1 will be 16 x 32, and the same characters as in Figure 17 will be output. , N=8, M=8, the frame F2 is selected, the number of dots of the character designed in the frame F2 becomes 32×32, and a character with a size of 32×32 is output.

Furthermore, if you select frame F3, the number of dots will be 24 x 24, and if you select frame F4, the number of dots will be 20 x 28.
Characters of each size are output.

Therefore, by arbitrarily selecting the numerical values M and N, any matrix group in the matrix group can be set to the frame F.
You can select from frames 1 to F4 or other frames.

FIG. 29 shows a control block diagram of a character generator having a function of setting numerical values M and N. Components in FIG. 29 having the same functions as those in FIG. 22 are given the same reference numerals.

A constant circuit 541 that outputs a numerical value M is provided for the row counter 521, and a constant circuit 541 that outputs a numerical value M is provided for the column counter 523.
A constant circuit 540 that outputs a numerical value N is provided. Among the outputs L ₀ to _{L 4} of the row counter 521, L ₂ , L ₃ , L ₄
is output to the comparison circuit 537 via the bus 535. Comparison circuit 537 outputs a line end signal from line 526 when the output of constant circuit 541 and the output of line counter 521 match, and obtains a signal for selecting a character on the next line.

Similarly, among the outputs C ₀ to C ₄ of the column counter 523 , C ₄ , C ₃ , and C ₂ are output to the comparison circuit 536 via the bus 534 . Comparison circuit 536 outputs a column end signal on line 527' when the output of constant circuit 540 matches the output of column counter 523, and obtains a signal for selecting a character in the next column.

A bus 544 is a data bus from second control units 105, 105' (FIGS. 4 and 7) for providing constants M and N, and 542 and 543 are timing signal lines for selecting circuits 540 and 541.

In this way, by setting numerical values from the second control section 105, 105', it becomes possible to select any matrix group among the matrix groups as shown in FIG. 28, and based on the command from the second control section, Outputs characters of any size.

In addition, to specify the font size, if a size index is given to the constant circuits 540 and 541 for each page, the font size can be changed on a page-by-page basis, and if a size index is given to each line, the font size can be changed on a line-by-line basis. I can,
If a size index is given to each character, it is possible to change the size of each character.

[Effect of the invention] With the above configuration, differences in character output formats currently used in each field, such as the number of characters/
Differences in lines, number of lines/pages, proportional spacing, uniform spacing, etc. can be adequately dealt with by changing the number of dots for each page or character, and the flexibility of the character output format is enhanced. It increases dramatically.

Although this embodiment has been specifically described above, the value of ij may also be a value other than the value of the present invention.

Even if the addresses shown in FIG. 17 of the unit memory matrix are addressed from completely different directions, the details of the specific explanation may change, but the gist remains the same.

In the above description, the unit matrix is accessed simultaneously at the same address, but other methods may be used in which a plurality of data in the unit matrix can be handled as data at the same address. For example, by further subdividing the 16-Bit data of a unit matrix into 4-Bit units, and accessing these 4-Bit units at a speed faster than the required unit matrix cycle time, for example, 4 times faster, 16-Bit reading can be completed every unit matrix cycle time. It does not matter if there is a time-sharing method.

In this example, an electrophotographic recording device using a laser beam was used as an output device, but an electrophotographic device using an OFT (optical fiber tube) or a needle electrode instead of a laser beam, or an inkjet recording device may also be used. , CRT (cathode ray tube), and other output methods.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of longitudinal mode recording, Fig. 2 is a diagram showing an example of transverse mode recording, Fig. 3 is a perspective view of a recording device using a laser beam, and Fig. 4 is a diagram showing an example of transverse mode recording.
The first control block diagram of the recording device shown in FIG. 5 is a diagram showing the input format of text information, FIG. FIG. 8 is a second control block diagram of the recording device of FIG.
~Figure 10 is a diagram for explaining the column conversion method, Figure 11
The figure shows an example of recording when the dot pattern of characters is not rotated, Figures 12 and 13 are diagrams showing the method of dividing the dot pattern, and Figure 14 is a diagram showing the reading order in portrait mode. Fig. 15 is a control block diagram, Fig. 16 is a diagram showing unit matrix memory, Fig. 17 is a diagram showing a memory matrix group, and Fig. 18 is a case in which the letter "P" is inserted into the matrix group of Fig. 17. Figure 1 shows the memory contents of
9 is a diagram showing the contents of memories A and B corresponding to FIG. 18, FIGS. 20 and 21 are diagrams showing an example of character output, and FIG. 22 is a control block of the character generator of the first embodiment. 23 is a diagram of the address determination circuit and its peripheral circuits, FIG. 24 is a diagram showing the selection order of unit matrices in vertical mode, and FIG. 25 is a diagram showing the selection order of unit matrices in horizontal mode. , FIG. 26 is a diagram of the digital selection circuit and its peripheral circuits,
Figures 27 1 and 2 are diagrams showing truth values for digit selection, Figure 28 is a diagram showing a memory matrix group for explaining the second embodiment, and Figure 29 is a diagram showing character generation according to the second embodiment. FIG. 3 is a control block diagram of the device. In the figure, 412 is a unit matrix memory;
509 and 510 are character memories, 540 and 541 are constant circuits, 536 and 537 are comparison circuits, 521 is a row counter, 523 is a column counter, 519 is an address determining circuit, and 529 and 531 are digit selectors, respectively.

Claims (1)

[Scope of Claims] 1. As a character pattern in which one character is expressed by M×N units (M and N are positive integers) of a unit matrix consisting of a plurality of dot data, character patterns of multiple sizes M and N are different. A storage means for storing, and character patterns M and N stored in the storage means.
an address specifying means for counting and reading out the address for each unit matrix; a size setting means for setting the size of the character pattern to be read by setting M and N; and a numeral means for setting M and N, and the addressing means counts the unit matrix of the character pattern up to M and N set in the numeral means and outputs a character pattern of a set size. A character pattern generating device characterized in that reading is performed from the storage means.