JPH027209B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse output device, and particularly to a pulse output device that can increase the variation range of output amplitude and offset voltage even in a high frequency region.

[Conventional technology] In recent years, the amount of data information in PCM (pulse code modulation) communication has been reduced to G (giga) bits, logic integrated circuits using GaAs, and ultra-high-speed reading and writing are possible.
Research and development of RAM (random access memory), etc. is progressing. There is a need for a device that outputs a test signal in the form of a pulse wave in order to test the operation of semiconductor devices or devices that operate digitally at such high speeds.

Of course, the frequency and data type of this test signal can be changed in various ways, and in order to check the input amplitude and threshold voltage margin of a semiconductor device as a test object or a device incorporating these, It is essential that the pulse amplitude and offset voltage of the test signal can be varied arbitrarily.

Conventionally, as a pulse output device that outputs such a pulse signal for testing, as shown in Fig. 2,
A differential logic circuit 2 in which the emitters (sources in the case of FETs) of a pair of transistors 1a and 1b are connected to each other and performs switching operation in a non-saturation region is widely used.

That is, the emitters of a pair of transistors 1a and 1b constituting this differential logic circuit 2 are commonly connected to a constant current circuit 3, and the collectors of each transistor are connected via load resistors 4a and 4b, respectively, to an offset control circuit. 5. Further, the bases of the transistors 1a and 1b are connected to input terminals 6a and 6b to which pulse signals having different polarities are inputted, as shown in the figure, and the transistors 1b
The collector of is connected to the output terminal 7 from which the output pulse signal is taken out. Further, the base of a current limiting transistor 3a constituting the constant current circuit 3 is connected to an input terminal 8 to which an amplitude control signal for controlling the amplitude of the output pulse signal is input. Furthermore, the input terminal of the differential amplifier 5a constituting the offset control circuit 5 is connected via a resistor 5b to an input terminal 9 of an offset control signal for controlling the offset voltage of the output pulse signal.

In the pulse output device configured in this manner, the amplitude of the output pulse signal output from the output terminal 7 is determined by the emitter current determined by the constant current circuit 3 controlled by the amplitude control signal input from the input terminal 8. Value I _E and load resistance 4b of transistor 1b
and the resistance value R ₄ (I _E R ₄ ). Therefore,
By changing the amplitude control signal, it is possible to obtain a desired amplitude value.

Further, the offset control circuit 5 outputs an offset voltage corresponding to the offset control signal inputted from the input terminal 9, and applies it to the load resistors 4a and 4b, so that the offset voltage of the output pulse signal outputted from the output terminal 7 is , a value proportional to the offset control signal. Therefore, it is possible to obtain a desired offset voltage by changing the offset control output signal.

However, the pulse output device constituted by the differential logic circuit 2 shown in FIG. 2 has the following problems. In other words, when increasing only the amplitude while keeping the offset voltage of the output pulse signal constant, the amplitude control signal is increased and the constant current circuit 3
Therefore, it is necessary to increase the emitter current value I _E , but as the emitter current value I _E increases, the collector-emitter voltage V _CE (in the case of FETs, the drain-source voltage V _DS ) becomes low. In general, the transition frequency f _T , which indicates the gain and phase characteristics of a transistor in a high frequency region, decreases as the collector-emitter voltage V _CE decreases. As a result, when the amplitude of the output pulse signal is increased, the rise/fall time of the pulse waveform becomes longer, causing a problem that the waveform characteristics deteriorate.

Also, when changing the offset voltage while keeping the amplitude of the output pulse signal constant,
The change in offset voltage means that transistor 1
The collector-emitter voltage _VCE of a and 1b will change. Therefore, when the offset voltage is high, the collector-emitter voltage V _CE increases, which increases the aforementioned transition frequency f _T and shortens the rise/fall times of the output pulse signal waveform, but conversely causes ringing. This phenomenon becomes more likely to occur, and the overall pulse waveform becomes disordered. Conversely, when the offset voltage is low, the collector-emitter voltage V _CE decreases, so ringing does not decrease, but there is a problem that the rise/fall time becomes longer.

When the amplitude or offset voltage of the output pulse signal is changed in this way, the transistors 1a and 1b
Since the transition frequency f _T of the output pulse signal changes, it has the disadvantage that it cannot be used in a high frequency region where rise time/fall time and ringing phenomena cause problems with the pulse period of the output pulse signal.

Furthermore, when using GaAsFETs as transistors 1a and 1b constituting a differential logic circuit,
Since the rated voltage between the drain and source of the FET is lower than the rated voltage between the collector and emitter of a general silicon transistor, there is also the problem that the variable range of the offset voltage in the output pulse signal cannot be widened.

In order to solve this problem, a pulse output device shown in FIG. 3 has been proposed. That is, the collector of the transistor 11b of the differential logic circuit 12 is connected to the input terminal of the variable attenuator 14.
The output terminal of this variable attenuator 14 is a capacitor 15
Output terminal 16 for outputting an output pulse signal via
and the differential amplifier 18 of the offset control circuit 18 via the inductance 17a.
It is connected to the (-) side input terminal of a. The (+) side input terminal of this differential amplifier 18a is connected to an input terminal 19 to which an offset control signal is input. Furthermore, the output terminal of this offset control circuit 18 is connected to the output terminal 16 via an inductance 17b.

Furthermore, the emitters of each of the transistors 11a and 11b of the differential logic circuit 12 are commonly connected to a constant current circuit 13.

In such a pulse output device, the output of the constant current circuit 13 is adjusted to fix the amplitude of the output pulse signal output from the differential logic circuit 12 to a maximum value. After the amplitude is attenuated by the variable attenuator 14, the AC component of the attenuated output pulse signal is led to the output terminal 16 via the capacitor 15, and the DC component is sent to the offset control circuit via the inductance 17a. 18. and,
This DC component is superimposed on the offset control signal inputted from the input terminal 19 in the offset control circuit 18, and outputted, and sent to the output terminal 16 via the inductance 17b. Therefore, output terminal 1
6, a final output pulse signal is output in which the AC component input via the capacitor 15 is superimposed on the DC offset voltage input from the offset control circuit 18 via the inductance 17b. Therefore, by adjusting the degree of attenuation of the variable attenuator 14, the amplitude of the output pulse signal output from the output terminal 16 can be varied, and by adjusting the offset control signal input to the input terminal 19, the amplitude of the output pulse signal can be varied. It is possible to vary the offset voltage of the output pulse signal.

Moreover, since the waveform, amplitude, and offset voltage of the pulse signal output from the differential logic circuit 12 are always constant, the amplitude of the circuit after the variable attenuator 14,
As long as the transmission characteristics such as phase maintain substantially flat frequency characteristics, the aforementioned characteristics such as rise/fall time are not affected by amplitude changes and offset voltage changes of the output pulse signal.

[Problems to be Solved by the Invention] However, even in the pulse output device configured as shown in FIG. 3, the following problems still need to be solved. In other words, the variable attenuator 14 for attenuating the output pulse output from the differential logic circuit 12 has a structure that changes the degree of attenuation in stages in consideration of frequency characteristics, etc., so the degree of attenuation can be changed continuously. It was difficult to make changes. The above problem can be solved by setting a large number of attenuation change steps, but this time, variable attenuator 1
4 equipment costs will rise.

Furthermore, the inductance 17a for separating the DC component of the pulse signal output from the variable attenuator 14 and the inductance 17b for combining the output signal of the offset control circuit 18 into the AC component have a limit on the low-pass frequency; Since the signal containing frequency components cannot be completely transmitted, the output terminal 16
There is a concern that sag may occur in the output pulse signal waveform.

The present invention has been made based on the above circumstances, and its purpose is to reduce the amplitude and offset voltage of the output pulse signal over a wide frequency band from direct current to high frequency range, thereby deteriorating the pulse waveform. The object of the present invention is to provide a pulse output device that can be varied to a large extent without any problems.

[Means for Solving the Problems] The present invention varies the offset voltage of a pulse signal output from a differential logic circuit using an externally inputted offset control signal, and also varies the offset voltage of a pulse signal output from an externally inputted amplitude control signal. In the pulse output device which is configured to vary the amplitude of the pulse signal, the pulse signal is output in response to an externally input pulse signal, and the amplitude of the output pulse signal is controlled by the amplitude control signal. a separation circuit that separates the output pulse signal of the pulse output circuit into an AC signal and a DC signal; a DC signal from the separation circuit, an inverted signal of the amplitude control signal, and the offset control signal. A bias control circuit that adds and outputs the sum is provided, and the bias control signal output from the bias control circuit and the AC signal from the separation circuit are superimposed and input to the differential logic circuit.

[Operation] With the pulse output device configured in this way, the pulse signal output from the pulse output circuit is separated into an AC signal and a DC signal by the separation circuit.
Then, the bias control circuit adds the offset control signal and the inverted amplitude control signal to the DC signal to obtain a bias control signal, which is superimposed on the separated AC signal and input to the differential logic circuit. . Therefore, when the value of the amplitude control signal is changed, the current source control circuits of both the differential logic circuit and the pulse output circuit operate in the same direction, and the bias control signal of the bias control circuit operates in the opposite direction. As a result, the amplitude of the pulse signal input to this differential logic circuit and the DC bias voltage change simultaneously, making it possible to continuously vary the amplitude of the output pulse signal and to always operate the differential logic circuit under optimal conditions. It is.

Furthermore, since the offset control signal is input to the offset control circuit and also to the bias control circuit, when the offset control signal changes, the bias control signal also changes in the same direction. However, even if the amplitude of the output pulse signal is kept constant and only the offset voltage is changed, the relative potential difference between the gate and drain of the FET in a differential logic circuit will not change. It is possible to operate with

Even if the amplitude and offset voltage of the output pulse signal are changed in this way, the pulse waveform is not adversely affected.

[Example] An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a pulse output device according to an embodiment. This pulse output device is roughly divided into a pulse output circuit 21 that outputs a pulse signal in response to a pulse signal input from the outside, a current source control circuit 22 that controls the current source of this pulse output circuit 21, and a pulse output circuit 21 that outputs a pulse signal in response to a pulse signal input from the outside. A separation circuit 23 that separates a pair of pulse signals output from the output circuit 21 into a DC signal and an AC signal, a bias control circuit 24 to which each DC signal separated by this separation circuit 23 is input, and this bias A differential logic circuit 25 into which each bias control signal outputted from the control circuit 24 is superimposed on each AC signal outputted from the separation circuit 23 and outputs an output pulse signal, and this differential logic circuit 25, and an offset control circuit 27 that applies an offset voltage to the differential logic circuit 25.

In the pulse output circuit 21, a pair of
The sources of the FETs 21a and 21b are connected to each other and to the collector of a current control transistor 22a of the current source control circuit 22. Further, the drains of the FETs 21a and 21b are grounded via load resistors 21c and 21d, respectively. The gates of the FETs 21a and 21b are connected to input terminals 28a and 28b to which input pulses having substantially the same threshold voltage and amplitude and different polarities are input. And each
The pulse signal output from each drain of FET21a, 21b is connected to each capacitor 23 of separation circuit 23.
a, 23b, and each resistor 23c,
23d, the signal is inputted to DC component detection circuits 29a and 29b each consisting of an integrating circuit. Each of these DC component detection circuits 29a and 29b integrates the input pulse signal waveform at a certain period and extracts a DC signal of this pulse signal waveform.The DC output is determined by the mark rate, duty factor, and signal level of this pulse signal waveform. The signal level changes.

Each DC signal output from each DC component detection circuit 29a, 29b is input to each analog adder 30a having four input terminals in the bias control circuit 24,
It is input to the first input terminal of 30b. The fixed bias voltage output from the fixed bias voltage generation circuit 31 is input to the second input terminal of each adder 30a, 30b, and the third input terminal of each adder 30a, 30b
The amplitude control signal inputted from the input terminal 32 is inverted in polarity by an analog inverting circuit 33 and inputted as an inverted signal to the input terminal of the input terminal 32 . Furthermore, the offset control signal input from the input terminal 34 is input to the fourth input terminal of each adder 30a, 30b.

Signals inputted from the four input terminals of each adder 30a, 30b are added and output as each bias control signal, and each FET 25a, 25 forming the differential logic circuit 25 via resistors 24a, 24b.
b is applied to each gate. Note that each capacitor 2 is connected to each gate from a separation circuit 23.
Each AC signal of each pulse signal outputted via 3a and 23b is also applied in a superimposed manner.

An offset control circuit 27 comprising a differential amplifier 27a, a current booster 27b, etc. is connected to each drain of each FET 25a, 25b of the differential logic circuit 25.
The offset voltage output from each resistor 2
5c and 25d. Also,
The drain of the FET 25b is connected to an output terminal 35 for outputting an output pulse signal of this device.

Further, the sources of the FETs 25a and 25b are commonly connected to the collector of a current limiting transistor 26a in the current source control circuit 26. The emitter of this transistor 26a is resistor 2
It is connected to the DC power supply (-V _E ) via 6b. The base of the transistor 26a is connected to two Zener diodes 26c and 26d of polarity shown in the figure.
The output terminal of the differential amplifier 26e is connected to the output terminal of the differential amplifier 26e. The (+) side input terminal of the differential amplifier 26e is connected to the amplitude control signal input terminal 32 via a resistor 26f, and to the (-V _E ) DC power supply via a resistor 26j. The (-) side input terminal is connected to the midpoint between dividing resistors 26g and 26h inserted between the emitter of transistor 26a and ground.

Further, the midpoint between the pair of Zener diodes 26c and 26d connected in series is connected to the pulse output circuit 21.
The transistor 22 in the current source control circuit 22 of
connected to the base of a.

Further, the input terminal 34 to which the offset control signal is input is connected to each adder 30 of the bias control circuit 24.
a, 30b, and the differential amplifier 27 of the offset control circuit 27 via a resistor 27c.
It is connected to the (+) side input terminal of a.

In the pulse output device configured in this way, the amplitude of the output pulse signal output from the differential logic circuit 25 via the output terminal 35 is
2 is the product of the source current IS determined by the current source control circuit 26 controlled by the amplitude control signal _input from input terminal 32
By changing the amplitude control signal input to the output pulse signal, the amplitude of the output pulse signal can be changed. Furthermore, when the level of the offset control signal inputted from the input terminal 34 is changed, the offset voltage outputted from the offset control circuit 27 is applied to the resistors 25c and 25d connected to the respective drains of the FETs 25a and 25b of the differential logic circuit 25. As a result, the offset voltage of the output pulse signal changes.

Here, the amplitude control signal inputted from the input terminal 32 is inputted to the current source control circuit 26 of the differential logic circuit 25, and is inverted by the inverting circuit 33 to each adder 30a, 30b of the bias control circuit 24.
is input. Therefore, each FET25a, 2
The gate voltage of 5b changes in the opposite direction to the changing direction of the amplitude control signal. As a result, by changing the amplitude control signal at the input terminal 32 while keeping the offset voltage of the output pulse signal constant, only the amplitude can be changed to, for example, V ₁ .
to V ₂ (V ₁ <V ₂ ), FET25a,
The gate voltage of 25b operates to be a voltage lower by (V ₁ −V ₂ ) than the voltage when the amplitude is V ₁ . In other words, the drain-gate voltage V D is increased for a large amplitude of the output pulse signal, and conversely, the drain-gate voltage V _D is increased for a small amplitude of the output pulse signal.
The gate voltage changes to reduce the gate-to-gate voltage _VDG . Therefore, FET25a, 25b
The change in the drain-source voltage V _DS when conductive is reduced, and the change in the gain and phase characteristics (transition frequency f _T ) in the high frequency region is also reduced. As a result, even if the amplitude of the output pulse signal changes significantly, there is little disturbance in the waveform of the output pulse signal.

On the other hand, the offset control signal inputted from the input terminal 34 is inputted to the offset control circuit 27 as well as to each adder 30 of the bias control circuit 24.
Since it is input to FETs 25a and 30b, when the offset voltage is changed while keeping the amplitude of the output pulse signal constant, the gate voltage of each FET 25a and 25b changes in the circumferential direction in synchronization with the change in the offset voltage. Therefore, each FET 25 of the differential logic circuit 25
The drain-to-gate voltage V _D of transistors a and 25b remains approximately constant regardless of changes in the offset voltage of the output pulse signal. Therefore, FET25a, 25
Since the gain and phase characteristics (transition frequency f _T ) in the high frequency region of b do not change,
The rise/fall times of the output pulse signal waveform do not change. As a result, even if the amplitude is changed, the output pulse signal waveform will not be disturbed.

In this way, the bias control circuit 24 tracks the level fluctuation of the DC signal of the pulse signal inputted from the pulse output circuit 21, and the differential logic circuit 24
The differential logic circuit 2 always responds to changes in the offset voltage and amplitude of the output pulse signal output from the differential logic circuit 2.
5 to maintain optimal bias conditions for each FET.
It has a function of supplying gate voltage to 25a and 25b.

Further, the AC signal from the separation circuit 23 and the DC bias control signal from the bias control circuit 24, which are input to the differential logic circuit 25, are combined without using an inductance, and the bias control circuit 25
Since the output impedance of each adder 30a, 30b of 4 is set to a very high value, each gate circuit of each FET 25a, 25b of the differential logic circuit 25 operates in a wide range from direct current to a high frequency region.

Generally, in order to obtain a large amplitude output pulse signal from the differential logic circuit 25, each FET 2 must be
The amplitude of the pulse signal input to each gate 5a and 25b needs to be large. The amplitude control signal input from the input terminal 32 is sent to the current source control circuit 26.
The amplitude of the pulse signal output from the pulse output circuit 21 is divided by the Zener diodes 26c and 26d and applied to the base of the current control transistor 22a of the current source control circuit 22 of the pulse output circuit 21. can be controlled by the amplitude control signal, so the above conditions can be easily satisfied. Moreover, since the rate of change is lower than the rate of change of the output pulse signal of the differential logic circuit 25,
Changes in the waveform of the pulse signal output from the pulse output circuit 21, such as rise/fall, duty factor, ringing, etc., caused by changes in the transition frequency _fT can be suppressed to a minimum.

Note that although the present invention provides the DC component detection circuits 29a and 29b consisting of an integrating circuit in order to detect the DC component of the pulse signal output from the pulse output circuit 21, When the mark rate and duty factor are constant, the DC signal of the pulse signal output from the pulse output circuit 21 is a constant value, so by using the fixed bias voltage generation circuit 31, the DC component is It is also possible to eliminate the detection circuits 29a, 29b.

[Effects of the Invention] As explained above, according to the pulse output device of the present invention, the amplitude and offset voltage of the output pulse signal can be significantly increased over a wide frequency band from direct current to high frequency range without deteriorating the pulse waveform. It can be changed to

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a pulse output device according to an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing conventional pulse output devices, respectively. 21...Pulse output circuit, 21a, 21b, 2
5a, 25b...FET, 22, 26...Current source control circuit, 23...Separation circuit, 23a, 23b...
... Capacitor, 24 ... Bias control circuit, 25
... Differential logic circuit, 27 ... Offset control circuit, 29a, 29b ... DC component detection circuit, 30
a, 30b...adder, 31...fixed bias voltage generation circuit, 33...inverting circuit.

Claims (1)

[Scope of Claims] 1. A differential logic circuit 25; an offset control circuit 27 that variably controls the offset voltage of a pulse signal output from the differential logic circuit in response to an offset control signal input from the outside; and a current source control circuit 26 that variably controls the amplitude of the pulse signal output from the differential logic circuit by controlling the current source of the differential logic circuit in response to an amplitude control signal input from the differential logic circuit. , in a pulse output device that outputs a pulse signal input to the differential logic circuit with a desired offset voltage and amplitude: outputs a pulse signal in response to a pulse signal input from the outside, and adjusts the amplitude of the output pulse signal. is controlled by the amplitude control signal; a separation circuit 23 that separates the output pulse signal of the pulse output circuit into an AC signal and a DC signal; the DC signal from the separation circuit and the DC signal; a bias control circuit 24 that adds and outputs an inverted signal of the amplitude control signal and the offset control signal; A pulse output device characterized in that the pulse output device is configured to input the pulse to the differential logic circuit.