JPH027263B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current compensation type power harmonic suppression device.

This type of harmonic suppression device is connected in parallel to the load as seen from the power supply, and performs current compensation to eliminate harmonic components from the power supply current by supplying or absorbing a complementary current to the harmonic current contained in the load current. give Conventionally, control for harmonic suppression involves feedback control in the direction of zeroing out the harmonic current included in the detected power supply current. In this case, if the closed-loop gain of the suppression device is made infinite, harmonic current compensation can be achieved completely, but due to constraints such as the compensation current capacity of the device and safety control, the gain is practically designed to be low. For this reason, in the conventional device, the harmonic suppression effect may not be enhanced depending on the load, and depending on the load, the harmonic component included in the compensation current may increase the harmonic current of the power supply.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a device that improves the harmonic current suppression effect by adjusting the phase of the compensation current based on the impedance of the power source and the load.

The figure is a configuration diagram showing an embodiment of the present invention. When power is supplied from the power supply 1 to the load 2, the harmonic suppression device 3 supplies a current i _a that compensates for the harmonic current included in the load current i _L , thereby eliminating harmonic components from the power supply current i _S. A compensating harmonic suppression device is constructed.

The harmonic suppression device 3 uses a DC reactor 4 as a current source to perform pulse width modulation (PWM) control on an inverter main circuit 5 that bridge-connects GTO thyristors using a gate circuit 6, and passes a harmonic component compensation current i _{a through a carrier removal filter 7.} supply. The control signal for this current i _a is passed through a band pass filter 9 of the power supply current i _S detected by a current transformer 8, and the current
A comparator 11 extracts the harmonic current component contained _in
A comparison is made with a carrier wave (triangular wave) generator 12 to obtain a PWM wave signal, which is then used as a control input to the gate circuit 6.

Note that the control system includes a control loop that keeps the DC current of the DC reactor 4 constant. This is a DC current obtained by detecting the deviation between the DC reactor current detected by the current transformer 13 and the setting value of the DC current setting device 14, and multiplying this deviation signal and the voltage detected by the transformer 15 by the multiplier 16. Add the control signal e _d to the harmonic control signal.

Here, the present invention enhances the harmonic suppression effect by adjusting the phase of the control signal in the phase adjustment circuit 10. This will be explained in detail below.

In the figure, when the power source 1 has an internal impedance Z _S and generates a harmonic voltage e _S , and the load 2 has a load impedance Z _L and generates a harmonic current i _H , the power source current i _S and the load Current i _L , harmonic compensation current i _a
The following relationships hold between the current i _Z of the load impedance Z _L and the current and voltage obtained by Laplace transform.

I _S +I _A −I _L =0 I _L −I _Z −I _H =0 Z _S I _S +E _a =E _S I _A =KI _S Z _L I _Z =E _a ...(1) This equation (1) The power supply current I _S is calculated from I _S =E _S +Z _L I _H /MZ _L +Z _S (2). However, M=1+K. In this equation (2), since the power supply current I _SS when the harmonic suppressor 3 is not operated is K=0, the following relationship is obtained.

I _SS =E _S +Z _L I _H /Z _L +Z _S ...(3) Therefore, the power supply current ratio A when operating and stopping the harmonic suppressor 3 is obtained from equations (2) and (3). A=I _S /I _SS =Z _L +Z _S /MZ _L +Z _S ...(4). As is clear from this relationship, the smaller the power supply current ratio A, the higher the harmonic suppression _{effect .
K} (= | K
It is sufficient to determine the phase of |e ^j 〓 ^k ).

That is, the phase of K that maximizes the denominator of equation (4) can be found by the following procedure.

The value δ of the denominator in equation (4) can be rearranged as shown in equation (5) below.

δ=M+Z _S /Z _L =M+Z=1+｜K｜e ^j 〓 ^k +｜Z｜e ^j
〓 ^z = 1 + | K | cosθ _K + | Z | cosθ _z + j (1K) sinθ _K
+|Z|sinθ _z )...(5) The square of the absolute value of this value δ is given by the following equation (6).

｜δ｜ ² =｜K｜ ² +｜Z｜ ² +1+2｜K｜｜Z｜cos(
θ _K −θ _Z ) +2｜K｜cosθ _K +2｜Z｜cosθ _Z ...(6) |K|, θ _K so that this |δ| ² has the maximum value
The harmonic suppression effect can be maximized by determining the value of |K|, which can be achieved by setting |K| to infinity, but this value is limited in order to stabilize the operation of the device. Therefore, θ _K that maximizes |δ| ² is determined by keeping the value of |K| constant at the maximum allowable value. This includes |δ
From the above equation (6) by partial differentiation of | ² , ∂|δ| ² /∂θ _K = −2|K|Z|sin
(θ _K −θ _Z )−2|K|sinθ _K (7), and the pole at which this value becomes zero can be found from the following equation (8).

｜Z｜sin(θ _K −θ _Z )+sinθ _K =0……(8) That is, the phase θ _K of K is θ _K =tan ^-1 |Z｜sinθ _Z /1+｜Z｜cosθ _Z = tan ^-1
｜Z _S ｜ /｜Z _L ｜sin(θ _S −θ _L )/1+｜Z _S ｜/｜Z _L ｜c
Setting os(θ _S −θ _L )...(9) increases the harmonic suppression effect.

The above θ _K is determined by Z (=Z _S /Z _L ), that is, the source impedance Z _S and the load impedance Z _L , and cos θ _Z ＞−1/|Z| ...(10) cos θ _Z ＜−1/|Z | ...(11) determines that cosθ _K >0 and cosθ _K <0.

That is, from the upwardly convex condition in which the second derivative of |δ| ² in equation (6) is negative, the following equation (12) becomes the condition, ∂ ² |δ| ² /∂θK ² =−2|K| ｜Z｜cos(θ _K −θ _Z
)−2｜K｜COSθ _K <0 (｜Z｜cosθ _Z +1)cosθ _K +｜Z｜sinθ _Z sinθ _K ＞
0...(12) If cosθ _K is 0, equation (12) becomes the following equation (13), |Z|cos ² +1+2|Z|cos ² θ _Z /1+|Z|cosθ _Z
0……(13) (｜Z｜＋cosθ _Z ) ² +1−cos ² θ _Z /1+｜Z｜co
If sθ _Z 0 cosθ _Z −1/|Z|, cosθ _K >0 holds true. Similarly, if cosθ _K <0, then from the following equation (14) |Z| ² +1+2|Z|cos ² θ _Z /1+|Z|cosθ _Z
<0...(14) cosθ _K <0 holds true when cosθ _Z <−1/|Z|.

Therefore, in the phase adjustment circuit 10 shown in the figure, the ratio of the source impedance Z _SN and the load impedance Z _LN to the N-th harmonic for N-th harmonic control is Z _N =Z _SN /
The N-th harmonic suppression effect is maximized by adjusting the phase θ _K determined by equation (9) according to Z _LN . Note that the bandpass filter 9 sets a passband for the Nth harmonic component, and to suppress each harmonic except the fundamental wave, the bandpass filter 9 and the phase adjustment circuit 10 are adapted to each harmonic. The control signal is the sum of The phase adjustment angle θ _K in these is cosθ _Z |
Since cosθ _K 0 in Z _LN |/|Z _SN |, −π/
2<θ _K <π/2, and cosθ _Z <|Z _LN |/|
In Z _SN |, π/2<θ _K <3π/2. Further, similar control can be performed not only by detecting the power supply current i _S but also by detecting the load current i _L.

As described above, according to the present invention, it is possible to maximize the suppression effect in supplying compensation current for stable harmonic suppression.

[Brief explanation of drawings]

The drawing is a circuit diagram showing an embodiment of the present invention. 1...Power source, 2...Load, 3...Harmonic suppressor, 4...DC reactor, 5...Inverter main circuit, 6...Gate circuit, 7...Carrier removal filter, 9...Band pass filter , 10... Phase adjustment circuit, 11... Comparator, 12... Carrier wave generator, 14... DC current setting device, 16... Multiplier.

Claims (1)

[Scope of Claims] 1. A harmonic suppression device that is connected in parallel to a load when viewed from a power supply and suppresses the generation of harmonic current in the power supply current by supplying or absorbing a complementary current to the harmonic current generated in the load, Detects harmonic components from the power supply current and calculates the power supply impedance in this detection signal.
For Z _S and load impedance Z _L , the detection signal is θ _K = tan ^-1 ｜Z _S ｜/｜Z _L ｜sinθ(θ _S −θ _L )
A harmonic suppression device characterized in that the phase is adjusted by θ _K obtained by /1+|Z _S |/|Z _L | cos(θ _S −θ _L ) to obtain a control signal for a harmonic compensation current.