JPH027550B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is used for vertical synchronization of television equipment, and uses a frequency divider circuit to create a frequency-divided output with a vertical period from a frequency that is an even multiple of the horizontal frequency. On the other hand, the vertical synchronization signal obtained by integrating the synchronization separation output signal is related to the vertical synchronization circuit of the type used for phase adjustment of this frequency dividing circuit.

Configuration of Conventional Example and Its Problems FIG. 1 shows a conventional vertical synchronization circuit, and FIG. 2 shows waveforms of each part thereof. In FIG. 1, reference numeral 1 denotes a synchronization separation circuit of a television receiver, the output of which is differentiated by circuit 2 to obtain a horizontal synchronization signal, which is applied to a phase detector 4. A comparison signal obtained from the horizontal flyback transformer 3 is also added to the detector 4. A detector 4 detects the phase difference between the two signals from circuits 2 and 3, and a filter 5 converts the phase difference into DC voltage, which is applied to an oscillator 6. The oscillator 6 is
Set the frequency to 31.5KHz, which is twice the horizontal frequency. The signal is applied to the horizontal deflection circuit 8 after being converted to a horizontal frequency through one-stage flip-flop circuits 7 before and after the horizontal deflection circuit 8. 9 is a frequency divider circuit with a 10-stage flip-flop configuration, which divides the oscillator 6's 31.5KHz frequency by 1/
Divide the frequency by 525 and take out the divided output with a vertical frequency of 60Hz. The frequency-divided output of 9 is applied to the vertical deflection circuit 10.

The frequency divider circuit 9 simply extracts a divided output of 60 Hz from a frequency twice the horizontal frequency, and has no relation to the phase of the vertical synchronizing signal. Therefore, a circuit is required to adjust the frequency-divided output phase to the phase of the vertical synchronization signal. The circuit portion in FIG. 1 is a phase matching circuit for frequency-divided output, which will be explained next.

The circuit constituted by transistors 14 and 15 is a NOR circuit, and the output of frequency divider circuit 9 is applied as an input to inverter 30, the polarity is changed, and the waveform shown in FIG. 2a is applied to the base of transistor 15. On the other hand, at the base of the transistor 14, the synchronized separated output 1 of the receiver is integrated by the circuit 12, and this is applied to the amplifier 13, and the output is applied to the inverter 29 to convert the polarity, so that a signal as shown in Fig. 2b is generated. Add waveform. In FIG. 2, portions A and G correspond to the case where the frequency-divided output and the vertical synchronization signal are in phase. In this case the second
The waveform shown in Figure C appears at the collectors of transistors 14 and 15. This output is the transistor 17,
In addition to one gate input of the NOR gate 18, the other gate input receives the output of the inverter 30, that is, the signal shown in FIG. 2a. Therefore, in the case of the same phase, the collector output of the transistor 18 is 0. This output is connected to capacitors 20, 23,
It is composed of transistors 24 and 25 through an integrator composed of a resistor 21 and a diode 22.
is applied to one gate input of the NAND gate, and the output of amplifier 13, ie, the output of FIG. 2f, is applied to the other gate. In the case of the same phase, the transistor 24
Since the input of is 0, the output inverted by the collector of 24, ie, transistor 27, is 0. Therefore, in this case, since the input to the circuit 11 for resetting the 10-stage flip-flop 9 is 0, the circuit 11 does not operate.

Next, as in the case of Fig. 2B, when the phases of the frequency-divided output and the vertical synchronization signal are different, the transistor
The outputs of the NOR gates 4 and 15 are 0, and a pulse of the opposite polarity from the inverter 30 appears at the collector of the transistor 18. This pulse causes capacitor 2
3 is charged and the base of transistor 24 is
When the m level in Figure e is reached, transistor 24 is turned on, and transistor 25 is connected to its collector.
The input of the base of the transistor 27, that is, the vertical synchronization signal, appears, and the positive pulse shown in FIG. 2g appears at the collector of the transistor 27. This output is the reset circuit 11
, the phase of the frequency-divided output of the 10-stage flip-flop 9 can be matched to the phase of the output pulse of the collector of the transistor 27. Thereafter, the phase of the frequency-divided output always matches the phase of the vertical synchronizing signal until the phase of the vertical synchronizing signal changes, such as when switching channels.

However, as shown in FIGS. 2E and 2F, the vertical synchronization signal may be disturbed by noise or the like.
When the vertical synchronizing signal does not go below the l level shown in FIG. 2b due to noise, a positive pulse appears at the collector of transistor 18, and the noise component added to transistor 25 appears at the collector of transistor 24, and this noise As a result, the frequency-divided output phase of the flip-flop 9 is disturbed.

As described above, in the conventional circuit, all the vertical synchronization signals are used for phase comparison, so the frequency-divided output phase is disturbed by noise.

Purpose of the Invention The present invention solves such conventional disadvantages, and the vertical deflection is less disturbed by noise, especially when used under weak electric field conditions or under noisy conditions such as in automobiles. It is an object of the present invention to provide a vertical synchronization circuit that can perform stable vertical deflection operation even when the vertical deflection operation is stable.

Structure of the Invention In the present invention, a signal with a frequency that is an even multiple of the horizontal frequency is divided to create a signal with a vertical frequency for vertical deflection, and the phase difference between the divided output and the received vertical synchronization signal is detected. A gate circuit that matches the phase of the divided output with the phase of the vertical synchronization signal when the two phases are different, and conducts the vertical synchronization signal only for a certain period of time to the circuit for detecting the phase difference. The characteristic is that the noise signal is supplied through the phase detection circuit, thereby reducing the chances of a noise signal being added to the phase detection circuit and reducing its adverse effects.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention is shown in FIG. 3, and will be described with reference to the waveform diagrams shown in FIGS. 4 and 2.

In FIG. 3, the parts with the same reference numerals as those in FIG. 1 are the same, so a description of these parts will be omitted. In the figure, the present invention differs from the conventional one in that a gate circuit 42 is provided for an oscillator 40 and a transistor 41 controlled by its output, and a vertical synchronization signal is supplied to a phase detection circuit via this gate circuit 42. The oscillator 40 is an unstable multivibrator type oscillator, and the output of this oscillator 40 is as shown in FIG.
As shown in the figure, the level is low for a period of approximately 50 msec over multiple vertical periods (approximately 3 vertical periods in this example).
This is a low-frequency oscillation waveform that remains at a high level for a period of about 0.5 to 1.0 seconds.

This output i is added to the base of the transistor 41, and its collector is connected to the output terminal of the inverter 29. Therefore, the received vertical synchronizing signal h is gated by the gate circuit 42 by this output i, and the fourth
As shown in Figure J, the waveform remains as it is for a certain period of 50 msec and is applied to the base of the transistor 14 of the phase detection circuit, and during the other 0.5 to 1.0 seconds it is cut off and remains at a low level. , the vertical synchronizing signal is not applied to the base of transistor 14 and remains at a low level. Therefore, this 0.5~
During the period of 1.0 seconds, as is clear from the fact that the level in FIG. Therefore, during this period, even if noise or the like is mixed into the vertical synchronization signal i, the vertical synchronization will not be disturbed. Also, during a period of about 50 msec, the transistor 41
is in a non-conducting state, the vertical synchronizing signal is applied to the base of the transistor 14 as in the conventional case, and if the vertical synchronizing signal and the frequency-divided output are not in phase due to channel switching etc. Can be matched.

The time setting of 50 msec was determined in order to apply about three vertical synchronizing signals to the transistor 14 during that period; if it is too short, the phase detection sensitivity will decrease, and if it is too long, the noise characteristics will deteriorate. Also, if the so-called dead time setting of 0.5 to 1.0 seconds is too short, the effect of noise characteristics will be reduced.
If it is too long, it will take time for the phases to match when switching channels, etc., and the phenomenon will be that vertical blanking will be visible on the cathode ray tube screen.

This circuit is used not only in general home TVs that frequently change channels, but also in car TVs used in buses, etc., which are used under noisy conditions. This has a great effect when used in a way that tends to be unstable. Also, when used in this way, channels are not changed frequently, so even if blanking appears on the screen for 0.5 to 1 second. Not many problems occur. Also, if you are using this for purposes other than automobiles, and you have not experienced ever-changing noise or input electric field strength, turn on the switch 43 installed between the base of the transistor 41 and ground in Figure 3. If you do this, you can operate as before.

Effects of the Invention As described above, according to the present invention, the period during which the received vertical synchronization signal is applied to the phase detection circuit in the frequency dividing rectangular vertical deflection circuit is limited. It is possible to realize a useful vertical synchronization circuit in which the vertical deflection is less likely to be disturbed even when the vertical deflection is downward.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional vertical synchronization circuit, Figure 2 is a waveform diagram for explaining its operation, and Figure 3 is a circuit diagram of a conventional vertical synchronization circuit.
The figure is a circuit diagram of a vertical synchronization circuit in one embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining its operation. DESCRIPTION OF SYMBOLS 1... Synchronization separation circuit, 6... Oscillator, 9... Frequency division circuit, 10... Vertical deflection circuit, 11... Reset circuit,
14, 15, 17, 18, 24, 25, 27...transistor, 40...oscillator, 41...transistor, 42...gate circuit.

Claims (1)

[Claims] 1 A signal with a frequency that is an even multiple of the horizontal frequency obtained from the television reception signal is divided by a frequency dividing circuit to create a frequency divided signal with a vertical period and applied to the vertical deflection circuit. A phase detection circuit is provided to detect the phase difference between the frequency-divided signal of the output of the circuit and the received vertical synchronization signal, and conducts the received vertical synchronization signal only during a first period spanning a plurality of vertical periods, and The frequency-divided signal is applied to the phase detection circuit through a gate circuit that repeats a periodic gate operation so as to be cut off during a second period that is sufficiently longer than the first period, and the frequency-divided signal is applied to the phase detection circuit by the output of the phase detection circuit. A vertical synchronization circuit, characterized in that the frequency dividing circuit is controlled to match the phase of the vertical synchronization signal with the phase of the vertical synchronization signal.