Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH02792B2 - - Google Patents
[go: Go Back, main page]

JPH02792B2 - - Google Patents

Info

Publication number
JPH02792B2
JPH02792B2 JP57116379A JP11637982A JPH02792B2 JP H02792 B2 JPH02792 B2 JP H02792B2 JP 57116379 A JP57116379 A JP 57116379A JP 11637982 A JP11637982 A JP 11637982A JP H02792 B2 JPH02792 B2 JP H02792B2
Authority
JP
Japan
Prior art keywords
circuit
frequency
emphasis circuit
signal
emphasis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57116379A
Other languages
Japanese (ja)
Other versions
JPS598107A (en
Inventor
Yutaka Ichii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP57116379A priority Critical patent/JPS598107A/en
Publication of JPS598107A publication Critical patent/JPS598107A/en
Publication of JPH02792B2 publication Critical patent/JPH02792B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/24Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing noise

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Noise Elimination (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Picture Signal Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Description

【発明の詳細な説明】 本発明はノイズリダクシヨン回路に係り、デイ
エンフアシス回路及びプリエンフアシス回路の周
波数特性を特定周波数帯域のみ他の帯域に比して
レベル減衰量及びレベル増強量を大に設定し、特
定周波数でリミツタレベルを越える大振幅のノイ
ズを確実に抑圧し得るノイズリダクシヨン回路を
提供することを目的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise reduction circuit, in which the frequency characteristics of a de-emphasis circuit and a pre-emphasis circuit are set such that the amount of level attenuation and the amount of level enhancement are large in a specific frequency band compared to other bands, It is an object of the present invention to provide a noise reduction circuit that can reliably suppress large amplitude noise exceeding a limiter level at a specific frequency.

第1図は一般の家庭用VTRの記録系及び再生
系のブロツク系統図を示す。同図において、記録
に際し、入力端子1に入来した映像信号は分離回
路2において輝度信号及び色度信号に分離され、
輝度信号はプリエンフアシス回路3にて高域増強
された後FM変調器4にてFM変調されて混合器
5に供給される一方、色度信号はカラープロセス
回路6にて信号処理されて混合器5に供給されて
輝度信号と混合され、記録アンプ7を介してビデ
オヘツド8に供給されてこれにて磁気テープ9に
記録される。
FIG. 1 shows a block diagram of the recording system and playback system of a general home VTR. In the figure, during recording, a video signal input to input terminal 1 is separated into a luminance signal and a chromaticity signal in a separation circuit 2,
The luminance signal is high-frequency enhanced in the pre-emphasis circuit 3, then FM modulated in the FM modulator 4 and supplied to the mixer 5, while the chromaticity signal is processed in the color processing circuit 6 and sent to the mixer 5. The signal is mixed with a luminance signal, and is supplied to a video head 8 via a recording amplifier 7, where it is recorded on a magnetic tape 9.

一方、再生に際し、ビデオヘツド8にて再生さ
れた信号は再生プリアンプ10を介して分離回路
11に供給され、ここで輝度信号及び色度信号に
分離され、色度信号は再生カラープロセス回路1
2にて信号処理されて混合器13に供給される一
方、輝度信号はノイズリダクシヨン回路14に供
給されてここでノイズ成分を抑圧された後、デイ
エンフアシス回路15にて高域減衰されて混合器
13に供給されて色度信号と混合され、出力端子
16より取出される。
On the other hand, during reproduction, the signal reproduced by the video head 8 is supplied to the separation circuit 11 via the reproduction preamplifier 10, where it is separated into a luminance signal and a chromaticity signal, and the chromaticity signal is transmitted to the reproduction color processing circuit 11.
2, the luminance signal is processed and supplied to the mixer 13, while the luminance signal is supplied to the noise reduction circuit 14, where noise components are suppressed, and then high-frequency attenuated in the de-emphasis circuit 15, and then sent to the mixer 13. 13, mixed with the chromaticity signal, and taken out from the output terminal 16.

ここで、ノイズリダクシヨン回路14の動作に
ついて考えてみる。分離回路11からの再生輝度
信号はドロツプアウト補償回路17及び1H遅延
回路18にてドロツプアウト補償された後FM復
調器19においてFM復調され、低域フイルタ2
0にて不要周波数成分を除去されて引算器21に
供給される一方、1H遅延回路18において1H遅
延された信号はFM復調器22にてFM復調され
た後低域フイルタ23にて不要周波数成分を除去
されて引算器21に供給される。引算器21にお
いて低域フイルタ20の出力信号から低域フイル
タ23の出力信号が引算され、再生輝度信号に含
まれるノイズ成分が取出される。
Now, let us consider the operation of the noise reduction circuit 14. The reproduced luminance signal from the separation circuit 11 is subjected to dropout compensation in a dropout compensation circuit 17 and a 1H delay circuit 18, then FM demodulated in an FM demodulator 19, and then passed through a low-pass filter 2.
0, unnecessary frequency components are removed and the signal is supplied to the subtracter 21, while the signal delayed by 1H in the 1H delay circuit 18 is FM demodulated in the FM demodulator 22, and then unnecessary frequency components are removed in the low-pass filter 23. The components are removed and supplied to the subtracter 21. In the subtracter 21, the output signal of the low-pass filter 23 is subtracted from the output signal of the low-pass filter 20, and the noise component contained in the reproduced luminance signal is extracted.

引算器21から取出されたノイズ成分はデイエ
ンフアシス回路24にて高域減衰された後リミツ
タ25にてあるレベルを以て振幅制限され、プリ
エンフアシス回路26にて高域増強された後アツ
テネータ27にそのレベルを1/2に減衰されて混
合器28に供給される。混合器28において低域
フイルタ20の出力からアツテネータ27の出力
信号が引算され、ノイズ成分を抑圧された再生輝
度信号が取出される。このとき、従来のデイエン
フアシス回路24の周波数対レベル特性は第2図
に破線で示す如く直線的である一方、プリエンフ
アシス回路26の周波数対レベル特性も第3図に
示す如く直線的である。
The noise component taken out from the subtracter 21 is attenuated in the high frequency range by a de-emphasis circuit 24, then limited in amplitude to a certain level by a limiter 25, amplified in the high frequency range by a pre-emphasis circuit 26, and then sent to an attenuator 27 to increase its amplitude. It is attenuated to 1/2 and supplied to the mixer 28. In the mixer 28, the output signal of the attenuator 27 is subtracted from the output of the low-pass filter 20, and a reproduced luminance signal with noise components suppressed is extracted. At this time, the frequency versus level characteristic of the conventional de-emphasis circuit 24 is linear as shown by the broken line in FIG. 2, while the frequency versus level characteristic of the pre-emphasis circuit 26 is also linear as shown in FIG.

ところで、家庭用VTR等におけるクロストー
ク成分の周波数は復調後で例えば1.3MHz付近で
あり、良質の画像を得るにはこのクロストーク成
分を抑圧しなければならない。
By the way, the frequency of crosstalk components in home VTRs and the like is, for example, around 1.3MHz after demodulation, and in order to obtain a high quality image, this crosstalk component must be suppressed.

然るに、上記従来回路ではこのクロストーク成
分の周波数に対しては何ら考慮されておらず、こ
のため、クロストークによるビートの振幅がリミ
ツタ25のリミツタレベル以上の場合にはこれを
十分に抑圧できず、画面にちらつきを生じ、良質
の画面を得ることができない欠点があつた。
However, in the conventional circuit described above, no consideration is given to the frequency of this crosstalk component, and therefore, if the amplitude of the beat due to crosstalk exceeds the limiter level of the limiter 25, it cannot be suppressed sufficiently. The disadvantage was that the screen flickered, making it impossible to obtain a high-quality screen.

そこで上記欠点を除去するための従来回路とし
て、第4図に示す如く、リミツタ25に並列に上
記クロストーク成分を通過する高域フイルタ29
を接続すると共に、リミツタ25の出力と高域フ
イルタ29の出力とを混合する混合器30を接続
した回路がある。このものによれば、大振幅のク
ロストーク成分を抑圧できるが、第1図示の回路
に更に高域フイルタ29及び混合器30を追加す
る必要があるために回路が多くなる欠点があつ
た。
Therefore, as a conventional circuit for eliminating the above-mentioned drawback, as shown in FIG.
There is a circuit in which a mixer 30 for mixing the output of the limiter 25 and the output of the high-pass filter 29 is connected. According to this method, large-amplitude crosstalk components can be suppressed, but it has the disadvantage that the number of circuits increases because it is necessary to further add a high-pass filter 29 and a mixer 30 to the circuit shown in the first diagram.

本発明は上記欠点を除去したものであり、以
下、図面と共にその一実施例について説明する。
The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described below with reference to the drawings.

本発明になるノイズリダクシヨン回路は、第1
図中、デイエンフアシス回路31の周波数対レベ
ル特性が第2図に実線で示す如く1.3MHz付近の
み特に大きく減衰するように設定されている一
方、プリエンフアシス回路32の周波数対レベル
特性が第3図に実線で示す如く1.3MHz付近のみ
を特に大きく増強するように設定されている。
The noise reduction circuit according to the present invention has a first
In the figure, the frequency versus level characteristic of the de-emphasis circuit 31 is set to be particularly greatly attenuated only around 1.3MHz, as shown by the solid line in Fig. 2, while the frequency versus level characteristic of the pre-emphasis circuit 32 is shown by the solid line in Fig. 3. As shown in , it is set to particularly greatly enhance only the frequency around 1.3MHz.

ここで、引算器21より取出されたノイズ成分
の周波数が1.3MHz付近以外であれば、デイエン
フアシス回路31において第1図示の従来回路と
同様の特性を以てレベル減衰され、リミツタ25
にて振幅制限された後にプリエンフアシス回路3
2において第1図示の従来回路と同様の特性を以
てレベル増強されてアツテネータ27に供給され
る。
Here, if the frequency of the noise component extracted from the subtracter 21 is other than around 1.3MHz, the level is attenuated in the de-emphasis circuit 31 with the same characteristics as the conventional circuit shown in FIG.
After the amplitude is limited by the pre-emphasis circuit 3
2, the signal is level-enhanced with characteristics similar to those of the conventional circuit shown in FIG. 1, and is supplied to the attenuator 27.

一方、引算器21より取出されたノイズが
1.3MHz付近の上記チヤンネル間クロストークで
あれば、デイエンフアシス回路31において第2
図示の実線の特性を以て特に大きく減衰され、リ
ミツタ25に供給される。この際、デイエンフア
シス回路31の周波数対レベル特性は上記のよう
に設定されているので、クロストーク成分の振幅
が大きくてもリミツタ25にて振幅制限を受ける
ことのないレベルにまで減衰され、リミツタ25
を確実に通過し得る。
On the other hand, the noise extracted from the subtractor 21 is
If the crosstalk between channels is around 1.3MHz, the de-emphasis circuit 31
The signal is particularly greatly attenuated with the characteristics indicated by the solid line shown in the figure, and is supplied to the limiter 25. At this time, since the frequency versus level characteristic of the de-emphasis circuit 31 is set as described above, even if the amplitude of the crosstalk component is large, it is attenuated to a level that is not subject to amplitude limitation by the limiter 25.
can definitely pass.

リミツタ25を通過したクロストーク成分はプ
リエンフアシス回路32に供給され、ここで、第
3図示の実線の特性を以て特に大きく増強されて
元のレベルに戻され、アツテネータ27に供給さ
れる。
The crosstalk component that has passed through the limiter 25 is supplied to a pre-emphasis circuit 32, where it is particularly greatly amplified with the characteristics shown by the solid line shown in FIG.

その他の構成及び動作は第1図示の従来回路と
同様であるので、その説明を省略する。
Other configurations and operations are the same as those of the conventional circuit shown in FIG. 1, so their explanations will be omitted.

なお、デイエンフアシス回路31及びプリエン
フアシス回路32において特にレベル減衰及び増
強する周波数は上記実施例の如きチヤンネル間ク
ロストークの周波数に限定されることはなく、例
えばモアレを生じる周波数等に設定してもよく、
上記と同様の効果を得ることができる。
Note that the frequency at which the level is particularly attenuated and enhanced in the de-emphasis circuit 31 and the pre-emphasis circuit 32 is not limited to the frequency of inter-channel crosstalk as in the above embodiment, and may be set to a frequency that causes moiré, for example.
The same effect as above can be obtained.

又、本実施例による回路は家庭用VTRにおい
て再生系のみに適用されるものであるため、この
回路に設けられていないVTRで記録した信号を
も何ら問題なく再生でき、互換上の問題を生じる
ことはない。
Furthermore, since the circuit according to this embodiment is applied only to the playback system of a home VTR, it is possible to play back signals recorded on a VTR not equipped with this circuit without any problems, causing compatibility problems. Never.

上述の如く、本発明になるノイズリダクシヨン
回路は、デイエンフアシス回路の周波数特性を、
特定周波数帯域のみ他の周波数帯域におけるレベ
ル減衰量に比して大きく設定する一方、プリエン
フアシス回路の周波数特性を、この特定周波数帯
域のみ他の周波数帯域におけるレベル増強量に比
して大きく設定したため、リミツタにおけるリミ
ツタレベルよりも大振幅の特定周波数のノイズが
入来した際、これをデイエンフアシス回路で減衰
してリミツタを通過せしめ得、これにより、デイ
エンフアシス回路及びプリエンフアシス回路の周
波数特性が直線的に設定されていた従来回路に比
して大振幅のノイズを確実に抑圧でき、しかも、
従来回路に比して新たに追加される回路がないの
で回路を簡単に構成し得、更に、抑圧したい信号
の特定周波数を適宜選択し得る等の特長を有す
る。
As mentioned above, the noise reduction circuit according to the present invention improves the frequency characteristics of the de-emphasis circuit by
The level attenuation in a specific frequency band is set to be larger than the amount of level attenuation in other frequency bands, and the frequency characteristics of the pre-emphasis circuit are set to be larger in this specific frequency band than the amount of level enhancement in other frequency bands. When noise of a specific frequency with an amplitude larger than the limiter level comes in, it can be attenuated by the de-emphasis circuit and passed through the limiter, thereby setting the frequency characteristics of the de-emphasis circuit and the pre-emphasis circuit linearly. It can reliably suppress large amplitude noise compared to conventional circuits, and
Compared to conventional circuits, there is no newly added circuit, so the circuit can be configured easily, and furthermore, it has the advantage of being able to appropriately select a specific frequency of a signal to be suppressed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は一般の家庭用VTRのブロツク系統図、
第2図は従来回路及び本発明回路におけるデイエ
ンフアシス回路の周波数対レベル特性図、第3図
は従来回路及び本発明回路におけるプリエンフア
シス回路の周波数対レベル特性図、第4図は従来
回路の要部のブロツク系統図である。 11……輝度信号、色度信号分離回路、13…
…加算器、14……ノイズリダクシヨン回路、1
6……出力端子、18……1H遅延回路、21,
28……引算器、25……リミツタ、27……ア
ツテネータ、31……デイエンフアシス回路、3
2……プリエンフアシス回路。
Figure 1 is a block diagram of a general home VTR.
Fig. 2 is a frequency versus level characteristic diagram of the de-emphasis circuit in the conventional circuit and the circuit of the present invention, Fig. 3 is a frequency versus level characteristic diagram of the pre-emphasis circuit in the conventional circuit and the circuit of the present invention, and Fig. 4 is a diagram of the main parts of the conventional circuit. It is a block system diagram. 11... Luminance signal, chromaticity signal separation circuit, 13...
... Adder, 14 ... Noise reduction circuit, 1
6...Output terminal, 18...1H delay circuit, 21,
28...Subtractor, 25...Limiter, 27...Attenuator, 31...De-emphasis circuit, 3
2...Pre-emphasis circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 入力情報信号に含まれるノイズ成分と見なさ
れる信号をデイエンフアシス回路及びリミツタを
介して取出し、該リミツタの出力をプリエンフア
シス回路を介した後該入力情報信号から引算して
取出すノイズリダクシヨン回路において、該デイ
エンフアシス回路の周波数特性を、特定周波数帯
域のみ他の周波数帯域におけるレベル減衰量に比
して大きく設定する一方、該プリエンフアシス回
路の周波数特性を、該特定周波数帯域のみ他の周
波数帯域におけるレベル増強量に比して大きく設
定したことを特徴とするノイズリダクシヨン回
路。
1. A noise reduction circuit that extracts a signal considered to be a noise component contained in an input information signal through a de-emphasis circuit and a limiter, and subtracts and extracts the output of the limiter from the input information signal after passing through a pre-emphasis circuit, The frequency characteristics of the de-emphasis circuit are set to be larger in a specific frequency band than the level attenuation in other frequency bands, while the frequency characteristics of the pre-emphasis circuit are set to be larger than the level attenuation in other frequency bands only in the specific frequency band. A noise reduction circuit characterized by being set larger than that of the noise reduction circuit.
JP57116379A 1982-07-05 1982-07-05 Noise reduction circuit Granted JPS598107A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57116379A JPS598107A (en) 1982-07-05 1982-07-05 Noise reduction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57116379A JPS598107A (en) 1982-07-05 1982-07-05 Noise reduction circuit

Publications (2)

Publication Number Publication Date
JPS598107A JPS598107A (en) 1984-01-17
JPH02792B2 true JPH02792B2 (en) 1990-01-09

Family

ID=14685537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57116379A Granted JPS598107A (en) 1982-07-05 1982-07-05 Noise reduction circuit

Country Status (1)

Country Link
JP (1) JPS598107A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6219859U (en) * 1985-07-17 1987-02-05
JPS6219858U (en) * 1985-07-17 1987-02-05
JPS63159976U (en) * 1987-04-07 1988-10-19

Also Published As

Publication number Publication date
JPS598107A (en) 1984-01-17

Similar Documents

Publication Publication Date Title
US4698696A (en) Noise reduction circuit for video tape recording and playback apparatus
JPH02156785A (en) Signal transmitter
US5079633A (en) Video signal processor for removing high frequency noise component
JPH02792B2 (en)
GB2099658A (en) Video signal processing circuit for a PAL VTR system
KR0186151B1 (en) Double deck video cassette tape recorder with video signal processing circuit
JPS61292494A (en) Magnetic recording and reproducing device
JP3030925B2 (en) Magnetic recording / reproducing device
JP2722447B2 (en) Magnetic recording / reproducing device
JP2535231Y2 (en) Broadband noise reduction circuit
JPH0413790Y2 (en)
JPH0117636B2 (en)
JPH0233434Y2 (en)
KR100194931B1 (en) Simple Digital Camcorder
JPH04286288A (en) Brightness signal recording circuit holding compatibility at the time of reproduction between different video system and its method
JPH0356915Y2 (en)
EP0289272B1 (en) Method and apparatus for demultiplexing a colour video signal
JPH0627023Y2 (en) Noise reduction circuit
KR0118646Y1 (en) Color signal processing circuit for a vcr
JPH0419757B2 (en)
JPH0318397B2 (en)
JPH0123993B2 (en)
JPS61212984A (en) Magnetic recording device
JPS63266983A (en) Video signal processing device
JPH0783495B2 (en) Chroma signal recorder