JPH028328B2 - - Google Patents
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- Publication number
- JPH028328B2 JPH028328B2 JP58059585A JP5958583A JPH028328B2 JP H028328 B2 JPH028328 B2 JP H028328B2 JP 58059585 A JP58059585 A JP 58059585A JP 5958583 A JP5958583 A JP 5958583A JP H028328 B2 JPH028328 B2 JP H028328B2
- Authority
- JP
- Japan
- Prior art keywords
- carry
- final
- bits
- partial product
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
Description
〔発明の属する技術分野〕
本発明は、データ処理装置におけるパイプライ
ン化乗算回路に関する。
〔従来技術の説明〕
従来、この種のパイプライン化された浮動小数
点乗算回路は、第１図に示すように、被乗数の仮
数部を格納する被乗数レジスタ１、乗数の仮数部
を格納する乗数レジスタ２、被乗数と乗数とを入
力し被乗数の倍数を作成する部分積群作成回路
３、該部分積群作成回路３の出力を加算し最終和
および最終桁上げを出力する多入力桁上げ保存加
算器４、該最終和および最終桁上げを格納する最
終和レジスタ５と最終桁上げレジスタ６、該最終
和レジスタ５と最終桁上げレジスタ６の２入力を
加算する桁上げ先見加算器７、演算結果レジスタ
８、制御回路９で構成されているのが一般的であ
つた。また、ベクトル演算プロセツサにおけるベ
クトル浮動小数点乗算については高速処理が要求
され、１マシンサイクルで１エレメントの乗算処
理が必要である。例えば浮働小数点の仮数部が56
ビツトの場合、乗算をリコード乗算器で実現する
と、第２図に示すように、29個の部分積が必要で
ある。この29個の倍数を第３図に示す多入力桁上
げ保存加算器で加算すると、27個の３入力加算器
が必要である。また、桁上げ先見加算器のデータ
幅も112ビツトが必要となる。
このように従来のパイプライン化乗雑器で１エ
レメント／マシンサイクルの高速性能を実現する
には、多大な金物（ハードウエア）を要し、価格
を引き上げる欠点があつた。
〔発明の目的〕
本発明は、上記の欠点を解決するものであり、
比較的高精度の精度を保ちつつ金物量の大幅な削
減を実現した高速なパイプライン乗算回路を提供
することを目的とする。
〔発明の要点〕
本発明は、２入力浮動小数点データを乗算する
パイプライン化乗算回路において、
Ｍ（Ｍは仮数部のビツト長で整数）ビツトの被
乗数とＭビツトの乗数との部分積群の下位Ｍ＋Ｎ
＋Ｓ＋ｌ（Ｎ、Ｓは整数）ビツトから2Mビツト部
までを削除して上位Ｍ＋Ｎ＋Ｓビツト部のみを作
成する部分積群作成回路と、
該部分積群作成回路の出力を入力し、Ｍ＋Ｎ＋
ｌビツトからＭ＋Ｎ＋Ｓビツトの最終和および最
終桁上げを作成する桁上げ保存加算トリー部を切
り捨て、すなわち、最上段から下段に桁上げ出力
が伝播される毎に桁上げ保存加算トリーの最下位
ビツトの部分和と部分桁上げを切り捨てて、Ｍ＋
Ｎビツトの最終和と最終桁上げを出力するＳ段の
多入力桁上げ保存加算器と、
この桁上げ保存加算器の２出力を入力し加算す
る桁上げ先見加算器と
を備えたことを特徴とする。
〔実施例による説明〕
以下、本発明の実施例を図面に基づいて説明す
る。
第４図は本発明実施例回路のブロツク構成図で
ある。また、第５図は本実施例回路で扱う浮動小
数点のデータ形式を示す図であり、同図におい
て、Ｓは仮数部MAの符号、Ｅは指数部（7bit）、
MAは絶対値表現の仮数部（56bit）である。
第４図において、１０は被乗数の仮数部56ビツ
トを格納するレジスタ、１１は乗数の仮数部56ビ
ツトを格納するレジスタ、１２は被乗数と乗数と
の倍数を作成する部分積群作成回路である。
被乗数の倍数を作成するアルゴリズムはリコー
ド手法を用いている。リコード手法では、第６図
に示すように、乗数56ビツトa1、a2…a56を１ビ
ツト重ね合わせ、各々３ビツトに分割し、M0、
M1〜M28の組とする。M0〜M28の重み付けは
（−２、１、１）であり、３ビツトのビツトパタ
ーンにより倍率は次表のように設定される。この
３ビツトのM0〜M28対応に部分積29個が作成さ
れる。
[Technical Field to Which the Invention Pertains] The present invention relates to a pipelined multiplication circuit in a data processing device. [Description of the Prior Art] Conventionally, this type of pipelined floating-point multiplication circuit, as shown in FIG. 2. A partial product group creation circuit 3 that inputs a multiplicand and a multiplicand and creates a multiple of the multiplicand; a multi-input carry save adder that adds the outputs of the partial product group creation circuit 3 and outputs the final sum and final carry; 4. A final sum register 5 and a final carry register 6 that store the final sum and final carry, a carry look-ahead adder 7 that adds the two inputs of the final sum register 5 and the final carry register 6, and an operation result register. 8 and a control circuit 9. Furthermore, high-speed processing is required for vector floating point multiplication in a vector arithmetic processor, and one element must be multiplied in one machine cycle. For example, the mantissa of a floating point number is 56
In the case of bits, if multiplication is implemented using a recode multiplier, 29 partial products are required, as shown in FIG. When these 29 multiples are added using the multi-input carry save adder shown in FIG. 3, 27 three-input adders are required. The data width of the carry look-ahead adder also requires 112 bits. As described above, in order to achieve high-speed performance of one element/machine cycle with the conventional pipelined multiplier, a large amount of hardware is required, which has the disadvantage of increasing the price. [Object of the invention] The present invention solves the above-mentioned drawbacks,
The purpose of the present invention is to provide a high-speed pipeline multiplication circuit that achieves a significant reduction in the amount of hardware while maintaining relatively high accuracy. [Summary of the Invention] The present invention provides a pipelined multiplication circuit that multiplies two-input floating-point data, in which a partial product group of an M (M is the bit length of the mantissa and an integer) bit multiplicand and an M-bit multiplier is calculated. Lower M+N
+S+l (N and S are integers) bits to 2M bits are deleted and only the upper M+N+S bits are created by inputting the output of the partial product group creating circuit and M+N+
The carry-save addition tree section that creates the final sum and final carry of M+N+S bits from l bits is truncated, that is, the least significant bit of the carry-save addition tree is truncated every time the carry output is propagated from the top to the bottom. Round down the partial sum and partial carry, and get M+
It is characterized by being equipped with an S-stage multi-input carry save adder that outputs an N-bit final sum and a final carry, and a carry look-ahead adder that inputs and adds the two outputs of this carry save adder. shall be. [Explanation based on Examples] Examples of the present invention will be described below based on the drawings. FIG. 4 is a block diagram of a circuit according to an embodiment of the present invention. FIG. 5 is a diagram showing the floating point data format handled by the circuit of this embodiment. In the figure, S is the sign of the mantissa part MA, E is the exponent part (7 bits),
MA is the mantissa part (56 bits) of absolute value expression. In FIG. 4, 10 is a register that stores the 56-bit mantissa part of the multiplicand, 11 is a register that stores the 56-bit mantissa part of the multiplier, and 12 is a partial product group creation circuit that creates a multiple of the multiplicand and the multiplier. The algorithm for creating multiples of the multiplicand uses the recoding method. In the recoding method, as shown in Fig. 6, the 56-bit multipliers a 1 , a 2 . . .
Set as M1 to M28. The weighting of M0 to M28 is (-2, 1, 1), and the magnification is set according to the 3-bit bit pattern as shown in the following table. 29 partial products are created corresponding to these 3 bits M0 to M28.
【表】
１３は部分積群作成回路１２で作成された被乗
数の倍数出力29本を入力し最終和および最終桁上
げを作成する桁上げ保存加算器である。１４は桁
上げ保存加算器１３の最終和出力を格納する64ビ
ツトのレジスタである。１５は桁上げ保存加算器
１３の最終桁上げ出力を格納する64ビツトのレジ
スタである。１６は最終和レジスタ１４の出力と
最終桁上げレジスタ１５の出力とを入力する64ビ
ツトの桁上げ先見加算器である。１７は桁上げ先
見加算器１６の上位56ビツトを格納する演算結果
レジスタである。１８は指数部の処理等の制御を
行う制御回路である。
第７図は第４図の部分積群作成回路１２の詳細
な回路図である。部分積群は小数点以下72ビツト
より下位ビツトが切り捨てられる。72ビツトは仮
数部のビツト数Ｍの56ビツトと最終積の精度規定
値Ｎの８ビツトと桁上げ保存加算器の段数Ｓの８
ビツトとの算術和である。したがつて、１２−１
の部分積は16ビツト、１２−２の部分積は17ビツ
トと順次ビツト幅が拡がり、１２−２９の部分積
は56ビツトである。
第８図は第４図で示される多入力桁上げ保存加
算器１３の詳細な回路図であり、この桁上げ保存
加算器は、29本の部分積出力を入力し最終和およ
び最終桁上げを作成するものである。
第９図は第８図の桁上げ保存加算器１３の一部
分の回路図を示しており、最上段から下位段に桁
上げが伝播する毎に最下位の３入力加算器が削減
される様子を示している。最終和および最終桁上
げのビツト幅は72ビツトである。
このように、この桁上げ保存加算器１３は、部
分積群出力を入力として多入力加算し、最上段か
ら下段に桁上げ出力が伝播される毎に桁上げ保存
加算トリーの最下位ビツトの部分和と部分桁上げ
を切り捨て、すなわち、Ｍ＋Ｎ＋１ビツト（65ビ
ツト）からＭ＋Ｎ＋Ｓビツト（72ビツト）までに
ついてそれぞれの最終和および最終桁上げを作成
する桁上げ保存加算トリー部を切り捨て、Ｍ＋Ｎ
ビツト（64ビツト）の最終和および最終桁上げと
を出力する。
次に本発明の特徴的な構成について述べる。
最近、浮動小数点の乗算器は汎用機でも１サイ
クルで処理する乗数のビツト幅は12、16、24ビツ
トまたはそれ以上と拡大されてきており、またベ
クトル演算プロセツサの分野でも１サイクルで１
エレメントの処理をする高速性能のパインライン
化乗算器が要求されるようになつている。前述し
たように、従来の回路により仮数部56ビツトの被
乗数と乗数との乗算を１サイクルで１エレメント
の処理を実現するには、第１図で示したように、
多大の金物を要し、価格を引き上げていた。この
欠点を除去するため、本発明実施例では第７図の
ように部分積群の2-73ビツト以下のハードウエア
を削除し、第９図で示したように、最終和および
最終桁上げの72ビツトを作成する桁上げ保存加算
器を設けることにより積の誤差を2-56＋2-64の精
度にしている。
〔発明の効果〕
本発明は、以上説明したように、Ｍビツトの被
乗数と乗数との部分積群の下位Ｍ＋Ｎ＋Ｓ（Ｎ、
Ｓは整数）以降を切り捨てて上位Ｍ＋Ｎ＋Ｓビツ
ト部のみを作成する回路と、該部分積群を多入力
加算してＭ＋Ｎビツトの最終和と最終桁上げとを
出力するＳ段の多入力加算器と、桁上げ先見加算
器とで構成することにより、従来のパイプライン
化乗算器の多大な金物量を要する欠点を除去し、
積の精度を高精度に保ちつつ金物量の大幅削減を
実現するパイプライン化高速乗算器を実現するも
のである。[Table] Reference numeral 13 is a carry save adder which inputs the 29 multiple outputs of the multiplicand created by the partial product group creation circuit 12 and creates the final sum and final carry. A 64-bit register 14 stores the final sum output of the carry save adder 13. A 64-bit register 15 stores the final carry output of the carry save adder 13. 16 is a 64-bit carry look-ahead adder which inputs the output of the final sum register 14 and the output of the final carry register 15; Reference numeral 17 denotes an operation result register for storing the upper 56 bits of the carry look-ahead adder 16. Reference numeral 18 denotes a control circuit that controls processing of the exponent part and the like. FIG. 7 is a detailed circuit diagram of the partial product group generation circuit 12 of FIG. 4. In the partial product group, bits lower than 72 bits below the decimal point are discarded. The 72 bits are the number of bits M in the mantissa, 56 bits, the specified accuracy value N of the final product, 8 bits, and the number of stages S, S, of the carry save adder.
It is an arithmetic sum with bits. Therefore, 12-1
The bit width gradually increases to 16 bits for the partial product of , 17 bits for the partial product of 12-2, and 56 bits for the partial product of 12-29. FIG. 8 is a detailed circuit diagram of the multi-input carry save adder 13 shown in FIG. 4. This carry save adder inputs 29 partial product outputs and calculates the final sum and final carry. It is something to create. FIG. 9 shows a circuit diagram of a part of the carry save adder 13 in FIG. 8, and shows how the lowest three-input adder is reduced each time a carry propagates from the top stage to the lower stage. It shows. The bit width of the final sum and final carry is 72 bits. In this way, this carry save adder 13 performs multi-input addition using the partial product group output as input, and adds the least significant bit part of the carry save addition tree each time the carry output is propagated from the top stage to the bottom stage. Truncating the sum and partial carry, that is, truncating the carry-save addition tree part that creates the final sum and final carry for M+N+1 bits (65 bits) to M+N+S bits (72 bits), respectively.
Outputs the final sum and carry of bits (64 bits). Next, the characteristic configuration of the present invention will be described. Recently, the bit width of floating-point multipliers that can process multipliers in one cycle has been expanded to 12, 16, 24 bits, or more even on general-purpose machines, and in the field of vector arithmetic processors, the bit width of multipliers that can be processed in one cycle has also been expanded.
There is an increasing demand for high-speed performance pinelining multipliers that process elements. As mentioned above, in order to realize the multiplication of a 56-bit mantissa multiplicand and a multiplier by one element in one cycle using a conventional circuit, as shown in FIG.
It required a large amount of hardware and raised the price. In order to eliminate this drawback, in the embodiment of the present invention, as shown in FIG. 7, the hardware of 2 to 73 bits or less of the partial product group is deleted, and as shown in FIG. By providing a carry-save adder that creates 72 bits, the product error is reduced to an accuracy of 2 -56 + 2 -64 . [Effects of the Invention] As explained above, the present invention provides the lower order M+N+S(N,
A circuit that creates only the upper M+N+S bit part by truncating the bits after S is an integer, and an S-stage multi-input adder that adds the partial product group to multiple inputs and outputs a final sum of M+N bits and a final carry. , and a carry look-ahead adder, it eliminates the drawback of conventional pipelined multipliers that require a large amount of hardware.
The objective is to realize a pipelined high-speed multiplier that can significantly reduce the amount of hardware while maintaining high product accuracy.
第１図は従来のパイプライン乗算回路の構成を
示すブロツク構成図。第２図は第１図に示した部
分積群作成回路３部分の詳細なブロツク構成図。
第３図は第１図に示した多入力桁上げ保存回路４
の詳細なブロツク構成図。第４図は本発明の一実
施例回路を示すブロツク構成図。第５図は本実施
例回路で扱う浮動小数点のデータ形式を示す図。
第６図はリコード手法におけるデータの取扱いを
説明する図。第７図は第４図の部分積群作成回路
１２の詳細な回路図。第８図は第４図の桁上げ保
存加算器１３の詳細な回路図。第９図は第８図の
桁上げ保存加算器の一部の回路図。
１，１０……被乗数レジスタ、２，１１……乗
数レジスタ、３……部分積群作成回路（112bit）、
４……多入力桁上げ保存加算器（112bit）、５…
…最終和レジスタ（112bit）、６……最終桁上げ
レジスタ（112bit）、７……桁上げ伝播加算器
（112bit）、８，１７……演算結果レジスタ
（65bit）、９，１８……制御回路、１２……部分
積群作成回路（72bit）、１３……多入力桁上げ保
存加算器（72bit）、１４……最終和レジスタ
（64bit）、１５……最終桁上げレジスタ、１６…
…桁上げ先見加算器（64bit）。
FIG. 1 is a block diagram showing the configuration of a conventional pipeline multiplier circuit. FIG. 2 is a detailed block diagram of the three parts of the partial product group generation circuit shown in FIG. 1.
Figure 3 shows the multi-input carry storage circuit 4 shown in Figure 1.
Detailed block configuration diagram. FIG. 4 is a block diagram showing a circuit according to an embodiment of the present invention. FIG. 5 is a diagram showing a floating point data format handled by the circuit of this embodiment.
FIG. 6 is a diagram explaining the handling of data in the recode method. FIG. 7 is a detailed circuit diagram of the partial product group generation circuit 12 of FIG. 4. FIG. 8 is a detailed circuit diagram of the carry save adder 13 of FIG. 4. FIG. 9 is a circuit diagram of a portion of the carry-save adder of FIG. 8. 1, 10... Multiplicand register, 2, 11... Multiplier register, 3... Partial product group creation circuit (112 bits),
4...Multi-input carry save adder (112bit), 5...
...Final sum register (112bit), 6...Final carry register (112bit), 7...Carry propagation adder (112bit), 8, 17... Arithmetic result register (65bit), 9, 18... Control circuit , 12...Partial product group creation circuit (72bit), 13...Multi-input carry save adder (72bit), 14...Final sum register (64bit), 15...Final carry register, 16...
...Carry look-ahead adder (64bit).
Claims (1)
るパイプライン化乗算回路であり、 被乗数と乗数との部分積を作成する部分積群作
成回路と、 この部分積群作成回路の出力から最終和と最終
桁上げとを出力する多入力桁上げ保存加算器と、 この多入力桁上げ保存加算器の出力する最終和
と最終桁上げの２出力を加算する桁上げ先見加算
器と を備えたパイプライン化乗算回路において、 上記部分積群作成回路は、 Ｍ（Ｍは仮数部のビツト長で正の整数）ビツト
の被乗数とＭビツトの乗数との部分積群の上位Ｍ
＋Ｎ＋Ｓ（Ｎ、Ｓは正の整数で、Ｎは最終積の精
度規定値であり、Ｓは上記多入力桁上げ保存加算
器の段数である。）ビツト部分を作成する手段を
含み、 上記多入力桁上げ保存加算器は、 Ｓ段で構成され、上記部分積群作成回路の出力
を入力しＭ＋Ｎ＋１ビツトからＭ＋Ｎ＋Ｓビツト
までについてそれぞれの最終和および最終桁上げ
を作成する桁上げ保存加算トリー部を切り捨て
て、Ｍ＋Ｎビツトの最終和と最終桁上げとを出力
する手段を含み、 上記桁上げ先見加算器は、 上記多入力桁上げ保存加算器の上記Ｍ＋Ｎビツ
トの最終和と最終桁上げとの２出力を入力し加算
する手段を含む ことを特徴とするパイプライン化乗算回路。[Scope of Claims] 1. A pipelined multiplication circuit that multiplies two input floating point data, comprising: a partial product group creation circuit that creates a partial product between a multiplicand and a multiplier; A multi-input carry save adder that outputs a final sum and a final carry from its output, and a carry look-ahead adder that adds the two outputs of the multi-input carry save adder, the final sum and final carry. In the pipelined multiplication circuit, the above partial product group generation circuit calculates the upper M of the partial product group of the M (M is the bit length of the mantissa part and is a positive integer) bit multiplicand and the M bit multiplier.
+N+S (N and S are positive integers, N is the specified accuracy of the final product, and S is the number of stages of the multi-input carry save adder.) The carry-save adder is composed of S stages, which inputs the output of the above-mentioned partial product group generation circuit, and truncates the carry-save addition tree section that creates the final sum and final carry for M+N+1 bits to M+N+S bits. and includes means for outputting a final sum of M+N bits and a final carry, and the carry lookahead adder has two outputs of the final sum of M+N bits and a final carry of the multi-input carry save adder. A pipelined multiplication circuit comprising means for inputting and adding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58059585A JPS59184945A (en) | 1983-04-04 | 1983-04-04 | Multiplication circuit for formation of pipeline |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58059585A JPS59184945A (en) | 1983-04-04 | 1983-04-04 | Multiplication circuit for formation of pipeline |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59184945A JPS59184945A (en) | 1984-10-20 |
| JPH028328B2 true JPH028328B2 (en) | 1990-02-23 |
Family
ID=13117448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58059585A Granted JPS59184945A (en) | 1983-04-04 | 1983-04-04 | Multiplication circuit for formation of pipeline |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59184945A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4958312A (en) * | 1987-11-09 | 1990-09-18 | Lsi Logic Corporation | Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS588353A (en) * | 1981-07-06 | 1983-01-18 | Nec Corp | Multiplier |
-
1983
- 1983-04-04 JP JP58059585A patent/JPS59184945A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59184945A (en) | 1984-10-20 |
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