JPH028333B2 - - Google Patents

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides a buffer storage device for operand access, a buffer storage device for instruction fetch, and a plurality of store address registers for performing store access to main storage. The present invention also relates to a store buffer control method in a data processing device equipped with a store buffer constituted by a store data register.

In recent years, various methods have been considered to improve the performance of data processing devices, and one of the methods is a pipeline method. This method divides one instruction execution sequence into multiple phases, provides multiple stations to execute each phase, and configures each station to operate independently. They are intended to be processed simultaneously.

Usually, the central processing unit (hereinafter referred to as CPU), which is the core of a data processing device, is as shown in Figure 8.
Three functional blocks, namely I-UNIT1, E-
It is composed of a UNIT 2, an S-UNIT 3, and a buffer storage device (BS) 4.

I-UNIT1 decodes instructions and controls the entire pipeline of the CPU. E-UNIT2 performs calculations, and S-UNIT3 performs buffer storage (hereinafter referred to as
This is a unit that controls access to the BS (BS) 4 and the main memory (not shown).

As an example of the above CPU pipeline, I-
Figure 9 shows the pipeline of UNIT1.

One instruction is the instruction fetch phase (INST
FETCH) after being read from BS4, φA ~ φF
It is processed by passing through the following six phases.

A portion of each phase is divided into two or three cycles, and the processing assignments for each cycle are as follows.

I: Instruction fetch address calculation.

T: Refer to the address translation buffer (TLB) and the tag section of BS4 for the address of the instruction.

B: Reading of BS4.

D: Decoding the command.

R: Register read.

A: Operand fetch address calculation.

T: Access the address translation buffer (TLB) and the tag section of BS4 for the address of the operand.

B: Reading of BS4.

E1: Operation execution cycle 1.

E2: Operation execution cycle 2.

V: Check cycle.

W: Write cycle of operation results.

In the above CPU pipeline, the first one shows how access to BS4 is performed.
0, which shows the pipeline b of the S-UNIT3 that controls the BS4 in comparison with the pipeline a of the I-UNIT1.

As is clear from the figure, both instruction fetch and operand access consist of four cycles, and the processing in each cycle is as follows.

P: Priority cycle that determines the priority for using BS4.

T: For the fetch address, refer to the address translation buffer (TLB) and the tag section of BS4.

B: Reading of BS4.

R: Depending on the access result, the read data is
-Result cycle sent to UNIT1 and E-UNIT2.

Access to BS4 is as shown in Figure 10.
In the pipeline that processes one instruction, the I cycle and A cycle are issued twice.

Therefore, in order to avoid conflict between accesses to the two BS4s, one instruction is processed every two cycles so that the I cycle and A cycle do not overlap. This relationship is the 11th
It is indicated by diagonal lines in the figure.

If a CPU using this pipeline is configured so that instructions can be input to the pipeline every cycle, the processing speed of the CPU can be doubled.

However, if the pipeline is activated every cycle, a conflict will occur between the I cycle and the A cycle, and even if two instructions can be fetched per I cycle, the processing capacity of the pipeline of the I-UNIT1 will be limited. This means that only one instruction can be executed in 1.5 cycles.

Therefore, if you want to configure an efficient every-cycle pipeline, you need a BS for instruction fetching,
It is necessary to separate the BS for operand fetch and create a configuration that allows each to operate independently.

The problem with having the above two BSs is:
This is a control to match the contents when the same block (in units of 32 bytes or 64 bytes) exists in the two BSs.

The problem is that the two CPUs are
It is similar to the control method that matches data when you have BS.

[Conventional technology]

FIG. 12 shows an example of the conventional system having the above two BSs. In this figure, 31 is an operand effective address register (hereinafter referred to as OER), 32 is a buffer memory for operand access (hereinafter referred to as operand buffer memory), 33 is an operand word register (hereinafter referred to as OWR), and 34 is an instruction. Effective register (hereinafter referred to as IER), 35 an instruction fetch buffer memory (hereinafter referred to as instruction fetch buffer memory), 36 an instruction word register (hereinafter referred to as IWR), 37 an operand store data register (hereinafter referred to as OSDR). , 38 are instruction store data registers (hereinafter referred to as ISDR).

In this conventional example, the address of the operand fetch from I-UNIT1 is set in OER31, the operand buffer memory 32 is accessed, and the read data is set in OWR33 and sent to E-UNIT2. .

Similarly, the instruction fetch address is IER3
4, command fetch buffer memory 35
The read data from is set in IWR36 and sent to I-UNIT1.

The operand store address above is OER1,
and IER 34 at the same time, and it is checked not only in operand buffer storage 32 but also in instruction fetch buffer storage 35 whether or not a data block at the address exists.

This is because even if an instruction sequence is placed at the beginning of the data block, data may be included after it.

Then, when the block exists, E-
OSDR the operand store data from UNIT2
37 and ISDR 38, and writes to the block at the corresponding address in the operand buffer memory 32 and the instruction fetch buffer memory 35.

On the other hand, when an operand fetch or an instruction fetch is performed, if the corresponding address does not exist in the buffer storage, a block transfer request for the data at the address is issued to the main memory (not shown), and the block transfer is performed. The data that came
It operates so that it is written to the two buffer memories mentioned above.

[Problem that the invention seeks to solve]

In the above-mentioned conventional method, when storing an operand, the pipeline indicated by P, T, B, and R of the S-UNIT 3 that accesses the operand buffer storage 32 and the pipeline of the S-UNIT 3 that accesses the instruction fetch buffer storage are used. line and the first
As shown in Figure 3, there is a problem that requires synchronization.

That is, as shown in 1 in the figure, if both Pop and Pip get priority in the priority cycle, they can immediately access the buffer for storing, but as shown in 2, for example, the buffer for instruction fetching When the memory is processing a block transfer request (Pmi), Pif is delayed by three cycles, and in order to synchronize with this, the pipeline on the operand side is also forced to wait for three cycles.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the conventional art, it is an object of the present invention to provide a means for reflecting operand stores in instruction fetch buffer storage without synchronizing both the operand fetch and instruction fetch pipelines.

[Means for solving problems]

This purpose includes a buffer storage device for operand access, a buffer storage device for instruction fetch, and a store buffer composed of a plurality of store address registers and store data registers for performing store access to the main storage device. The instruction fetch is performed from the instruction fetch buffer storage device,
The operand fetch is performed from the operand access buffer storage device, and the operand store is performed from the operand access buffer storage device,
In a data processing device having a means for performing the operand store in the store buffer in the same sequence and reflecting the operand store in the instruction fetch buffer storage device in a different sequence from the store buffer, the store buffer is reflected in the instruction fetch buffer storage device. It has a store address to be stored, multiple hold (HOLD) flags indicating that store data is being held, and a pointer indicating which of multiple store buffers should be reflected in the instruction fetch buffer storage device. When starting the write sequence to the buffer storage device for IF ST, the instruction fetch store transmission (IF ST
By turning on the ISSUED flag and using the value of the above pointer as an identification (ID) bit at each cycle of the write sequence, at the end of the write, the store buffer indicated by the above identification (ID) bit is held (HOLD). ) flag, and if the above write sequence is interrupted, the above hold (HOLD) flag is reset by resetting the instruction fetch store issue (IF ST ISSUED) flag of the store buffer indicated by the above identification (ID) bit. On,
And send command fetish store (IF ST ISSUED)
This is achieved by the instruction buffer store control method of the present invention, which restarts the write sequence for store buffers whose flags are off.

This uses the address and data of the store buffer provided in the store-through type buffer storage to reflect the operand store in the instruction fetch buffer storage.

[Effect]

That is, according to the present invention, it is composed of an operand buffer memory, an instruction fetch buffer memory, a plurality of store address registers (STAR) for performing store access to the main memory, and a store data register (STD). In a data processing device having a store buffer, a plurality of store addresses and store data to be reflected in the instruction fetch buffer memory are stored.
an STB HOLD flag, an IF ST ISSUED flag indicating that a write to the instruction fetch buffer memory has been sent to the instruction fetch pipeline;
It is equipped with an ID bit that indicates which store buffer inputs the instruction into the fetch pipeline, and when the subsequent pipeline processing is canceled due to the delay of the preceding pipeline processing, the instruction is input to the fetch pipeline.
By resetting the ST ISSUED flag,
If the above STB HOLD flag is on, IF ST
By detecting a store buffer whose ISSUED flag is off, the canceled pipeline processing is reintroduced to the instruction fetch pipeline, so the instruction fetch buffer memory of the operand store is This has the effect of allowing the reflection of information to be carried out without contradiction.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
The present invention is based on the premise that the store access from I-UNIT 1 is a so-called store-through method in which the store address and data are set in a store buffer that can hold the data at the same time as writing to the buffer memory, and the data is also written to the main memory.

FIG. 1 is a block diagram showing a configuration example related to the basic operation of the present invention, FIG. 2 is a diagram showing the configuration of a store buffer (STB), and FIGS. 3A and B are examples of the embodiment shown in FIG. 1. Figure 4 shows the detailed configuration of
A diagram explaining the operation of STB VALID and STB READY, FIG. 5 is a diagram showing the operation of the store buffer control flag as a time chart, and FIG. 6 is a diagram explaining the operation of ID for the instruction fetch pipeline.
FIG. 7 is a time chart showing the operation when store access control is performed by implementing the present invention.

In FIG. 1, 31 to 38 are the same as those explained in FIG. STB HOLD flag H, which is the control flag of the store buffer (STB) shown, and IF
The ST ISSUED flag I is a functional block necessary to implement the present invention.

First, the operand store address from I-UNIT1 is not set in IER34, but is stored in OER.
It is checked whether the address exists in the operand buffer memory 32, and if so, the operand store data set in the OSDR 37 is written to the operand buffer memory 32.

At the same time, the operand store address is
STAR 390 is set, operand store data from E-UNIT2 is set to STD 391, and then a write request to the main memory is issued.

The present invention provides the operand store address provided in the store-through type buffer storage and the STAR3 in which the data is set.
By using the addresses and data of 90 and STD 391, the operand store is reflected in the instruction fetch buffer memory 35.

The operand store address set in the STAR 390 is set in the IER 34, and it is checked whether the address exists in the instruction fetch buffer memory 35. If the address exists, the store data in the STD 391 is written to the instruction fetch buffer memory 35 through the ISDR 38.

Due to the above operation, in operand store access, it is no longer necessary to execute both the operand fetch and instruction fetch pipelines synchronously, and the operand store is reflected in the instruction fetch buffer memory 35 in the store buffer (STB). Using the address (i.e. contents of STAR390) and data (STD391), I-
This can be done asynchronously with the pipeline of UNIT1. However, STAR390 and STD391 are
It has already been provided as a component of S-UNIT3, and its feature is that by reusing it, it can be implemented without adding almost any new hardware.

Next, detailed operations when implementing the present invention will be described using FIGS. 3 to 7.

For convenience, FIG. 3A and FIG. 3B are obtained by dividing one drawing at the positions indicated by dashed-dotted lines.

In this figure, the operand access address and instruction fetch address from I-UNIT are set in OER31 and IER34, respectively, and at the same time address translation buffer OP TLB311,
When a logical address is converted into a real address at high speed by the IF TLB 312, buffer memories 32, 35
OP that remembers the block address of each
Access BS TAG313 and IF BS TAG314.

The logical addresses read from the above OP TLB 311 and IF TLB 312 are
16, the address is checked to see if it is the applicable address, and at the same time the real address part is sent to the OP BS.
It is compared with the block address of the buffer memory held in TAG313 and IF BS TAG314, and the OP BS TAG313 and IF BS TAG314 are
1 out of 16 comparators 317 and 318
When the two match signals become valid, the outputs of the operand buffer memory 32 and the instruction fetch buffer memory 35 are selected by the align & select circuits 319 and 320, respectively, and are used as operand data and instruction data, respectively.
Sent to UNIT, I-UNIT.

Operand real address register (hereinafter referred to as ORR)
) 321, instruction real address register (hereinafter referred to as IRR) 322, comparator circuits 315, 31
6, the address translation buffer where the match occurred
PRIMARY of TLB311,312,
When the real address held in one of the ALTERNATE registers is received and the corresponding block does not exist in the buffer memories 32 and 35, it is used to set the transfer request address to the main memory in the MAR 323.

To describe the above operation in more detail, when accessing the operand store, the OER 31 is set, the OP TLB 311 and the OP BS TAG 313 are accessed, and it is determined whether or not the block to be stored exists in the operand buffer memory 32. investigate.

At the same time, the real address from OP BS TAG311 is sent to four STAR3 via ORR321.
90 as a store address to the main memory.

Data to be stored is sent from the E-UNIT, passes through the store align circuit 324, and is set in one of the four store buffers STD 391.

Writing to the operand buffer memory 32 is as follows:
It is performed from the OSDR 37 through the store alignment circuit 324.

The store buffer holds the real address of the store to main memory, as shown in Figure 2.
Holds STAR390 and 8 bytes of data
It consists of STD391, and the above is used as a control flag.
There is a valid flag V indicating that an address has been entered in STAR390, a ready flag R indicating that data has been entered in STD, and a byte mark (BM) indicating the write byte position when writing a portion of 8 bytes or less. The STB HOLD flag H indicates that store data to be reflected in the instruction fetch buffer memory is held, and the IF ST indicates that a write access to the instruction fetch buffer memory has been input to the instruction fetch pipeline.
ISSUED flag I is provided.

The four store buffers are used in order for each access, and when the fourth store buffer is reached, if the data has been written to the main memory, the function is to cyclically return to the first store buffer.

The instruction is reflected in the fetch buffer memory 35 by selecting four STARs 390 by the select circuit 325.
One of them is selected and set in IER34.

At the same time, IF BS TAG314 is accessed,
It is checked whether the corresponding block exists or not. At this time, since the address set in IER34 is a real address, there is no need to use TLB312,
The value of IER 34 is sent directly to comparator 318.
(Not shown) If the store address exists in the instruction fetch buffer memory 35, the corresponding store data in the STD 391 is selected by the select circuit 326 and written to the instruction fetch buffer memory 35 via the ISDR 38.

At the same time as the instruction is reflected in the fetch buffer memory 35, STAR 390 passes through the select circuit 325 and is set in MAR 323, becoming the store address to the main memory, and the corresponding data in STD 391 passes through the MDI 327 and is set to the main memory. Sent as write data.

After the operand store address enters STAR 390 and the instruction fetch buffer memory 35
If the same address enters the IER 34 before the instruction has been reflected in the IRR 322, the comparator 328 checks the real address of the instruction fetch set in the IRR 322 and the real address of the store in the STAR 390, and if they match. Then, he instructs her to repeat the command fetish.

If all four STARs 390 are used and a new operand store address cannot be set, the above addresses cannot be compared, so in order to guarantee the order of operand store access and instruction fetch, All instruction fetch accesses must wait until STAR 390 can receive the next store address. Therefore, the redoing of these instruction fetches is controlled by I-UNIT1. (Not shown) The above operations ensure the order of operand store access and instruction fetch. The control circuit for the instruction fetch retry signal is a NAND circuit 329 with negative input.

Note that the store is reflected in the instruction fetch buffer memory 35 because the present invention is based on a store-through method.
It is clear that this can also be achieved by invalidating the corresponding block address on the IF BS TAG 314 without writing to it.

The present invention relates to the control of the store buffer when the store is reflected in the instruction fetch buffer memory 35.

As mentioned above, the valid flag V (hereinafter referred to as STB VARID) is used as a control flag for the store buffer.
) and ready flag R (hereinafter referred to as STB).
READY), and the details of its operation are shown in Figure 4.

First, operand store access is performed using the OP TLB 311 in FIG. 3, as shown in this figure.
The first flow (P, T, B, R) that accesses the OP BS TAG 313 and indicates whether there is a block to be stored or not, and the OP BS DATA 32,
It consists of a second flow (P, W, S) that writes data from E-UNIT. Here, W: write cycle for TLB and TAG.

S: Write cycle for BS.

It is.

STB VALID is STAR390 and ORR32
It is turned on in the R cycle when the store address from 1 is set, and STB READY is set to STD.
It is controlled to be turned on in the S cycle when data from the store align circuit 324 is set in 391.

The store address and store data set in STAR390 and STD391 are respectively stored in MAR32 at the end of the S cycle.
3. It is set in the MDI 327 and sent to the main memory, and at the timing of completion of the sending, the above
STB VALID and STB READY flags are reset.

In this example, four STAR390,
It has STD391, and which of these to use is selected by a signal decoded from a 2-bit pointer.

STAR390 selection is pointer STB INP
After the STAR390 is set,
+1 and operates to indicate the next STAR390.

Pointer STB DINP is STB of B cycle
Shift the INP value to W cycle and STAR39
Used to select STD391 corresponding to 0.

Use the pointer STB OUTP to determine which store buffer should be set to MAR323 and MDI327.
The decoded output is used as a control signal for the selection circuit (SEL).

In a buffer storage device having such a configuration, the order of sending to the main storage device and store access to the instruction fetch buffer storage 35 is not necessarily determined.

This is because sending to main memory is possible when the interface bus is "free" and must wait if another request is already being sent.

Store access to the instruction fetch buffer memory 35 will not necessarily be accepted if the pipeline on the instruction fetch side is busy.

Furthermore, even after the instruction is accepted by the pipeline on the fetch side, processing cannot be continued depending on the state of the preceding request, and is temporarily canceled.
You may be required to re-enter the system.

In order to control store access like this,
In the present invention, the STB indicates that store data to be reflected in the instruction fetch buffer memory 35 is held in the store buffer as described above.
A HOLD flag, an IF ST ISSUED flag that indicates that a write access to the instruction fetch buffer memory 35 has been sent to the instruction fetch side pipeline, and an ID bit that indicates from which store buffer the instruction was input to the instruction fetch pipeline. There is.

These two flags and the STB mentioned above
Figure 5 shows the timing relationship between the VALID and STB READY flags.

The STB HOLD flag is set in the same R cycle as the STB VALID flag, indicating that store access to the instruction fetch buffer memory 35 is on hold.

Inputting the instruction from the store buffer to the instruction fetch pipeline is performed using the pointer STB IF STP in Figure 4.
If the STB HOLD flag is attached to the store buffer indicated by this pointer, a request with priority P (IF ST IOW) (the first flow) is sent to the instruction fetch pipeline shown in FIG. stand up

When this request is prioritized and the instruction fetch pipeline is activated, the IF ST ISSUED flag of the corresponding store buffer is turned on.
Indicates that a store access to the instruction fetch buffer memory 35 has been sent.

In the instruction fetch pipeline, as shown in Figure 6, when the above IF ST LOW request moves to the T cycle, the IF ST ISSUED flag corresponding to the decoded output of STB IF STP is set, and the IF ST ISSUED flag is set from which store buffer. First, the contents of STB IF STP indicating whether a store access has been entered is set to T ID, and then B ID,
It is shifted to R ID and W ID.

In the R cycle, if it is found that there is no address block to be stored in the instruction fetch buffer memory 35, the STB HOLD flag of the store buffer indicated by the decoded output of R ID is set to
As shown in FIG. 5, it is reset at the end of the R cycle.

If an address block exists,
P (IF ST HIGH) (the second flow) for writing is set and the write flow is activated.

The ID of the store buffer in this case is indicated by W ID, and the corresponding STB HOLD flag will be reset.

The STB HOLD flag is as shown in FIG. 3B.
Indicates that the data has not been reflected in the instruction fetch buffer memory 35, and the actual address of the instruction fetch set in the IRR 322 and the STAR 39
It is used as a control signal to determine whether the comparator 328 should check the real address of the store within 0.

When the STB HOLD flag is turned off, the result of the comparator 328 is controlled to be ignored.

In such a store access to the instruction fetch pipeline, if the preceding address block of P (IF ST LOW) exists in the instruction fetch buffer memory 35, as shown in FIG. There is a need to do.

At this time, it is fine as long as the P(IF ST HIGH) request takes priority, but as shown in the figure, if it is delayed for one cycle, the subsequent P(IF ST HIGH)
LOW) destroys the information (not shown) stored for P(IF ST HIGH), subsequent requests must be canceled at the end of the B cycle.

In such a case, it is required to control the canceled store access so that it can be retransmitted.

In this embodiment, when such a case occurs in the T cycle and the B cycle as shown in the figure, the control flip-flop "IF ST WAIT" for starting the above-mentioned cancel is activated, and the T cycle in FIG. The IF ST ISSUED flag is reset by the decoded output of ID and B ID, so while the STB HOLD flag is turned on, the IF
ST ISSUED flag is turned off.

STB IF STP in Figure 6 is incremented by 1 when a store access is sent to the instruction fetch pipeline, but the IF ST ISSUED flag, T ID~
W ID indicates the canceled store buffer, so when a store buffer with the STB HOLD flag on and the IF ST ISSUED flag turned off is detected, the canceled P( IF ST
LOW) is controlled to be retransmitted. When retransmitting, there is a possibility that multiple stores within the same 8 bytes are in the store buffer, so in order to protect the order of store reflection, the above-mentioned
The IF BS TAG 314 may be instructed to be invalidated.

By controlling in this manner, the operand store can be reflected in the instruction fetch buffer memory 35 without any contradiction.

〔Effect of the invention〕

As described above in detail, the instruction buffer store control method of the present invention includes operand buffer storage, instruction fetch buffer storage, and a plurality of store address registers (STAR ) and a store buffer consisting of a store data register (STD), a store address to be reflected in the instruction fetch buffer memory, a plurality of STB HOLD flags indicating that store data is held, and an instruction. An IF ST ISSUED flag indicating that the write to the fetch buffer memory of the above instruction has been sent to the fetch pipeline, and an ID bit indicating from which store buffer the instruction was input to the fetch pipeline,
When a subsequent pipeline process is canceled due to a delay in the previous pipeline process, the corresponding
By resetting the IF ST ISSUED flag, the above STB HOLD flag is on and the IF ST
By detecting a store buffer whose ISSUED flag is off, the canceled pipeline processing is reintroduced to the instruction fetch pipeline, so the instruction fetch buffer memory of the operand store is This has the effect of allowing the reflection of information to be carried out without contradiction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration related to the basic operation of the present invention, FIG. 2 is a diagram showing an example of the configuration of a store buffer (STB), and FIGS. 3A and B
1 is a diagram showing the detailed configuration of the embodiment shown in FIG. 1, FIG. 4 is a diagram explaining the operation of STB VALID and STB READY, FIG. Figure 6 is a diagram explaining the operation of the ID for the instruction fetch pipeline, Figure 7 is a time chart showing the operation when controlling store access by implementing the present invention, and Figure 8 is a diagram explaining the operation of the central processing unit. (CPU) configuration, Figure 9 is a diagram explaining the operation of the I-UNIT pipeline, Figure 10 is an explanatory diagram showing the access timing to buffer memory for one instruction,
The figure is an explanatory diagram of two-cycle one-instruction processing, Figure 12 is a block diagram of a conventional system with two buffer memories, and Figure 13 is the synchronous control timing required for the conventional system shown in Figure 12. A diagram explaining
It is. In the drawings, 1 is I-UNIT and 2 is E-UNIT.
UNIT, 3 is S-UNIT, 4 is buffer memory, 3
1 is the operand execution address register (OER),
32 is operand buffer storage, 33 is operand word register (OWR), 34 is instruction execution register (IFR), 35 is instruction fetch buffer storage, 36 is instruction word register (IWR), 37 is operand store data register (OSDR), 3
8 is an instruction store data register (ISDR), 31
1,312 is an address translation buffer (OP TLB,
IF TLB), 313 and 314 are the tag part (OP BS
TAG, IF BS TAG), 317 and 318 are comparators, 35 and 36 are comparators, 319 is an align & select circuit, 324 is a store align circuit, 32
1 is the operand real address register (ORR), 3
22 is an instruction real address register (IRR), 390
is store address register (STAR), 391 is store data register (STD), is STB
VALID flag, STB READY flag, pointer STB INP, pointer STB OUTP,
is pointer STB IF STP, ~ is ID, I,
T, B, D, R, A, E1, E2, V, W, S are each cycle of the pipeline, STAR VALID V,
STB READY R, STB HOLD H, IF ST
The ISSUED flag I indicates a control flag.

Claims (1)

[Claims] 1 buffer storage device for operand access;
It is equipped with an instruction fetch buffer storage device and a store buffer composed of a plurality of store address registers and store data registers for performing store access to the main memory, and instruction fetches are performed from the instruction fetch buffer storage device. , the operand fetch is performed from the operand access buffer storage device, the operand store is performed to the operand access buffer storage device and the store buffer in the same sequence, and the operand store is reflected in the instruction fetch buffer storage device as described above. In a data processing device having a means for performing processing in a separate sequence from a store buffer, the store buffer has a store address to be reflected in the instruction fetch buffer storage device and a plurality of hold flags indicating that store data is held. , has a pointer indicating which of multiple store buffers should be reflected in the instruction fetch buffer storage device, and when a write sequence to the instruction fetch buffer storage device is started, the instruction corresponding to the store buffer indicated by the pointer is By turning on the IF ST ISSUED flag and using the value of the above pointer as the identification (ID) bit at each cycle of the write sequence, at the end of the write, the data indicated by the above identification (ID) bit Reset the store buffer's hold (HOLD) flag, and if the above write sequence is interrupted, the above identification (ID) is reset.
By resetting the instruction fetch store sending (IF ST ISSUED) flag of the store buffer indicated by the bit, the write sequence for the store buffer where the above hold flag is on and the instruction fetch store sending (IF ST ISSUED) flag is off. A store control method to an instruction buffer characterized by rebooting.