JPH028491B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a frequency divider formed on a semiconductor substrate by combining DC-driven Josephson logic circuits, and is particularly applicable to Josephson computers. The present invention relates to a DC-driven Josephson frequency divider which is designed to increase its operating speed to make it suitable.

[Background of the invention]

The prior art and its problems will be explained with reference to FIGS. 1 to 7. Conventionally, various types of frequency dividers using semiconductor integrated circuits have been proposed. For example, Charles A Lietchi, “A GaAs MSI Word
Generator Operating at 5 Gbist/s
Data Rate”IEEE J.of Microwave Thechnics
and Theory, Vol.MTT−30, No.7, 1980,
P.988 discloses a frequency divider composed of GaAs field effect transistors operating at 6.5GHz.
Power consumption is estimated to be approximately 100mW per bit.
Such a frequency divider is constructed by combining logic gates. Josephson logic circuits can also form logic gates, so they can form frequency dividers. In particular, Josephson logic circuits are characterized by ultra-high-speed operation that exceeds conventional semiconductor devices, so it is expected that frequency dividers with unprecedented high-speed operation will be constructed. In fact, HC Jones, “Self-Activating
Toggle”IBM Technical Disclosure Bulletin,
Vol. 23, No. 9, Feb. 1981 discloses a frequency divider using Josephson logic circuits. In the above document, an AC driven circuit is used. In the AC drive system, the waveform of the current flowing through the Josephson logic circuit becomes a rectangular wave as shown in FIG. 1st
In the figure, a region 1 in which the current is kept at a flat value is a valid period, and the logic operation proceeds during this period. Region 2 is an invalid period during which the polarity of the driving power source is switched, and no logic operation proceeds. In an AC drive circuit, if the region 2 is made too small, a malfunction called a punch-through phenomenon will occur. This phenomenon is described by EPHarris, “Punchthrough
in Josephson Logic Devices”IEEE Trans.on
Magnetics, Vol.MAG−17, No.1, Jan.1981,
Disclosed in PP603-606. For example, in order to suppress the probability of malfunction to 10 ^-22 , region 2 is 200 ps.
(picoseconds) or more. Then, the upper limit of the movable frequency of the frequency divider will be 5 GHz or less (considering the positive and negative halves of Figure 1 as independent periods),
The performance can be lower than that of conventional semiconductor circuit configurations. One solution to address these difficulties is to use DC driven circuits. Various types of DC-driven Josefson logic gates are known, but the representative ones are Current Steering Circuit (hereinafter referred to as CS circuit) and Hybrid Unlatching Flip Flop.
One example is Logic Element (hereinafter abbreviated as HUFFLE). These are SMFaris, “Loop
Decoder for Josephson Memory Arrays”
IEEE Journal of Solid State Circuits, Vol.
SC-14, No. 4, Aug. 1979, pp. 699-707 and AF
Hebard et al., “A DC-Powered Josephson
Flip Flop” IEEE Trans.on Magnetics, Vol.
These are logic gates disclosed in MAG-15, No. 1, Jan.

The operation of the CS circuit and HUFFLE will be explained below using diagrams. The CS circuit and HUFFLE basically consist of a combination of two Josephson elements, inductance, and resistance. One Josephson element is a Josephson magnetic quantum interferometer consisting of a single Josephson junction or a plurality of Josephson junctions. It is assumed that the threshold characteristic of this Josephson element is as shown in FIG. In FIG. 2, 11 indicates a threshold curve, 12 is a Josephson device, I _g is a gate current, I _c is a control current,
I _B is the bias current. In the CS circuit and HUFFLE, the bias current I _B is set so that the operating points of the two Josephson elements constituting them alternately take positions such as points 13 and 14.
Figure 3 shows the configuration of the CS circuit. In Figure 3,
G ₁ and G ₂ are Josephson elements, I _g is the gate current, I _io is the input current, I _B is the bias current, I ₁ and I ₂ are the currents flowing through the left loop and right loop, respectively, L ₁ and L ₂ is inductance.
The ratio of L ₁ and L ₂ is about 1:3 or more. This is for initial settings. Bias current I _B1 , I _B2
When set appropriately (that is, so as to realize operating points 13 and 14 in FIG. 2), input and output characteristics as shown in FIG. 4 are obtained. FIG. 4a shows the input current _Iio , and b shows the output currents _I1 and _I2 of each loop. Note that in a CS circuit, it is common to provide a damping resistor in parallel with the Josephson element, but this is omitted in FIG. Similarly,
The circuit configuration and input/output characteristics of HUFFLE are shown in Figures 5 and 6. L is the load inductance, R _L is the load resistance, I _put is the output current, and the other symbols are the same as in FIG. The bias current I _B is
In this case as well, settings are made so that operating points 13 and 14 in FIG. 2 are realized.

The CS circuit and HUFFLE perform majority logic operation. Therefore, by appropriately setting the magnitude of the bias current and the direction of the input, any function of OR, AND, NOR, or NAND can be performed.
This can be realized by a CS circuit or HUFFLE.

Here, FIG. 7 shows an example of a circuit diagram of a frequency divider constructed from an existing semiconductor circuit. This is an SEM
−ICONDUCTR DATA BOOK (TTL)
HITACHI, 1980, P.90. Consists of 2 NAND elements, 4 AND elements, and 2 NOR elements, and input signal
The Q output or output is divided by half the frequency with respect to CLK. Each gate in Figure 7
If you replace it with a CS circuit or HUFFLE, you can get a frequency divider circuit, but there are limits to the circuit's integration and speed. The operating speed of the CS circuit and HUFFLE depends on the magnitude of the damping resistance and load resistance, but mainly depends on the load inductance (L ₁ +L ₂ in Figure 3,
It depends on L in the figure. Unless these inductances are set to a certain value or more, the gate operation will become unstable. For example, as a Josephson element, the critical current density is 1000 A/cm ² and the junction area is 5 μmφ.
When using a junction Josephson magnetic quantum interferometer, L ₁ + L ₂ 60PH in CS circuit, L in HUFFLE
Must be 40PH. The gate delay times at this time (the time from the time when the input exceeds the threshold of the Josephson element until the time when the output reaches 90% of the steady value) are approximately 30 ps and 45 ps, respectively. Now,
The critical path in the circuit of FIG. 7 includes three stages of gates. Therefore, when a CS circuit is used as a logic gate, the half cycle of the input signal CLK must be approximately 90 ps or more, and when a HUFFLE is used, it must be 135 ps or more, which increases the frequency of the divider's movable frequency. The upper limit will be 5.5GHz and 3.7GHz, and will also be composed of conventional GaAs field effect transistors.
Frequency divider operating at 6.5GHz (Charles A.
Lietchi's literature).

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problems in the prior art, and to use a DC-driven Josephson integrated circuit, it is possible to operate at higher speeds than existing frequency dividers made of semiconductor elements, and it is less likely to malfunction. The aim is to provide peripheral equipment.

[Summary of the invention]

In order to achieve this object, the present invention has the following configuration.

That is, a first flip-flop circuit having first and second Josephson elements, and a third and fourth flip-flop circuit having first and second Josephson elements.
A DC drive type flip-flop circuit comprising: a second flip-flop circuit having a Josephson element; and means for applying a bias current to the first to fourth Josephson elements; the first and second flip-flop circuits are connected to each other; It is a Josephson frequency divider, and the first to fourth Josephson elements are:
Each of the first to fourth Josephson elements includes a Josephson junction therein;
Each of the Josephson elements is configured to receive a frequency-divided input signal and a signal from a flip-flop circuit different from the flip-flop circuit to which the Josephson element belongs, and the bias current is applied to each of the first to fourth Josephson elements. The sum of the frequency-divided input signal and the signals from the different flip-flop circuits determines the threshold value of the Josephson element in the order of the first Josephson element - the third Josephson element - the second Josephson element - the fourth Josephson element. It is characterized by being set so as to exceed.

[Embodiments of the invention]

An embodiment of a frequency divider in which a DC-driven Josephson flip-flop circuit is combined will be described below. First, the most basic frequency divider using a CS circuit as a flip-flop circuit will be explained using FIG.

This frequency divider consists of two CSs as shown in Figure 8a.
The circuits CS1 and CS2 are connected in series. In Figure 8a, 71, 72, 73, 74 are CS
Josephson elements are the constituent elements of circuits CS1 and CS2, and here an asymmetric two-junction magnetic quantum interferometer is used, of which 71 and 72 are gate current
73 and 74 are respectively driven by a current source 75 of _Ig , and a current source 76. Each Josephson element has three control lines. Wiring 78 applies bias current I _b1 to elements 71 and 72, and wiring 79 applies bias current to elements 73 and 74.
I give _b2 . The wiring 77 is a wiring through which the input current IN flows. The structure of the Josephson device is shown in FIG. 8b. This element forms a closed circuit with Josephson junctions J1 and J2 and an inductance L connecting them. The three control lines 85, 86, 87 are magnetically coupled to the inductance L. The currents flowing through the control lines 85, 86, and 87 are respectively I _C , I _C2 ,
Let it be I _C3 . R _D is the damping resistance. The threshold curve of this device is shown in FIG. 8c. The horizontal axis is the control current I _C and the vertical axis is the gate current I _G.

Since the gate current is constant at _Ig , the operating point exists on A.

The operating point on A is determined by the sum of the currents flowing through the control lines 85, 86, and 87. Due to the asymmetric structure of the device, the shape of threshold curve 88 is asymmetric. The reason for this asymmetry is that the gradient ΔI _g /ΔI _C of the threshold curve 88 at B is steep, and _the threshold current This is to suppress fluctuations in I _THC and obtain a stable operating range.
Since it is asymmetrical, a mark C is attached to the part where the gate current is injected. The magnitude of the damping resistance R _D is determined by the following equation: where C _J is the junction capacitance of J1 and J2, and L _T is the total inductance of the closed loop formed by elements 71 and 72 and inductance 80. is chosen as. Figure 8c shows the bias current
The method for setting I _b1 and I _b2 is also shown. That is, There is a relationship between The input current IN has an offset of I _g /2 and has a sine wave or similar waveform with a peak-to-peak amplitude of I _g .

The operation of this frequency divider will be explained with reference to FIG. 8e.
Prior to that, the name of each element and the name of the output current are determined as shown in FIG. 8d. That is, elements 71, 7
2, 73, 74 respectively Q _1A , Q _1B , Q _2A , Q _2B
and the respective output currents are I _1A , I _1B , I _2A , and I _2B . Three currents +IN, I _b1 , and I _2A are input to element Q _1A . Similarly, Q _1B has +IN, I _b1 , I _2B , and Q _2A
−IN, I _b2 and I _1B are input to Q _2B , and −IN, I _b2 and I _1A are input to Q 2B. When the bias currents I _b1 and I _b2 are set to the magnitudes shown in FIG. 8c, the input to each element changes as shown in FIG. 8e as the input current IN changes. In the figure, the length of the arrow indicates the magnitude of the current, and the direction of the arrow indicates the direction of the current.
First, as an initial state, the input current IN is zero,
Suppose that the gate current I _g is gradually raised from zero to a steady-state value. When the disequilibrium inductances 80 and 81 in FIG. 8a are sufficiently larger than 82 and 83, most of the gate current I _g flows to Q _1B and Q _2B , and I _1A ≒ I _2A ≒ 0, I _1B ≒ I _2B ≒I _g =I. At this time, in column 91 of Figure 8e, the current shown by the size of each arrow flows through each control line, and the total is 91 below.
A current as shown by the arrow is flowing in the meter column of 6. This allows the sum of control line currents to reach the threshold value with only Q _2A .
Although I exceeds _THC , there is no change in the state of the output current because no gate current flows through Q _2A from the beginning. When the input current IN is increased from 0 to I in this state, the current shown in column 92 flows through each control line of each element, resulting in a total current as shown in column 97. As a result, the sum of the control line currents exceeds the threshold value I _THC only at Q _1B . Since the gate current I _g is flowing through Q _1B at this point, Q _1B switches from the zero voltage state to the voltage state. Then until now Q _1B
Almost all of the gate current flowing in Q 1A flows toward Q _1A , so that I _1A ≒I and I _1B ≒0. When the gate current of Q _1B approaches zero, Q _1B returns to the zero voltage state again. Since the sum of the control line currents of Q _1A is less than I _THC , Q _1A is still in a zero voltage state. As I _1A increases from 0 to I, the sum of control line inputs to Q _2B increases, but is still below I _THC and remains in a zero voltage state. As I _1B decreases from I to 0, the sum of the control line inputs to Q _2A decreases, but it remains below I _THC and remains in a zero voltage state.

That is, a steady state is reached when I _1A ≒I, I _1B ≒0, I _2A ≒0, and I _2B ≒I. Next, when IN advances by half a cycle and reaches 0, the current shown in column 93 flows through the control line of each element, and _Q2B causes a switch from zero voltage state → voltage state → zero voltage state, and the output The current switches. Similarly, in the 94th column, Q _1A is switched, and in the 95th column, Q _2A is switched.

In other words, for two periods of input current IN, output current
I _1A , I _1B , I _2A , and I _2B show changes of one cycle, and a frequency division operation is established.

Now, there is still room for improvement in the performance of the frequency divider shown in FIG. Let's consider the operation of the CS circuit again. Figure 9a shows the specific structure of the CS circuit, and Figure 9b shows the CS circuit.
It shows the relationship between the magnitude of circuit load inductance L ₁ or L ₂ and time τ. The switching time τ was defined as the time from the time when the input crossed the threshold of the element until the time when the output reached 90% of the steady value. In Figure 9a, 101 and 102 have a critical Josephson current of 0.2 mA and a junction capacitance of 0.8 pF.
This is a two-junction magnetic quantum interferometer consisting of two Josephson junctions. This Josephson junction uses lead alloy electrodes and has a critical current density of 1000mA/
It is realized by a Josephson junction with a diameter of 5 μm, which is cm ² . This CS circuit has a load inductance L ₂
As , the switching time τ increases as shown in the figure. If L ₂ is too small, the CS circuit will not operate, but if you are aiming for high-speed operation, it is better to keep L ₂ small.

On the other hand, in the circuit shown in FIG. 8, the inductances 80 and 81 corresponding to L ₂ must be enormous in terms of load inductance. Again, the critical Josephson current for the element is 0.2 m.
A. We will discuss numerically using an example using a two-junction magnetic quantum interferometer consisting of two Josephson junctions with a junction capacitance of 0.8 pF. All wiring is now
Assume that the width is 5 μm. The thickness of each electrode and insulating film constituting the Josephson device is based on the known example JH.
Greiner et al. “Fabrication Process for
Josephson Integrated Circuits”IBM J.Res.
According to Develop Vol.24, No.2, March, 1980.
Then, L ₁ cannot generally fall below 50PH.
Therefore, L ₂ must be 150PH, and the operation of the CS circuit becomes slower as L ₂ becomes larger.

Therefore, if we do not use both I ₁ and I ₂ in Figure 3 as output currents and instead use only I ₂ , all the inductance generated by coupling with the next stage element will be added to the L ₂ side. , L ₁ is minimized.
An embodiment in which such a concept is applied to the circuit shown in FIG. 8 will be described with reference to FIG. 10. Figure 10a
shows the configuration of the frequency divider. 111, 112, 11
3,114 is a Josephson element, and uses a two-junction magnetic quantum interferometer shown in FIG. 8b. 111 and 11
2 is 113 by the current source 115 of the gate current I _g .
and 114 are similarly driven by current source 116, respectively. 118, 119, 120, and 121 are bias currents I _b1 and 121 for the elements 111 to 114, respectively.
These are current lines that give I _b2 , I _b3 , and I _b4 . 117 is a wiring through which the input current IN flows. The difference with the circuit of FIG. 8a is that the output lines of Josephson elements 112 and 114 are directly connected to ground, while the output lines of Josephson element 111
4, and for the output line of element 113, element 1
11 and 112 to ground. In other words, the output lines of elements 111 and 113 are much longer and have greater inductance than the output lines of elements 112 and 114, so inductances 80, 81 and 82, 83 shown in FIG. 8a are unnecessary. The bias conditions will be explained using the threshold curve 122 shown in FIG. 10b. If the threshold value of the device at gate current I _g is I _THC It is. The input current IN has an offset of I/2,
The current is a sine wave or similar waveform with a peak-to-peak amplitude of I. The operation of this frequency divider is shown in FIG. 10c.

First, in the initial state, the input current IN is I,
Assume that the gate current is gradually increased from 0 to a steady-state value I. This state and the state of the control line input to each element every time IN advances by 1/2 cycle after that are shown in columns 131 to 135 as in FIG. 8e. In this case as well, the output currents I _1A and I _2A are 1 for 2 input cycles.
The period changes and normal frequency dividing operation is performed. According to this FIG. 10 embodiment, 80, 8 in FIG.
A disequilibrium inductance such as 1 is no longer necessary, thereby increasing speed.

Consider configuring a multi-bit frequency divider circuit by connecting such frequency dividers in multiple stages. The wiring method in that case must be such as to minimize the load inductance present on the input line of the next stage divider. This load inductance can be divided into contributions from the coupling portion with the next-stage frequency divider element and the wiring connecting them. As an assumption, we use a 5 μm line width as the wiring, and an asymmetric two-junction magnetic quantum element consisting of two Josephson junctions with a critical Josephson current of 0.2 mA and a junction capacitance of 0.8 PH, and an inductance of about 0.8 PH connecting them. Considering the use of an interferometer, when using the same process technology as the above-mentioned known example document (JHGreiner, et al.), the inductance at the connection with the element is approximately 20PH for one element, and the wiring inductance is approximately 20PH for each element. Approximately 1 PH per 10 μm. In normal wiring methods, the contribution of the former tends to be large. Therefore, in order to reduce the load inductance, the number of coupled load elements must be minimized. If two CS circuits constitute one frequency divider circuit and are connected in two or more stages, the load of the CS circuit in the previous stage frequency divider will be six. This slows down the frequency divider and reduces the performance of the frequency divider.

FIG. 11a shows a wiring method for a 2-bit frequency divider that can avoid such problems. One frequency divider consists of three CS circuits, two of which are used to drive the next stage. The numbers of load elements in the three CS circuits 141, 142, and 143 that constitute the frequency divider are 4, 2, and 4, respectively.
Improvements are being made. In addition, giving top priority to increasing the speed of the first frequency divider will lead to improving the operating speed of multi-stage frequency dividers, so we changed the wiring method of the first frequency divider and the second frequency divider. The length of the wiring, which is a load on the device, is kept to a minimum. Each CS circuit 141, 142, 143, 144, 145, 1 in the figure
The load inductance of 46 is approximately 125, 90, and
125, 155, 95, 155PH. However, assuming that the third frequency divider is also connected in the same type as the second frequency divider.
The load of the CS circuit 146 was determined. 147 is an input line for the divided signal current IN, and 1480, 149
0, 1500, 1510, 1520, 1530 are input lines for bias currents I _b1 , I _b2 , I _b3 , I _b4 , I _b5 , I _b6 , and 1540, 1550, 1560, 157
0, 1580, and 1590 are current sources that supply gate currents that drive the CS circuit. The bias conditions will be explained with reference to FIG. 10b mentioned above. If the threshold value of the device at gate current I _g is I _THC , then
When I _g = 0.3 mA, I _b1 to I _b4 are subject to the same restrictions as in equation (3), for example, 0.85, 0.6, 0.85,
It is set to 1.1mA. I _b5 and I _b6 are set to 0.85 and 1.1 mA. The input IN has an offset of 0.15 mA and provides a sinusoidal current with a peak-to-peak amplitude of 0.3 mA. FIG. 11b shows the simulation results when the input frequency is 16 GHz. I ₁ , I ₂ , I ₃ , and I ₄ in the figure are the output currents of the CS circuits 141, 142, 143, and 144, respectively. Normal operation is performed and the conventional example (mentioned above)
It can be seen that the performance exceeds that of Charles A. Lietchi (author).

The operation of a frequency divider configured by combining two or three CS circuits has been described above, but a similar frequency divider can also be configured by using HUFFLE as a flip-flop circuit. The basic 1-bit configuration is shown in FIG. 12a. 151, 152, 15 in the same figure
3,154 is an element that is a component of HUFFLE,
Here, an asymmetric two-junction magnetic quantum interferometer is used. Element 151 has a current control line for gate current I _g . Wiring 160 connects elements 151 and 153
In addition, wiring 161 applies bias current to elements 152 and 154, respectively. 159 is input current IN
is the wiring that flows through it. The structure of the device is shown in FIG. 12b. This device consists of Josephson junctions J1 and J2
A closed circuit is formed by an inductance L connecting these. Three control lines 165, 166, 1
67 is magnetically coupled to the inductance L. The threshold curve of this device is shown in FIG. 12c. The reason for the asymmetric threshold curve is
This is due to the same reason as in the case of CS circuits. Figure 12b
In, R _L is a load resistance, and if the quasi-particle tunnel resistance of Josephson junction J1 or J2 is R _NN , R _L is set to approximately R _NN /4R _L R _NN /2 (4). If R _L is made too large, a hang-up phenomenon will occur and the switching operation will be inhibited. On the other hand, if R _L is made smaller, switching becomes slower. Figure 12c shows the bias current I _b1 and
The method for setting I _b2 is also shown. Gate current I _g
Let the threshold values of the element be I _THC1 and I _THC2 (I _THC1 <
I _THC2 ), then I _b1 = I _b2 I _b1 +2I _g I _THC2 I _b1 +I _g I _b1 −2I _g >I _THC1 I _g =I...(5). The input current IN is a sine wave or a similar waveform with a peak-to-peak amplitude of about 2I without offset.

The operation of this frequency divider will be explained with reference to FIG. 12e. Before explaining the names of each element and output current,
Define as shown in Figure 2 d. +IN, I _b1 and +I ₂ are input to element Q _1A . Similarly, Q _1B has +IN,
I _b2 and -I ₂ are input to Q _2A , -IN, I _b1 and -I ₁ are input to Q _2B , and -IN, I _b2 and +I ₁ are input to Q 2B. When the bias currents I _b1 and I _b2 are determined as shown in Figure 12c, the input to each element changes as the input current IN changes.
It changes as shown in Figure e. First, assume that the input IN is zero as an initial state and the gate current I _g is gradually raised to a steady value. Then the bias current I _b1
Temporarily increase I _THC2 or higher, then return to the original value. Then elements Q _1A and Q _2A are in a voltage state and I ₁ +
I _g , I ₂ + I _g . In this state, when IN is raised from zero to I _g , currents as indicated by the size of each arrow in the column 181 in Figure 12e flow through the control wires of each element, and the total is 186 below. A current flows as shown by the arrow in the column, and as a result, the sum of the control line inputs exceeds I _THC2 only with Q _1A , but since Q _1A is already in a voltage state, nothing changes. . When the input IN advances for the next half cycle and reaches -I, the control line current shown in column 182 flows.
Q _2B switches, and Q _2A returns to zero voltage state as a reaction. Similarly, Q _1B is switched in column 183, Q _2A is switched in column 184, and Q _1A is switched in column 185, returning to the original event. That is, IN 2
Outputs I ₁ and I ₂ show a change of one period with respect to the period,
Frequency division operation is established.

Now, let's consider the operation of HUFFLE again.
FIG. 13 shows a specific structure of HUFFLE and the switching time τ with respect to the load inductance L in that case. In this case, τ is also defined as the time from the time when the input crosses the threshold of the element to the time when the output reaches 90% of the steady-state value. In the figure, reference numerals 191 and 192 are two-junction magnetic quantum interferometers composed of two Josephson junctions with a critical Josephson current of 0.2 mA and a junction capacitance of 0.8 pF. As shown in the figure, τ of this HUFFLE increases as the load inductance L increases. If L becomes too small, the HUFFLE operation will not occur, but in order to achieve high-speed operation, L should be small. Therefore, this point must be taken into consideration in actual circuit layout and wiring.

Consider configuring a multi-bit frequency divider by connecting such frequency dividers in multiple stages. In that case, the wiring method must be such as to minimize the inductance of HUFFLE, which constitutes the first bit. Based on the same discussion as in the case of the CS circuit, we decided on the wiring method as shown in Figure 14a. one frequency divider to three
It consists of HUFFLE, one of which is used to drive the next stage. Furthermore, the wiring methods for the first frequency divider and the second frequency divider are different. Under the same assumption as in the case of the CS circuit, each HUFFLE 201, 202,
The inductance of 203, 204, 205, 206 is approximately 130, 75, 125, 165, 105, 125PH respectively
becomes. However, the load of 206 was determined assuming that the third frequency divider is also connected in the same type as the second frequency divider. 207 is an input line for the divided signal IN;
08, 209, 210, 211 are bias currents
These are input lines for I _b1 , I _b2 , I _b3 , and I _b4 . 212, 21
3,214,215,216,217,218,
219, 220, 221, 222, 223 are each
This is a current source that supplies gate current to drive each HUFFLE. The bias conditions are the same as the above 12th
This will be explained with reference to Figure c. I _THC2 0.9mA,
I _THC1 -0.6 mA. When I _g =0.3mA
I _b1 and I _b2 are each, for example, 0.55 due to the restriction of equation (5).
mA, set to 0.55mA. I _b3 and I _b4 are both 0.8
mA. The input IN is a sinusoidal current with an amplitude of 0.5 mA peak-to-peak without offset. Figure 14b shows that the input frequency is
Simulation results for 6GHz are shown. In the figure, I ₁ , I ₂ , I ₃ , and I ₄ are HUFFLE201 and 2, respectively.
These are the output currents of 02, 203, and 204. It can be seen that normal operation is occurring.

The structure and operation of a frequency divider that combines two or three CS circuits and HUFFLE has been explained above. All of these systems use a combination of two flip-flops that operate on clock signals shifted by half a period. Other types of frequency dividers use short pulses within the switching time of a flip-flop. In this method, it is necessary to generate short timing pulses in synchronization with the input, so it cannot follow inputs with very high frequencies. However, apart from the pulse generation circuit, it is basically possible to divide the frequency by 1/4 using two flip-flops, so it may have functional advantages. The examples shown below are also used in the above-mentioned document (JH
Using the same process technology as Greiner et al.
The present invention relates to a circuit fabricated using a Josephson junction with a Josephson critical current density of 1000 A/cm ² using 5 μm wide wiring.

FIG. 15 shows the configuration and operation of a 1/4 frequency divider formed by combining a pulse generation circuit and two CS circuits. FIG. 15a is a circuit configuration diagram. In the same figure, 231, 232, 233, 234 are shown in Figure 8b.
CS circuits 239 and 240 are composed of the elements shown in FIG. 235, 236 are current sources that supply gate current I _g , 237, 238 are bias currents I _b1 ,
Wirings 241 and 242 that give I _b2 are shown in Figure 15b
This is a two-junction magnetic quantum interferometer whose structure is shown in . These 241 and 242 are connected by an inductance L of 400PH to form a closed circuit. JP has a critical current
Josephson junction with 0.2mA and 0.8PH junction capacitance,
R is a resistance of 1Ω. 246 is the wiring through which the input current IN flows, 244 and 245 are the bias currents I _b3 ,
This is the wiring that gives I _b4 , 241 to 246 and L,
JP and R together form a pulse generation circuit 250. This pulse generation circuit is described in U.S. Patent Specification No.
No. 4144465 (1979). FIG. 15b is a structural diagram of a two-junction magnetic quantum interferometer used in the pulse generation circuit 250, where J1 and J2 are Josephson junctions with a critical current of 0.4 mA and a junction capacitance of 1.6 pF, L is an inductance of 0.8 pF, and R _D is an inductance of 0.8 pF. 12
The resistance is Ω. The two control lines 254 and 255 are magnetically coupled to the inductance L. 1st
Curve 257 in FIG. 5c is the threshold curve for elements 231-234, and curve 258 in FIG.
1,242 threshold curves are shown, and the bias conditions are shown by FIGS. 15c and 15d. The amplitude of the pulse generated by the pulse generation circuit 250 is I _P
(0.2mA). In Figure 15c, I _b2 I _b1 + I _g I _b2 + I _P > I _THC ...(6). If I _g =0.3mA, I _THC
Since it is 0.9mA, I _b1 = 0.8mA and I _b2 = 0.5mA. On the other hand, in Figure 15 d Must be. If I _G =0.6mA, I _THC
Since it is 0.9mA, I _b3 = 0.75mA and I _b4 = 1.05mA.

The frequency dividing operation of the circuit of FIG. 15a will be explained with reference to FIG. 15f. Prior to this, the names of each element and output current are determined as shown in FIG. 15e. For element Q _1A -
I ₂ , I _b1 and + (current pulse) are input. similarly
Q _1B has +I ₂ , I _b2 and + (current pulse), Q _2A has +I ₁ , I _b2 and + (current pulse), Q _2B has -I ₁ and I _b1
and + (current pulse) are input. Each time a current pulse arrives, the input to each element changes as shown by the arrow in FIG. 15f. First, assume that the gate current I _g is gradually raised from zero to a steady value without applying a current pulse as an initial state. Due to the inductance of the wiring, most of I _g flows to Q _1B and Q _2B and becomes I ₁ I ₂ . On the other hand, the pulse generation circuit also gradually increases the gate current I _G from zero to a steady value. Next, when a pulse-like input with a height of I _b4 −I _b3 is applied to the input IN, the pulse generation circuit 250 is connected to the CS circuit 239 through the Josephson junction JP and the resistor R.
240 with a very short width current pulse.
At this time, the input other than the current pulse for each element is 261
As shown in the column, due to the arrival of the current pulse,
Only Q _2B switches, and the state changes as shown in column 262. Similarly, if you continue to inject the IN input,
Q _1B , Q _2A , and Q _1A switch and return to their original state.
Actually, as an IN input, the offset is 1/2 (I _b4 −
I _b3 ), the peak-to-peak amplitude is (I _b4 − I _b3 )
All you have to do is add a sine wave current of . Then part 4
With respect to the period, the output I ₁ or I ₂ shows a change of one period. In other words, a 1/4 frequency division operation is established. Input IN
The first simulation result is when a sinusoidal current with an offset of 0.15 mA, a peak-to-peak amplitude of 0.3 mA, and a frequency of 2.5 GHz is applied.
It is shown in Figure 6. In the figure, I (V11) is the current flowing through the inductance L in the pulse generation circuit 250, and I
(V12) is a current pulse supplied to the CS circuits 239 and 240 via Josephson junction JP and resistor R, I (V21) is I _g −I ₁ , I (V22) is I ₁ ,
I (V31) represents I _g −I ₂ and I (V32) represents I ₂ .

Now, a similar 1/4 frequency divider circuit can be constructed by using HUFFLE instead of the CS circuit. This will be explained with reference to FIG. FIG. 17a shows a circuit configuration diagram. In the figure, 271 to 274 are elements shown in FIG. 12b, which constitute HUFFLEs 281 and 282. Reference numerals 275 to 278 are current sources that supply the gate electrode I _g , 279 and 280 are wiring lines that provide bias currents I _b1 and I _b2 , and 250 is the pulse generating circuit shown in FIG. 15a. FIG. 17b shows elements 271 to 27.
It shows the threshold curve 283 and bias conditions of No. 4, and it must satisfy I _b1 I _b2 I _b1 + I _P + I _g > I _THC (8). I _b1 = for I _g = 0.3mA
It is sufficient to set I _b2 =0.5mA. The frequency division operation of the circuit in FIG. 17a will be explained using FIG. 17d, with the names of each element and output current defined as in FIG. 17c. In addition to the current pulses generated by the pulse generation circuit 250, the elements Q _1A , Q _1B , and Q _2A Q _2B each receive an I ₂ +
I _b1 , −I ₂ +I _b2 , −I ₁ +I _b1 , and I ₁ +I _b2 are input. Each time a current pulse arrives, the input of each element is
It changes as shown by the arrow in Figure 7d. First, assume that the gate current I _g is gradually raised from zero to a steady value without applying a current pulse as an initial state. here
Temporarily make I _b1 higher than I _THC and switch Q _1A and Q _2A . At this time, the inputs of each element are as shown in column 291, and when the current pulse arrives, only _Q2B is switched, and the state becomes as shown in column 292. Similarly, each time a current pulse arrives, Q _1B , Q _2A ,
Q _1A switches and returns to its original state. That is, the outputs I ₁ and I ₂ show a change of one cycle for four cycles of the input IN. That is, 1/4 cycle operation is established. The first simulation result is when a sinusoidal current with no offset, peak-to-peak amplitude of 0.3 mA, and frequency of 2.5 GHz is applied as input IN.
It is shown in Figure 8. Curve I (V11) in the figure is the current flowing through the inductance L in the pulse generation circuit 250, I (V12) is the Josephson junction JP, and the resistance R
Current pulses supplied to HUFFLE281, 282 through I (V21) are outputs I ₁ , I (V31)
represents the output I ₂ .

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide a frequency divider that is made of a Josephson logic circuit and operates at a frequency of 16 GHz, and in that case, the power consumption per bit is equal to the power consumption in the power supply resistor network. The input current required for operation is extremely small at a peak value of 0.1 to 0.3 mA, making it possible to achieve higher speeds, lower power consumption, and higher performance than conventional frequency dividers made of semiconductor elements. Sensitization can be achieved. The frequency divider of the present invention also has the effect of being less likely to malfunction.

[Brief explanation of drawings]

Figure 1 is a diagram showing the power supply current waveform used in a conventional AC-driven Josephson circuit, Figure 2 is a threshold curve diagram of a Josephson element, Figure 3 is a configuration diagram of a CS circuit, and Figure 4 is a diagram of a CS circuit. Operation explanation diagram, Figure 5 is a configuration diagram of the HUFFLE logic gate, Figure 6 is a diagram of the configuration of the HUFFLE logic gate.
An explanatory diagram of the operation of the HUFFLE logic gate. FIG. 7 is a diagram showing an example of a frequency divider constructed using conventional semiconductor technology. FIGS. 8 to 18 are explanatory diagrams of embodiments of the present invention. A frequency divider using a circuit and an explanation diagram of its operation, Figure 9 is a characteristic diagram of a CS circuit, Figure 10 is a frequency divider using an improved CS circuit and an explanation diagram of its operation,
Figure 11 is a diagram to explain the wiring and operation of a 2-bit CS frequency divider, Figure 12 is a diagram to explain the frequency divider using HUFFLE and its operation, Figure 13 is a characteristic diagram of HUFFLE,
Fig. 14 is a diagram illustrating the connection and operation of a 2-bit HUFFLE frequency divider, Fig. 15 is a diagram illustrating a 1/4 frequency divider using a CS circuit and its operation, and Fig. 16 is a diagram illustrating an example of its operation. FIG. 17 is an explanatory diagram of a 1/4 frequency divider using HUFFLE and its operation, and FIG. 18 is a diagram showing an example of its operation. 71, 72, 73, 74, 111, 112, 1
13,114,151,152,153,154
... Josephson element consisting of a two-junction magnetic quantum interferometer, 75, 76, 115, 116, 1540,
1550, 1560, 1570, 1580, 15
90,155,156,157,158,212
~223... Current source providing gate current, 77,
117, 147, 159, 207...Input line, 7
8,79,1480,1490,1500,15
10,1520,1530,160,161,2
08-211...Bias current line, 141-14
6,239,240...CS flip-flop,
201～206,281,282...HUFFLE
Flip-flop, 250...Current pulse generation circuit.

Claims (1)

[Claims] 1. A first device having a first and a second Josephson element;
a second flip-flop circuit having third and fourth Josephson elements; and means for applying a bias current to the first to fourth Josephson elements; A DC-driven Josephson frequency divider formed by interconnecting circuits, wherein the first to fourth Josephson elements are:
Each of the first to fourth Josephson elements includes a Josephson junction therein;
Each of the Josephson elements is configured to receive a frequency-divided input signal and a signal from a flip-flop circuit different from the flip-flop circuit to which the Josephson element belongs, and the bias current is applied to each of the first to fourth Josephson elements. The sum of the frequency-divided input signal and the signals from the different flip-flop circuits determines the threshold value of the Josephson element in the order of the first Josephson element - the third Josephson element - the second Josephson element - the fourth Josephson element. A DC-driven Josephson frequency divider, which is characterized by being set so as to exceed. 2. Claim 1, characterized in that either a current steering circuit or a hybrid unlatching flip-flop logic element is used as the first and second flip-flop circuits. DC-driven Josephson frequency divider. 3. The DC-driven Josephson frequency divider according to claim 1 or 2, wherein a pulse signal from a DC-driven Josephson pulse generation circuit is used as the frequency-divided input signal. 4. The DC-driven Josephson frequency divider according to claim 1, 2, or 3, characterized in that a plurality of the DC-driven Josephson frequency dividers are connected in series to form a multi-bit configuration. . 5. Claims characterized in that each of the cascade-connected frequency dividers has a third flip-flop circuit, and the third flip-flop circuit is used as a DC-driven buffer gate for driving the next bit. 4. The DC-driven Josephson frequency divider according to item 4.