JPH028515B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a clamp circuit for regenerating a DC component used when converting a television signal into a digital signal.

(Prior Art) When a television signal such as an NTSC signal is converted into a digital signal by an A/D converter, the dynamic range of the television signal input to the A/D converter is The DC component of the television signal must be regenerated to match the dynamic range of the converter.

That is, in the transmission of television signals, only the alternating current signal is often transmitted because it is technically easy. As a result, the DC component from the television signal is lost, and the black level becomes inconsistent. This lost DC component is compensated for, and the A/D
In order to effectively quantize the television signal within the dynamic range of the converter, it is necessary to perform DC component regeneration to equalize the black level.

To meet these demands, keyed clamp circuits have been commonly used that regenerate the DC component by using a pulse synchronized with the horizontal synchronization signal as a clamp pulse and making the tip or pedestal part of the horizontal synchronization signal constant. It's here. FIG. 1 shows an example of a conventional configuration of a keyed clamp circuit that stabilizes the DC component in the pedestal portion.

In Figure 1, the input terminal 10 has an analog
A television signal is input. This television signal is split into two branches, and one analog adder circuit 1
After being added to the output of the D/A converter 11 by the A/D converter 13, the signal is converted into a digital signal and taken out to the output terminal 14, and then added to the synchronization separation circuit 15. Pedestal extraction circuit 16
is a circuit that extracts only the digital signal corresponding to the pedestal of the television signal from among the digital signals obtained by the A/D converter 13 based on the synchronization signal separated by the synchronization separation circuit 15. .

The digital value corresponding to the pedestal level extracted in this manner is input to the pedestal level calculation circuit 17, and the digital value Vp corresponding to the pedestal level is calculated. The digital value Vp output from this arithmetic circuit 17 is
The signal is input to a digital calculation circuit 18, and the difference between Vp and a reference digital value Vpo (referred to as a reference level), which is the output of a reference level generation circuit 19, is calculated. The output of the arithmetic circuit 18 is input to the D/A converter 11 via the digital integration circuit 20. Oscillator 21 supplies a sampling clock to A/D converter 13.

The clamp circuit configured in this manner includes an addition circuit 12, an A/D converter 13, a pedestal extraction circuit 16, a pedestal level calculation circuit 17, a subtraction circuit 18, a reference level generation circuit 19, an integration circuit 20,
The D/A converter 21 forms an automatic control loop whose target value is the reference level Vpo. Therefore,
The digital value Vp corresponding to the pedestal level at the output of the A/D converter 13 is the reference level.
The control loop operates to match Vpo.
In other words, the D/A converter 11
The outputs of are added as a DC component in an adder circuit 12,
By matching the pedestal level Vp' (analog value) of the television signal input to the A/D converter 13 with its reference level Vpo' (analog value corresponding to the digital reference level Vpo), the DC component is regenerated. do.

(Problem to be solved by the invention) In the conventional keyed clamp circuit described above,
A digital value corresponding to the pedestal level Vp' of the television signal input to the A/D converter 13
A digital error signal E is calculated by comparing Vp with a digital reference level Vpo. For this reason, there is a dead zone in the level comparison characteristic due to the quantization accuracy of the A/D converter 13, and due to the existence of this dead zone, it is theoretically impossible to reduce the clamp level fluctuation (level jitter) to zero. . This problem will be explained in detail below.

In the keyed clamp circuit shown in FIG. 1, the pedestal level Vp' of the analog television signal input to the A/D converter 13 is set at Even if it fluctuates between the threshold values, the digital value of the pedestal portion in the output of the A/D converter 13 does not change. Therefore, an analog error signal is the difference (Vp' - Vpo') between the pedestal level Vp' of the television signal input to the A/D converter 13 and the analog value Vpo' corresponding to the digital reference level Vpo. E′ is
2 depending on the quantization step of the A/D converter 13
Even if the digital error signal E fluctuates between the levels ΔVo between the two threshold values, the digital error signal E does not change, and during this period the loop gain of the control loop in the keyed clamp circuit becomes zero.

FIG. 2 shows the level comparison characteristics of the control loop in the keyed clamp circuit of FIG. 1. As shown in FIG. 2, the digital error signal E is the analog error signal E'(=Vp'-Vpo').
2 depending on the quantization step of the A/D converter 13
It changes stepwise every time the level ΔVo between the two thresholds changes, and becomes zero at a point corresponding to a certain threshold.

In this case, the digital error signal E becomes zero.
The range of Vp'-Vpo' is ΔVo, and even if the pedestal level Vp' changes within this range, the clamp level is not controlled because the loop gain of the control loop is zero. As a result, the pedestal level Vp', which is the clamp level, causes a level jitter of ΔVo at the maximum. Such level jitter in the clamp level is added to the television signal as noise, causing significant deterioration.

The present invention has been made in view of these points, and its purpose is to provide a clamp circuit that can perform DC component regeneration necessary when converting a television signal into a digital signal without causing level jitter at the clamp level. Our goal is to provide the following.

(Means for Solving the Problems) The present invention provides a digital value of a digital error signal that changes in a stepwise manner, which is an error signal of a clamp level (pedestal level or synchronization signal level) with respect to a predetermined reference level. The present invention is characterized in that it is provided with means for always adding a constant minute digital value smaller than one step of the value.

(Function) When a minute digital value smaller than one step is added to the digital error signal, the level comparison characteristic indicating the relationship between the difference between the clamp level and the reference level and the digital error difference signal changes in the direction of the digital level of the digital error signal. Shift by minute digital value. As a result, the control loop operates under bang-bang control in which the digital error signal alternately takes two positive and negative values, during which time the difference between the clamp level and the reference level is kept constant.

Therefore, in principle, level jitter at the clamp level does not occur, and even if it does occur, it is suppressed to an amount sufficiently smaller than the level range depending on the quantization step of the A/D converter.

(Example) Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3 is a block diagram showing the configuration of a clamp circuit according to an embodiment of the present invention, which has a configuration in which a digital generator circuit 30 and a digital adder circuit 31 are added to the clamp circuit of FIG.

That is, the digital level generating circuit 30 generates a certain minute digital value, specifically, the digital error signal E in the level comparison characteristic shown in FIG.
This circuit generates a digital value Δe smaller than one step Δ of . Now, if the number of quantization bits of the A/D converter 13 is 8 bits, one step ΔE of the digital error signal E is 1/1 of the full case of the television signal input to the A/D converter 13.
Represents 2 ⁸ . In other words, ΔE is expressed by the least significant bit of an 8-bit digital signal.

At this time, if the D/A converter 11 has a conversion accuracy (number of input bits) of 9 bits or more and the upper 8 bits are used as the digital error signal E, the digital level generating circuit 30 generates the signal. A digital value Δe smaller than ΔE can be represented by the 9th bit or less counting from the most significant bit. In short, if the conversion accuracy of the D/A converter 11 is n bits and the effective number of bits of the digital error signal E is m (m<n), the digital value Δe
is assigned nm bits.

The digital addition circuit 31 adds the digital signal of the digital value Δe from the digital level generation circuit 30 and the digital error signal E which is the output of the digital subtraction circuit 18. The output signal of this digital addition circuit 31 is then supplied to the digital integration circuit 20.

The level comparison characteristic of the clamp circuit configured in this way, that is, the relationship between the difference Vp'-Vpo' between the pedestal level Vp' and the reference level Vpo' and the digital error difference signal E is as shown in FIG. Become. This level comparison characteristic is based on the level comparison characteristic of the conventional clamp circuit shown in FIG. It will be shifted by that amount.

Here, since the digital value Δe is less than one step ΔE in the stepped level comparison characteristic as described above, the line parallel to the vertical axis of the level comparison characteristic as shown in FIG. ′＝
At the position of ΔVo/2, it intersects the horizontal axis (axis of Vp'-Vpo'), that is, the line of E=0.

Therefore, the control operation in this clamp circuit is bang-bang control in which the digital error signal E alternates between a value of +Δe and a value of −ΔE+Δe at the position of Vp′−Vpo′=−ΔVo/2. ,
Vp'−Vpo' works to converge to ΔVo/2.

bang-bang control
Also called two-positions control or on-off control, in an automatic control system, the manipulated variable to obtain the controlled variable is divided into two depending on the control deviation (deviation of the controlled variable from the target value). This is a control that alternates between two states (there is no stable point between the two states). When such control is performed, the actual manipulated variable becomes an intermediate value between the two states due to temporal averaging. In this embodiment, the clamp level corresponds to the control amount, the digital error signal E corresponds to the manipulated variable, and Vp'-Vpo' corresponds to the control deviation.

As a result of such bang-bang control, the digital error signal E is no longer stable at zero as in the past, but instead has two values, +Δe and -ΔE+Δe, alternately, and the loop gain of the control loop becomes infinite. Becomes large. In this case, the pedestal level Vp' of the television signal input to the A/D converter 13, which is the clamp level, is stabilized with a constant error of -ΔVo/2 with respect to the reference level Vpo'. Therefore, its temporal fluctuation (level jitter) is, in principle, zero.

That is, in the conventional clamp circuit shown in FIG.
However, according to the present invention, such level jitter caused by the quantization step of the A/D converter 13 does not exist in principle, and even if the level jitter occurs, , is sufficiently smaller than ΔVo.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, a case has been explained in which a positive level digital signal is generated from the digital level generation circuit 30, but even if a negative level digital signal is generated, the steady error will only be +ΔVo/2. Similarly, level jitter in the clamp level is reduced by bang-bang control.

Further, in the above embodiment, the synchronization separation circuit 15 is connected to the input terminal 10 to separate the synchronization signal from the television signal in the form of an analog signal. It is also possible to separate the synchronization signal from the digitized television signal by connecting the two.

Furthermore, in the above embodiment, in order to make the control loop non-localized, the digital error signal E is input to the D/A converter 11 via the integrating circuit 20.
It is also possible to remove the integrating circuit 20 and make it non-local. Furthermore, a loop filter made of a digital circuit may be inserted between the integrating circuit 20 and the D/A converter, or a loop filter made of an analog circuit may be inserted between the D/A converter 11 and the addition circuit 12. This also makes it possible to further reduce jitter.

Further, in the above embodiment, the case where the pedestal level is used as the clamp level has been described, but the present invention can also be applied to a clamp circuit that uses the synchronization signal level (tip level) as the clamp level. In that case, the pedestal level extraction circuit 16,
The pedestal level calculation circuit 17 may be replaced with a synchronization signal extraction circuit and a synchronization signal level calculation circuit, respectively.

(Effects of the Invention) As described above, according to the present invention, the level jitter of the clamp level can be significantly reduced, and it is extremely effective in reproducing the DC component when A/D converting a television signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional keyed clamp circuit, FIG. 2 is a diagram showing level comparison characteristics of the clamp circuit of FIG. 1, and FIG. 3 is a block diagram of a clamp circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing the level comparison characteristics of the clamp circuit of FIG. 3. 11...D/A converter, 12...Analog addition circuit, 13...A/D converter, 15...Synchronization separation circuit, 16...Pedestal extraction circuit, 17...Pedestal level calculation circuit, 18... Digital subtraction circuit, 19...Reference level generation circuit, 20...
Integrating circuit, 21... oscillator, 30... digital level generation circuit, 31... digital addition circuit.

Claims (1)

[Claims] 1. An A/D converter that converts a television signal into a digital signal, and a digital value corresponding to the pedestal level or synchronization signal level of the television signal from the output signal of the A/D converter. means for obtaining an error signal with respect to a reference level of the digital value obtained by this means as a digital value that changes in a stepwise manner; means for adding a constant smaller digital value; and a digital signal converter for converting the digital value to which the digital value has been added into an analog signal.
A clamp circuit comprising: an A converter; and means for adding an output signal of the D/A converter to a television signal input to the A/D converter.